In digital communication systems symbol timing recovery is of fundamental importance. The accuracy in estimation of symbol timing has a direct effect on received data error rates. The primary objective of this thesis is to implement a practical Digital Phase Locked Loop capable of accurate synchronisation of symbols suffering channel corruption typical of modern mobile communications. This thesis describes an all-software implementation of a Digital Phase Locked in a real-time system. A timing error detection (TED) algorithms optimally implemented into a Digital Signal Processor. A real-time transmitter and receiver system is implemented in order to measure performance when the received signal is corrupted by both Additive White Gaussian Noise and Flat Fading. The Timing Error Detection algorithm implemented is a discrete time maximum likelihood one known as FFML1, developed at Canterbury University. FFML1 along with other components of the Digital Phase Locked loop are implemented entirely in software, using Motorola 56321 assembly language.

Les oscillateurs sont des blocs qui figurent dans presque tous les circuits. En effet,ils sont utilisés pour générer les signaux de synchronisation (les horloges), les signauxmodulés et démodulés ou récupérer des signaux noyés dans du bruit (détection synchrone).Les caractéristiques de ces oscillateurs dépendent de l'application. Dans le cas des boucles àverrouillage de phase (PLL), il existe de fortes exigences en matière de stabilité et de bruitde phase. En outre, face aux avancées des technologies nanométriques, il est égalementnécessaire de prendre en compte les effets liés à la variabilité des procédés de fabrication.Aujourd'hui, de nombreuses études sont menées sur les oscillateurs asynchrones en anneauqui présentent des caractéristiques bien adaptées à la gestion de la variabilité et qui offrentune structure appropriée pour limiter le bruit de phase. A ce titre, les anneaux asynchronessont considérés comme une solution prometteuse pour générer des horloges.Cette thèse étudie les avantages et les potentiels offerts par les oscillateursasynchrones en anneau. Deux applications principales ont été identifiées. D'une part, cesoscillateurs sont une solution prometteuse pour la génération d'horloges polyphasées àhaute fréquence et à faible bruit de phase. D'autre part, ils constituent une alternativesimple, dans une certaine mesure aux oscillateurs plus conventionnels et aux DLLs, car ilssont programmables en fréquence numériquement et sont susceptibles de fournir lesfonctionnalités d'arrêt de type gated clock de façon native. Plusieurs oscillateurs ont étéconçus, implémentés, fabriqués en technologie CMOS 65 nm de STMicroelectronics et,finalement, caractérisés sous pointes. Ces travaux ont notamment permis de démontrer lapertinence de ces oscillateurs, qui constituent une alternative sérieuse aux très classiquesoscillateurs en anneau à base d'inverseurs.

Στόχος της διπλωματικής εργασίας είναι η σχεδίαση ενός συστήματος που να επιτρέπει την μελέτη των τεχνικών Σύνθεσης Συχνοτήτων με βρόχο κλειδωμένης φάσης μέσω του RMCLab. Στη παρούσα διπλωματική εργασία μελετήθηκε και σχεδιάστηκε το κατάλληλο υλικό (hardware) και λογισμικό (software) έτσι ώστε να δίνεται η δυνατότητα μελέτης του βρόχου σύνθεσης συχνότητας χωρίς κανένα ουσιαστικό περιορισμό. Ο χρήστης του συστήματος που κατασκευάστηκε σ’ αυτή τη διπλωματική εργασία μπορεί να μελετήσει βρόχους σύνθεσης συχνοτήτων που υλοποιούνται με όλες τις γνωστές μέχρι σήμερα τεχνικές (πχ: Integer N, Fractional, ΣΔ), ή ακόμη να εφαρμόσει δικές του τεχνικές ή νέες, πρόσφατες τεχνικές όπως αυτή του DIPA. Μπορεί επιπλέον να σχεδιάσει και να χρησιμοποιήσει τους δικούς του διαιρέτες συχνότητας, τον δικό του phase/frequency comparator και ακόμη να επιλέξει μέσα από μία ευρεία περιοχή στοιχείων (αντιστάσεις πυκνωτές) για την υλοποίηση του φίλτρου του συνθέτη. Εκτιμούμε ότι το αποτέλεσμα αυτής της διπλωματικής εργασίας θα συμβάλει σημαντικά στην κατανόηση του βρόχου κλειδωμένης φάσης και του συνθέτη συχνοτήτων από τους φοιτητές, και επιπλέον θα διευκολύνει σημαντικά την υλοποίηση και πειραματική επιβεβαίωση νέων διατάξεων βασισμένων σε βρόχο κλειδωμένης φάσης. / The aim of this dissertation is the development and implementation of the appropriate hardware and software for enabling the study of the PLL based frequency synthesis techniques using the facilities of the RMCLab (Remote Monitored and Controlled Lab.). The RMCLab user is now able to study deeply on the well known techniques of frequency synthesis as Integer N, Fractional or ΣΔ, since the developed system enables him to access and customize any of the synthesizer components (dividers, phase/frequency detector, filter). Additionally, the system allows the user to apply new appeared frequency synthesis techniques such as the DIPA technique, or even to develop and experiment on his own ideas regarding frequency synthesis. It is anticipated that the system developed under this dissertation will enable students to deeply understand on the theory of phase locked loop and practice on various frequency synthesis techniques.

Αντικείμενο της παρούσης διπλωματικής εργασίας είναι ο σχεδιασμός ενός συνθέτη συχνοτήτων για MB-OFDM (Multiband Orthogonal Frequency-Division Multiplexing) UWB εφαρμογές. Ο συνθέτης συχνοτήτων αποτελεί εξέχουσας σημασίας δομικό στοιχείο των RF πομποδεκτών αφού είναι υπεύθυνος για την παραγωγή του (LO oscillator) σήματος που οδηγεί τον downconverter και τον upconverter στο μονοπάτι του δέκτη και του πομπού αντίστοιχα. Μελετήθηκαν οι δομές, οι κυριότερες τοπολογίες και τα χαρακτηριστικά ενός τυπικού συνθέτη συχνοτήτων καθώς και τα κύρια εξαρτήματα που το απαρτίζουν. Αφού μελετήσαμε το βασικό και το εναλλακτικό σχέδιο συχνοτήτων όπως παρουσιάζεται από το MB-OFDM πρότυπο προτείναμε την κατάλληλη τοπολογία η οποία και διαφέρει από αυτή των τυπικών συνθετών συχνοτήτων που χρησιμοποιούνται ευρέως στα ασύρματα συστήματα τηλεπικοινωνιών λόγω των υψηλών απαιτήσεων της UWΒ τεχνολογίας. Η επιλογή των εξαρτημάτων που απαρτίζουν τον συνθέτη συχνοτήτων έγινε με βάση την ελαχιστοποίηση του θορύβου φάσης και της κατανάλωσης ισχύος, της εξάλειψης ανεπιθύμητων σημάτων στην έξοδό του, τα οποία μπορούν να δημιουργήσουν παρεμβολές σε άλλα τηλεπικοινωνιακά συστήματα καθώς και την επίτευξη μικρού χρόνου αποκατάστασης που απαιτεί ένας τέτοιος συνθέτης. Προτείνεται και εξομοιώθηκε λοιπόν συνθέτης συχνοτήτων με περιοχή λειτουργίας του από 3.1 έως 10.6 GHz με βήμα συχνότητας 528 MHz όπως αυτή ορίζεται από το πρότυπο 802.15.3 που αναφέρεται στην UWB τεχνολογία. Από τα αποτελέσματα της εξομοίωσης προκύπτει ότι επιτυγχάνεται χαμηλός θόρυβος φάσης, μικρός χρόνος αποκατάστασης και μικρή ισχύς των ανεπιθύμητων σημάτων, αποτελέσματα που συνάδουν με τις απαιτήσεις της UWB τεχνολογίας. Τέλος προτείνεται και υλοποιείται η πλακέτα του βρόχου κλειδωμένης φάσης ο οποίος και αποτελεί το βασικό δομικό στοιχείο του συνθέτη συχνοτήτων. / The subject of the present essay is the design of a frequency synthesizer for MB-OFDM (Multiband Orthogonal Frequency-Division Multiplexing) UWB applications. The frequency synthesizer is a structural part of foremost importance at the RF transceivers, as it is responsible for the production of the signal (LO oscillator) that leads the downconverter and the upconverter at the path of the receiver and the transmitter correspondingly. Structures, principal topologies and a typical’s frequency synthesizer characteristics have been studied, as well as the main components that compose it. After having studied the current and the alternate frequency plan –as presented by MB-OFDM standard-, we proposed the proper topology, which is different from the one for the typical frequency synthesizers, that are widely used at the RF communication systems, due to UWB technology’s high specifications. The choice of the components that compose the frequency synthesizer is based on the minimization of the phase noise and the power consumption, on the reduction of spurious signals during its entrance, which can create interferences to other communicational systems, as well as on the accomplishment of a short settling time, which a synthesizer of this kind demands. So, a frequency synthesizer with a frequency range from 3.1 to 10.6 GHz, with a frequency step of 528 MHz -as it is defined from the standard 802.15.3 that is referred at UWB technology-, has been proposed and simulated. From the results of the simulation, it emerges that a low phase noise is accomplished, a short settling time and a low power of spurious signals, results that add up to UWB technology’s specifications. Finally, the PCB (printed circuit board) of the phase locked loop - which consists the basic structural part of the frequency synthesizer - has been proposed and implemented.

Στην παρούσα Διπλωματική Εργασία μελετάται η αρχιτεκτονική και τα χαρακτηριστικά ενός νέου συνθέτη συχνοτήτων (Frequency Synthesizer) που βασίζεται στην τεχνική του βρόχου κλειδωμένης φάσης (Phase-Locked Loop). Η νέα αρχιτεκτονική ξεπερνά την δυσκολία του απλού συνθέτη συχνοτήτων να έχει ταυτόχρονα μικρό βήμα συχνότητας και μικρό χρόνο κλειδώματος, ενώ ταυτόχρονα διατηρεί και επαυξάνει την δυνατότητα των απλών συνθετών να απορρίπτουν τον θόρυβο φάσης, δίνοντας έτσι πολύ καλή ποιότητα σήματος εξόδου. Τα χαρακτηριστικά αυτά καθιστούν τον νέο συνθέτη πολύ ανταγωνιστικό. / This Diploma Thesis studies the architecture and the characteristics of a new Frequency Synthesizer which based on the Phase-Locked Loop technique. This new architecture overcomes the difficulty of the simple frequency synthesizer to have simultaneously small frequency step and small locking time, while maintains and enhances the possibility to reject phase noise. This concludes to the high quality of the output signal. The above characteristics make the new synthesizer very competitive.

Phase locked loop (PLLs) are the keystone for the electronic as well as for the communication circuits. Without any exaggeration, PLLs are found almost in every electronic and communication devices. Countless research has been performed, for the modification and enhancement of the PLLs circuit. While, due to the numerous advantage of the digital circuitry, the recent research is focusing on the all digital implementation of the PLLs. Therefore, it was competitive to touch with burning research. Low power and wide range all digital phase locked loop (ADPLL), for video applications is presented. ADPLL has an operating input frequency between 10kHz to 150 kHz and output frequency between 10 MHz to 300 MHz. The phase frequency detector (PFD) is based on D-flip flops, having two output error and direction signal. The traditional charge pump (CP) is replaced by time-to-digital converters (TDC) and analog low pass filter (LPF) by digital low pass filter (digital-LPF). For completely digital architecture, voltage controlled oscillator (VCO) is replaced by the digitally controlled oscillator (DCO). In DCO, eleven bits are dedicated for controlling bits, two bits for biasing and one bit for enable the DCO. The designed steps for ADPLL were almost similar to the designed steps of a second order analog PLL. The ADPLL is implemented on a CMOS 65-nm technology.

Este trabalho tem por objetivo apresentar uma nova forma de analisar as redes de sincronismo de fase mutuamente conectadas. Estas redes são formadas por Phase-Locked Loops digitais ou DPLLs. O sinal gerado por cada DPLL é enviado a todos os demais dispositivos, formando a rede mutuamente conectada. Parte-se do pressuposto de que as ligações entre os dispositivos são dotadas de atrasos, o que dificulta o tratamento do problema. No entanto, é apresentado aqui um método para análise das malhas de sincronismo via discretização do modelo de tempo contínuo, objetivando dirimir essa dificuldade, já que atrasos são facilmente representados em modelos de tempo discreto. Para tanto, o modelo da rede no espaço de estados é equacionado a partir da rede. Esse modelo no espaço de estados é, então, discretizado e, enfim, pode-se determinar o estado síncrono da rede incluindo a freqüência de sincronismo e analisar sua estabilidade. Como se poderá constatar, escolhendo um período de amostragem adequado, pode-se representar o comportamento das redes de sincronismo com modelos discretos, obtendo elevado grau de precisão. / This work introduces a new method for studying a mutually-delayed-connected network of Digital Phase-Locked Loops DPLLs. The signal generated by a DPLL in the network is sent to all other devices in this same network. Because of delayed signals, it is difficult to treat this problem. So, its shown here a method for analyzing the networks via discretization of continuous time delay model in order to deal with this issue easily, considering that delays are naturally represented in discrete time models. First of all, a continuous state space model is obtained from mutually-connected network. Then, this model is discretized and, finally, the synchronous state can be determined and the stability can be analyzed. As shown below, choosing a proper time sample, the behavior of mutually-delayed-connected networks can be approximately represented by a discrete time model.

Conselho Nacional de Desenvolvimento CientÃfico e TecnolÃgico / Este trabalho apresenta o desenvolvimento de um sistema de conversÃo de energia eÃlica (WECS - Wind Energy Conversion System) com gerador sÃncrono de imà permanente (PMSG - Permanent Magnet Synchronous Generator) operando com velocidade variÃvel. O circuito de processamento de energia à dividido em dois estÃgios. No estÃgio AC-DC, uma topologia boost bridgeless trifÃsica unidirecional absorve a energia fornecida pelo gerador e injeta no link DC. Neste conversor, a tÃcnica de autocontrole permite a extraÃÃo de corrente com baixa taxa de distorÃÃo harmÃnica (THD â Total Harmonic Distortion) e alto fator de potÃncia. AlÃm disso, um algoritmo de rastreamento do mÃximo ponto de potÃncia (MPPT - Maximum Power Point Tracking) determina a velocidade de rotaÃÃo do gerador que irà garantir o ponto adequado de operaÃÃo. Este modo de operaÃÃo à mantido enquanto a potÃncia disponÃvel for menor que a potÃncia nominal do conversor. Caso contrÃrio, o algoritmo de MPPT à desabilitado e uma malha de controle de potÃncia mecÃnica garante a condiÃÃo nominal de potÃncia. No estÃgio de conversÃo DC-AC, um inversor trifÃsico ponte completa, cujo controle à baseado na teoria das potÃncias instantÃneas, provà energia à rede elÃtrica cumprindo com as exigÃncias normativas. Uma anÃlise teÃrica completa à apresentada assim como os resultados de simulaÃÃo considerando o protÃtipo com a potÃncia nominal de 6 kW equivalente a turbina eÃlica utilizada. Resultados experimentais satisfatÃrios sÃo apresentados para uma potÃncia de 3 kW: o rendimento do sistema completo à superior a 90%; a corrente que circula no gerador apresenta THD de aproximadamente 2,6% e fator de potÃncia de 0,942; e a corrente injetada na rede elÃtrica possui THD de 1,639% e fator de potÃncia de 0,994. / This master thesis presents the development of a Wind Energy Conversion System (WECS) with Permanent Magnet Synchronous Generator (PMSG) operating at variable speed. The energy processing circuit is divided into two stages. In the AC-DC stage, an unidirectional three-phase bridgeless boost topology absorbs the energy supplied by the generator and injects it into the DC link. In this converter, the self-control technique allows the current extraction with low THD and high power factor. Furthermore, a - Maximum Power Point Tracking (MPPT) determines the rotational speed of the generator that will ensure the proper operating point. This mode of operation is maintained while the available power remains lower than the converter rated power. Otherwise, the MPPT algorithm is disabled and a mechanical power control loop ensures the rated power condition. On the DC-AC conversion stage, a three-phase full-bridge inverter, whose control is based on the theory of instantaneous power, provides energy to the grid complying with regulatory requirements. A complete theoretical analysis is presented as well as the simulation results considering the prototype with a rated power of 6 kW equivalent of wind turbine used. Satisfactory experimental results are shown to an output of 3 kW: the efficiency of the total system is above 90%; the current through the generator has a THD of about 2.6% with a power factor of 0.942; moreover, the current injected into the grid has a THD of about 1.639% and a power factor of 0.994.

Neste tabalho à realizado o estudo de um conversor de trÃs nÃveis com ponto neutro grampeado (NPC), proposto para a interligaÃÃo de sistemas de conversÃo de energia à rede elÃtrica. Para tanto à utilizado um filtro indutivo L, tÃcnicas de controle vetorial, e a tÃcnica PLLcomo mÃtodo de sincronismo. SÃo desenvolvidas equaÃÃes para a determinaÃÃo das perdas do conversor, as quais podem ser aplicadas a diversas tÃcnicas de modulaÃÃo PWM. TrÃs tÃcnicas sÃo apresentadas: modulaÃÃo PD; modulaÃÃo com injeÃÃo de terceiro harmÃnico (THIPWM); e modulaÃÃo vetorial baseada em portadora (CB-SVPWM). Toda a modelagem do sistema à apresentada, bem como um exemplo de projeto para um sistema de 6 kW.SÃo realizadas simulaÃÃes computacionaispara diferentes estudos de caso, validando o projeto do conversor e a modelagem desenvolvida. A resposta Ãs dinÃmicas do sistema à satisfatÃria, sendo o conversor capaz de controlar o fluxo de potÃncia ativa (com fator de potÃncia uniÃrio) e reativa entregues à rede. / This work deals with the study of a three-level inverter with Neutral Point Clamped (NPC), proposed for the interconnection of energy conversion systems to the grid. In order to accomplish a complete study, an inductive filter L is proposed, as well as vector control techniques and a PLL synchronization method. Equations are developed for the determination of the losses of the converter, which can be applied to various PWM techniques. Three Modulation techniques are presented: Phase Disposition modulation(PD), modulation with injection of the third harmonic (THIPWM) and carrier-based space vector modulation (SVPWM-CB). The complete modeling system is presented, as well as an example for designing a system of 6 kW. Numerical simulations are performed for different study cases, validating the converter design and modeling developed. The simulation results show that the proposed NPC converter is fully satisfactory, the converter being able to control the active (unity power factor) and reactive power flow delivered to the grid.

Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-03-21T18:37:34Z No. of bitstreams: 1 pedrohenriquedecastrogomes.pdf: 1205999 bytes, checksum: b3d28e019c29c4bb978f107c4b25c3ef (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-03-22T12:40:06Z (GMT) No. of bitstreams: 1 pedrohenriquedecastrogomes.pdf: 1205999 bytes, checksum: b3d28e019c29c4bb978f107c4b25c3ef (MD5) / Made available in DSpace on 2017-03-22T12:40:06Z (GMT). No. of bitstreams: 1 pedrohenriquedecastrogomes.pdf: 1205999 bytes, checksum: b3d28e019c29c4bb978f107c4b25c3ef (MD5) Previous issue date: 2007-08-22 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / A crescente demanda pelos consumidores por índices de qualidade de energia cada vez mais elevados e a recente desregulamentação do setor elétrico, vem exigindo uma demanda cada vez maior pelo monitoramento da qualidade da energia elétrica pelas concessionárias de uma maneira descentralizada. Aliado a esse fato, a alta proliferação de cargas não lineares conectadas à rede elétrica, entre outros, têm tornado a estimação de parâmetros dos sinais elétricos da rede uma tarefa cada vez mais desafiadora. Assim, o desenvolvimento de algoritmos de estimação eficientes e com baixa complexidade computacional, ou passíveis de implementação em sistemas (hardwares) de baixo custo, têm-se tornando uma prerrogativa importante. Nesse escopo, essa dissertação apresenta a descrição de uma malha de PLL (Phase-Locked-Loop) robusta (ER-QPLL), capaz de estimar os parâmetros (fase, freqüência e amplitude) da componente fundamental de um sinal de entrada qualquer. O desenvolvimento da estrutura baseou-se no aprimoramento de uma malha de PLL do tipo quadratura (QPLL), que estima os parâmetros da componente fundamental de um sinal de entrada através da aquisição das suas componentes em fase e em quadratura. As modificações da malha foram a introdução de um filtro notch adaptativo em sua entrada e a implementação de toda a estrutura utilizando o operador delta (δ), relacionado à Transformada Gama (γ). A introdução do filtro notch adaptativo na entrada da malha garante uma significativa melhoria na relação SNR do sinal de entrada, sem prejudicar demasiadamente a resposta dinâmica da estrutura. A característica adaptativa do filtro garante uma performance satisfatória da malha para sinais de entrada com parâmetros variantes no tempo. A implementação da malha utilizando o operador delta (δ) assegura uma performance ideal quando a mesma é implementada em sistemas de precisão limitada de, no mínimo, 16 bits. De acordo com os resultados demonstrados nesse trabalho, a performance da malha é satisfatória mesmo ao se utilizar altas taxas de amostragem relativas à freqüência de operação da malha. Finalmente, foi proposta uma implementação da malha em um microprocessador (DSP) da família TMS320, o que comprova a viabilidade de implementação da mesma em sistemas (hardware) de ponto fixo. / The always more restrictive energy quality benchmarks, pushed on by consumers, associated with the electric sector deregulamentation has been imposing the necessity, for the concessionaries, of a better and decentralized monitoring of energy electric quality. At the same time, the increase of nonlinear loads connected to the electric network, among other facts, has been increasing the complexities associated with this electric signals parameters estimation. So, the synthesis of efficient parameters estimation algorithms, with low computational effort and with easy implementation on low-cost hardware systems has becoming a priority for the energy quality area. Based on these assumptions, this work deals with the design and synthesis of a robust Phase-Locked-Loop (PLL) structure, more specifically an Enhanced Quadrature Phase-Locked-Loop (ER-QPLL) with capacity of estimate several parameters, more specifically phase, frequency and amplitude, from any input signal. The synthesis of this ER-QPLL structure was based on the enhancement of a Quadrature Phase-Locked-Loop (QPLL) that can estimate the parameters of the fundamental component of any input signal thought the information acquired with the acquisition of its phase and quadrature components. The enhancements of this QPLL structure were, basically, the introduction of a adaptive notch filter on its input, associated with an delta operator (δ), a tool of the gamma transformer (γ), for modeling the whole structure. A significant improvement in the SNR of the input signal, without degradation of the dynamic structure output, was achieved with the introduction of the notch filter. The adaptive characteristics of this notch filter can deal, in a very good way, with the non-stationery properties of the input signals. The structure implementation based on delta operator (δ) can assure an almost ideal performance for limited precision systems of, at least, 16 bits. According to the results obtained in this work, the performance of the proposed structure can be considered very good, even when dealing with high sampling rates relative to the network frequency operation. Finally, a structure based on a microprocessor DSP from TMS320 family was proposed and implemented showing its feasibility for fixed-point hardware.