Considere um sistema de comunicação em que um equipamento transmissor envia pacotes de dados, de tamanho fixo e a uma taxa uniforme, a um equipamento receptor. Considere também que esses equipamentos estejam conectados por uma rede de comutação de pacotes, que introduz um atraso aleatório a cada pacote que trafega na rede. Nesta tese, é proposto um modelo de recuperação adaptativa de relógio capaz de sincronizar as frequências e as fases desses dispositivos, dentro de certos limites especificados de precisão. Esse método para atingir sincronização de frequência e de fase é baseado em medições dos tempos de chegada dos pacotes ao receptor, que são usados para controlar a dinâmica de um phase-locked loop (PLL) digital. O desempenho desse modelo é avaliado através de simulações numéricas realizadas considerando valores de parâmetros realistas. Os resultados indicam que esse esquema tem potencial para ser usado em aplicações práticas. / Consider a communication system in which a transmitter equipment sends fixed-size packets of data at a uniform rate to a receiver equipment. Consider also that these equipments are connected by a packet-switched network, which introduces a random delay to each packet. In this thesis, we propose an adaptive clock recovery scheme capable of synchronizing the frequencies and the phases of these devices, within specified limits of precision. This scheme for achieving frequency and phase synchronization is based on measurements of the packet arrival times at the receiver, which are used to control the dynamics of a digital phase-locked loop (PLL). The scheme performance is evaluated via numerical simulations performed by using realistic parameter values. The results suggest that this scheme has potential to be used in practical applications.

Esta dissertação propõe o projeto e a implementação de um sintetizador de sinal pertencente à banda X, com frequência de 9.192 GHz, para promover a transição atômica do átomo de césio durante o ciclo de operação do padrão atômico de frequência do CePOF/IFSC. Diferente do sintetizador em uso, este provê duas fontes de sinais, a fim de realizar a alimentação simétrica da cavidade de micro-ondas. A alimentação simétrica apresenta uma melhoria em relação à montagem experimental atual e visa atenuar os efeitos de gradiente de potência ao quais os átomos estão expostos enquanto cruzam a cavidade de interrogação. O sintetizador também apresenta um controle de fase em um dos sinais, para que seja possível um ajuste de fase entre eles, permitindo que ambos cheguem à cavidade de interrogação em fase. O método utilizado para a síntese dos sinais é o indireto, onde o sinal de interesse é obtido por meio de osciladores e componentes que possibilitam a manipulação algébrica das frequências, aliados aos circuitos de travamento para controle dos osciladores / This text considers the design and implementation of an X-band signal synthesizer, with a 9.192 GHz frequency, to promote the atomic transition of cesium during the operation process of the CePOF/IFSCs atomic frequency standard. Unlike the current synthesizer, the present one provides two sources of signal, in order to perform the symmetrical feed of the microwave cavity. The symmetrical feed is an improvement compared to the current experimental set up and aims at reducing the power gradient effects to which the atoms are exposed when travelling throughout the interrogation cavity. The synthesizer also has a phase control in one of the signals, in order to ensure that both signals will get into the interrogation cavity in phase. The synthesis method used is the indirect one; the desired signal is formed by means of oscillators and devices that allow the algebraic manipulation of frequencies, combined with lock circuits to control the oscillators

L’ensemble des travaux présentés au sein de manuscrit porte sur la réalisation d’un synthétiseur de fréquences millimétriques capable de répondre aux besoins de la convergence WiFi-WiGig. Une première étude est réalisée dans le but de définir une architecture de synthétiseur de fréquence faible consommation adaptée aux standards du WiFi et du WiGig. L’ensemble des éléments composants la PLL sont par la suite détaillés, mettant en avant les avantages offerts par la technologie 28 nm FDSOI CMOS. Une étude plus approfondie des VCO millimétriques large bande et faible consommation est ensuite présentée, permettant de mettre en avant une réelle méthodologie de conception en lien avec la technologie 28 nm FDSOI CMOS. Finale-ment, diverses solutions sont proposées dans le but d’améliorer les performances de la PLL, avec l’incorporation de VCO millimétriques à ondes lentes, ou d’oscillateurs à anneaux synchronisés. / The works presented in this manuscript focus on the realization of a millimeter frequency synthesizer meeting the needs of the WiGig-Fi convergence. A first study was conducted to define a suitable low-power frequency synthesizer archi-tecture for WiFi and WiGig standards. All of the PLL components are subsequently detailed, highlighting the 28nm CMOS FDSOI technology benefits. Then, a study of low power millimeter broadband VCO is presented, highlighting a design methodology related to the 28nm CMOS FDSOI technology. Finally, various solutions are proposed in order to improve the PLL performances, with the incorporation of slow wave VCO, or injection locked ring oscillators.

La thèse étudie tout d’abord la relation entre les harmoniques à fentes du rotor (RSHs) et la vitesse du rotor instantanée. Pour suivre directement l'RSH, les exigences du système sont pleinement prises en compte.Dans un deuxième temps, les travaux de thèse ont permis de développer un système sans capteur en fonction de boucle à verrouillage de phase (PLL): La largeur de bande centrale est réglée en ligne sur la base des valeurs de référence, des fréquences d'alimentation et de glissement prévues au convertisseur PWM, la PLL est réglée pour suivre le rotor de la machine à RSH sans la nécessité de toute injection de signal à haute fréquence, ni en rotation, ni de pulsation. Ce système d'estimation de vitesse, qui est approprié pour le contrôleur scalaire, avait été intégré avec le lecteur scalaire, conduisant à un simple calcul peu exigeant, à faible coût de l’entraînement de la machine à induction sans capteur à faible coût. Les résultats expérimentaux montrent que le système est en mesure de suivre la vitesse de la machine dans une plage de vitesse très étendue.Enfin, un système sans capteur amélioré basé sur l'analyse de composant mineur (MCA) neurones est décrit. Selon la théorie de Pisarenko, il a été vérifié que le MC qui se trouve dans le sous-espace de bruit est orthogonale au sous-espace de signal, par conséquent, les fré-quences de signal contenues dans l'entrée peuvent être calculées à partir d'un polynôme formé par la MC. Classiquement, ce qui nécessitera la décomposition propre encombrants, néan-moins, la méthode de neurones proposée dans cette thèse peut récupérer le MC de façon ré-cursive avec moins de calculs et des performances améliorées d'erreur (la solution est sur un total de moins sens carré). En outre, l'estimateur de vitesse est appliquée à l'entraînement scalaire avec vérification expérimentale, l'ensemble du système se comporte bien, et la méthode MCA renforcée par réseaux neuronaux a fourni un bon potentiel dans l'application des harmoniques récupérer. / The thesis first studies the relation between the rotor slot harmonics (RSHs) and the instan-taneous rotor speed. To directly track the RSH, the requirements of the system are fully ad-dressed.Second, the thesis presents a sensorless scheme based on phase-locked loop (PLL): The centre bandwidth is tuned on-line on the basis of the reference values of the supply and slip frequencies provided to the PWM converter, the PLL is tuned to track the machine rotor slot-ting harmonic without the need of any high frequency signal injection, neither rotating nor pulsating. This speed estimation scheme, which is suitable for the scalar controller, had been integrated with the scalar drive, leading to a simple, computationally not demanding, low cost sensorless IM drives. The experiment results show that the system is able to track the machine speed in a very wide speed range.Finally, an improved sensorless scheme based on minor component analysis (MCA) neu-rons is described. According to the Pisarenko’s theory, it has been verified that the MC which lies in the noise subspace is orthogonal to the signal subspace, thus, the signal frequencies contained in the input can be computed from a polynomial formed by the MC. Conventional-ly, this will require the bulky eigen-decomposition, nevertheless, the neural method proposed in this thesis can retrieve the MC recursively with less computation and improved error per-formance (the solution is of total least square meaning). Moreover, the speed estimator is ap-plied to the scalar drive with experimental verification, the overall system is well behaved, and the MCA method enhanced by neural networks has provided a good potential in the ap-plication of harmonics retrieve.

Considere um sistema de comunicação em que um equipamento transmissor envia pacotes de dados, de tamanho fixo e a uma taxa uniforme, a um equipamento receptor. Considere também que esses equipamentos estejam conectados por uma rede de comutação de pacotes, que introduz um atraso aleatório a cada pacote que trafega na rede. Nesta tese, é proposto um modelo de recuperação adaptativa de relógio capaz de sincronizar as frequências e as fases desses dispositivos, dentro de certos limites especificados de precisão. Esse método para atingir sincronização de frequência e de fase é baseado em medições dos tempos de chegada dos pacotes ao receptor, que são usados para controlar a dinâmica de um phase-locked loop (PLL) digital. O desempenho desse modelo é avaliado através de simulações numéricas realizadas considerando valores de parâmetros realistas. Os resultados indicam que esse esquema tem potencial para ser usado em aplicações práticas. / Consider a communication system in which a transmitter equipment sends fixed-size packets of data at a uniform rate to a receiver equipment. Consider also that these equipments are connected by a packet-switched network, which introduces a random delay to each packet. In this thesis, we propose an adaptive clock recovery scheme capable of synchronizing the frequencies and the phases of these devices, within specified limits of precision. This scheme for achieving frequency and phase synchronization is based on measurements of the packet arrival times at the receiver, which are used to control the dynamics of a digital phase-locked loop (PLL). The scheme performance is evaluated via numerical simulations performed by using realistic parameter values. The results suggest that this scheme has potential to be used in practical applications.

Esta dissertação propõe o projeto e a implementação de um sintetizador de sinal pertencente à banda X, com frequência de 9.192 GHz, para promover a transição atômica do átomo de césio durante o ciclo de operação do padrão atômico de frequência do CePOF/IFSC. Diferente do sintetizador em uso, este provê duas fontes de sinais, a fim de realizar a alimentação simétrica da cavidade de micro-ondas. A alimentação simétrica apresenta uma melhoria em relação à montagem experimental atual e visa atenuar os efeitos de gradiente de potência ao quais os átomos estão expostos enquanto cruzam a cavidade de interrogação. O sintetizador também apresenta um controle de fase em um dos sinais, para que seja possível um ajuste de fase entre eles, permitindo que ambos cheguem à cavidade de interrogação em fase. O método utilizado para a síntese dos sinais é o indireto, onde o sinal de interesse é obtido por meio de osciladores e componentes que possibilitam a manipulação algébrica das frequências, aliados aos circuitos de travamento para controle dos osciladores / This text considers the design and implementation of an X-band signal synthesizer, with a 9.192 GHz frequency, to promote the atomic transition of cesium during the operation process of the CePOF/IFSCs atomic frequency standard. Unlike the current synthesizer, the present one provides two sources of signal, in order to perform the symmetrical feed of the microwave cavity. The symmetrical feed is an improvement compared to the current experimental set up and aims at reducing the power gradient effects to which the atoms are exposed when travelling throughout the interrogation cavity. The synthesizer also has a phase control in one of the signals, in order to ensure that both signals will get into the interrogation cavity in phase. The synthesis method used is the indirect one; the desired signal is formed by means of oscillators and devices that allow the algebraic manipulation of frequencies, combined with lock circuits to control the oscillators

Submitted by Renata Lopes (renatasil82@gmail.com) on 2016-07-27T14:50:55Z No. of bitstreams: 1 carolinaventuripinheiro.pdf: 2690052 bytes, checksum: 1d8da177ba05614f2f5b1f876bebdaa4 (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2016-07-27T15:51:51Z (GMT) No. of bitstreams: 1 carolinaventuripinheiro.pdf: 2690052 bytes, checksum: 1d8da177ba05614f2f5b1f876bebdaa4 (MD5) / Made available in DSpace on 2016-07-27T15:51:51Z (GMT). No. of bitstreams: 1 carolinaventuripinheiro.pdf: 2690052 bytes, checksum: 1d8da177ba05614f2f5b1f876bebdaa4 (MD5) Previous issue date: 2016-04-07 / FAPEMIG - Fundação de Amparo à Pesquisa do Estado de Minas Gerais / Uma questão importante para a inserção da geração distribuída (GD) é a confiabilidade e a qualidade de energia fornecida aos consumidores. Este trabalho visa analisar a conexão de um sistema fotovoltaico (PV) e seus efeitos na rede elétrica utilizando simulação em tempo real. O sistema de simulação implementado consiste de sistemas fotovoltaicos, conversores de energia, carga variável e rede elétrica, implementados em um Real Time Digital Simulator (RTDS), enquanto que o controle é executado a partir da plataforma dSPACE, caracterizando uma sistema de simulação do tipo Hardware In the Loop (HIL). Os modelos de carga foram desenvolvidos com base em perfis de demanda reais, a partir de três alimentadores de distribuição diferentes da cidade de Leopoldina, no estado de Minas Gerais. Os dados de medição dos alimentadores foram tomados com um intervalo de 15 minutos, totalizando um tempo de medição de 24 horas. Dados de radiação solar usadas nos modelos PV foi medido no Labsolar - Universidade Federal de Juiz de Fora, também por um período de 24 horas. O propósito deste estudo é executar uma simulação HIL, combinando RTDS e dSPACE, que é um controlador digital. Com o tempo real é possível investigar o comportamento do sistema com a potência injetada pelo sistema PV, incluindo o controle do inversor utilizado para acoplar os diferentes sistemas fotovoltaicos à rede, em uma modelagem que se aproxima da realidade, com menores custos de implementação e maior segurança. Os resultados mostram uma comparação entre a potência ativa e reativa injetada pelos sistemas fotovoltaicos e a rede, e a energia consumida pelas cargas, validando a estratégia de controle implementada. / An important issue for the integration of Distributed Generation (DG) is the reliability and quality of energy supplied to consumers. This work aims at analyzing the grid connection of a photovoltaic (PV) system and its effects on the electrical network using realtime simulation. The implemented simulation system consists of photovoltaic systems, power converters, variable load and electrical grid, implemented in Real Time Digital Simulator (RTDS) while the control is run from the dSPACE controller, creating a Hardware In the Loop (HIL) platform. The load models were developed based on actual demand profile from three different distribution feeders of the city of Leopoldina, in the state of Minas Gerais. The feeders’ measurement data was taken with an interval of 15 minutes, with a total measurement time of 24 hours. Solar radiation data used in the PV models has been measured at the Solar Laboratory – Universidade Federal de Juiz de Fora, also for a 24-hour period. The purpose of this study is to perform a HIL simulation, combining RTDS and dSPACE, which is a digital controller. With real-time/ HIL simulation, it is possible to investigate the behavior of the system with the power injected by the PV system, including inverter control used to attach the different photovoltaic systems to the grid, in a model which approaches reality, with low implementation cost and higher safety. Results show a comparison between the active and reactive power injected by the photovoltaic system and network, and the power consumed by the loads, verifying the implemented control strategy.

International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / This paper discusses the design and performance of the FM/PM/BPSK "personal computer card-based" receiver. In PSK, a carrier recovery technique must be used for signal demodulation. Costas loop is a well known method and is the basis in the design of the BPSK demodulation. A new design approach employing digital Box Car arm filters is used to improve receiver performance and flexibility. Detail design and performance of the digital Costas loop will be explored in a later section. A classical technique is employed for Phase demodulation with the use of tracking Phase Lock Loop. Frequency demodulation is designed around a simple, single FM discriminator IC.

The expanding growth of mobile products and services has led to various wireless communication standards that employ different spectrum bands and protocols to provide data, voice or video communication services. Software deffned radio and cognitive radio are emerging techniques that can dynamically integrate various standards to provide seamless global coverage, including global roaming across geographical regions, and interfacing with different wireless networks. In software deffned radio and cognitive radio, one of the most critical RF blocks that need to exhibit frequency agility is the phase lock loop (PLL) frequency synthesizer. In order to access various standards, the frequency synthesizer needs to have wide frequency tuning range, fast tuning speed, and low phase noise and frequency spur. The traditional analog charge pump frequency synthesizer circuit design is becoming diffcult due to the continuous down-scalings of transistor feature size and power supply voltage. The goal of this project was to develop an all digital phase locked loop (ADPLL) as the alternative solution technique in RF transceivers by taking advantage of digital circuitry's characteristic features of good scalability, robustness against process variation and high noise margin. The targeted frequency bands for our ADPLL design included 880MHz-960MHz, 1.92GHz-2.17GHz, 2.3GHz-2.7GHz, 3.3GHz-3.8GHz and 5.15GHz-5.85GHz that are used by wireless communication standards such as GSM, UMTS, bluetooth, WiMAX and Wi-Fi etc. This project started with the system level model development for characterizing ADPLL phase noise, fractional spur and locking speed. Then an on-chip jitter detector and parameter adapter was designed for ADPLL to perform self-tuning and self-calibration to accomplish high frequency purity and fast frequency locking in each frequency band. A novel wide band DCO is presented for multi-band wireless application. The proposed wide band adaptive ADPLL was implemented in the IBM 0.13µm CMOS technology. The phase noise performance, the frequency locking speed as well as the tuning range of the digitally controlled oscillator was assessed and agrees well with the theoretical analysis.

La synthèse de fréquences est une fonction largement utilisée dans les émetteur-récepteurs radios. En général, la fonction synthèse de fréquence est réalisée à l’aide d’une boucle à verrouillage de phase utilisant des diviseurs de fréquence numériques. Cette thèse présente un nouveau type de diviseur de fréquence faisant appel à des mémoires D et son application à la synthèse de fréquences. Ce nouveau diviseur permet de repousser les limites des diviseurs numériques classiques à bascules D, en matière de fréquence maximale de fonctionnement et de consommation, tout en conservant leur souplesse d’utilisation. La première partie de cette thèse présente les techniques usuelles de réalisation des synthèses de fréquence et des diviseurs de fréquences, ainsi que le nouveau diviseur SRO à base de mémoires D, sujet de ces travaux. Une étude détaillée de ce diviseur est réalisée avec un premier modèle utilisant une approche numérique, puis un second plus réaliste faisant appel à une modélisation de type analogique. Cette étude démontre que ce nouveau diviseur SRO est capable de fonctionner à une fréquence plus élevée ou avec une consommation moindre, tout en réalisant les mêmes facteurs de division, que les diviseurs classiques à bascules D. La dernière partie de cette thèse présente plusieurs implémentations en technologies CMOS et BiCMOS de ST Microelectronics du diviseur SRO. En particulier son implémentation dans deux synthétiseurs de fréquences fractionnaires à 24 GHz montre son intérêt de part la réduction significative de consommation obtenue, tout en conservant une structure simple utilisant une surface de silicium réduite / Frequency synthesis is almost used in all RF transceivers, where this function is usually achieved by using phase-locked-loop circuits. Most often, the phase-locked-loop includes digital frequency dividers in the feedback that present high power dissipation and low maximum frequency at gigahertz frequencies. This thesis presents a versatile new D latch-based divider that improves these issues and its application to frequency synthesis. The first part presents several frequency synthesis techniques and theirs main characteristics. Then is described various classical frequency dividers and the proposed new D latch-based SRO divider. A detailed study of the SRO divider is presented with two approaches, the digital one and the analogue one. This study demonstrates the benefit of the SRO divider in terms of power dissipation and speed compared with the widely used D flip-flop based dividers. The last part presents several implementations of the SRO divider in CMOS and BiCMOS processes of ST Microelectronics. Particularly, the SRO divider was implemented in two 24 GHz fractional synthesizers, where it demonstrates its interest for reduction of power dissipation while using small silicon area.