This is a thesis report done as part of the Master of Science in Electronics Design Engineering given at Linköping University, Campus Norrköping. The thesis work is done at Ericsson AB in the spring of 2005. The thesis describes a method of removing variations in the tuning sensitivity of voltage-controlled crystal oscillators due to different manufacturing processes. These variations results in unwanted variations in the modulation bandwidth of the phase-locked loop the oscillator is used in. Through examination of the theory of phase-locked loops it is found that the bandwidth of the loop is dependent on the tuning sensitivity of the oscillator. A method of correcting the oscillator-sensitivity by amplifying or attenuating the control-voltage of the oscillator is developed. The size of the correction depends on the difference in oscillator-sensitivity compared to that of an ideal oscillator. This error is measured and the correct correction constant calculated. To facilitate the measurements and correction extra circuits are developed and inserted in the loop. The circuits are both analog and digital. The analog circuits are mounted on an extra circuit board and the digital circuits are implemented in VHDL in an external FPGA. Tests and theoretical calculations show that the method is valid and able to correct both positive and negative variations in oscillator-sensitivity of up to a factor ±2.5 times. The bandwidth of the loop can be adjusted between 2 to 15 Hz (up to ±8 dB, relative an unmodified loop).

In this dissertation, we propose a circuit design and implementation of physical layer for FlexRay-based automotive communication systems which are expected to be widely used in car electronics for the years to come. To reduce the volume of electrical lines in a car and ensure safe connections, the automotive communication systems are more important than ever. FlexRay systems have been deemed as better than other existing solutions for the complicated in-vehicle networks. A low-voltage differential-signaling-like transmitter is proposed to drive the twisted pair of the FlexRay bus. Furthermore, a three-comparator scheme is used to carry out bit slicing and state recognition at the receiver end. A prototype system as well as a chip implemented by using a typical 0.18 £gm single-poly six-metal CMOS process is reported in this dissertation. Furthermore, an accurate clock signal is required in any control system, especially in the vehicle applications, where the ¡§safety¡¨ is the top priority. Because of the TDMA strategy (Time Division Multiple Access) was chosen for the FlexRay communication protocol, the system clock should not be drifting too much. A robust 20 MHz clock generator with process, supply voltage, and temperature compensation and a low-jitter 80 MHz phase-lock loop are proposed in this dissertation to reduce hostile environment effects. Finally, because the ¡§safety¡¨ and ¡§reliability¡¨ are top design requirements in the automobile electronics, we should also focus on the power supply design in the in-car communication networks. Therefore, a high tolerant and high efficiency voltage converter is proposed in this dissertation. By utilizing stacked power MOSFETs, a voltage level converter, a detector and a controller, this design is realized by a typical CMOS process without any thick-oxide device to tolerate input voltage range up to 3 times of the VDD voltage.

This thesis presents a wide tuning, low phase noise CMOS integer-N frequency synthesizer with 1.8V power supply. The frequency synthesizer is designed using the TSMC 0.18£gm CMOS 1P6M technology. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection (ABS), an optimum-band selection (OBS), and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator with switched capacitors technique with a lowered VCO gain (KVCO) to achieve wide tuning range and low phase noise in order to cover the desired operating frequency bands and to accommodate process, voltage, and temperature (PVT) variations. The ABS accomplishes the efficient search for a VCO discrete tuning curve among a group of frequency sub-bands. It is apparent to reduce the calibration time by adopting the binary search algorithm to select the calibration word. However, the variation of Kvco across different channels can still be large after the execution of ABS. There might be many sub-bands covering the desired frequency. Hence the sub-band which is selected by ABS could not be an optimum choice for the minimum Kvco variation. The OBS is proposed to implement an algorithm in order to find the optimum solution which has the minimum Kvco variation and covers the desired frequency. The Kvco variation is quantified by OBS and using this value to adjust the charge pump current. Therefore, Loop bandwidth and stability were maintained across the operating range by using optimum-band selection(OBS) and a programmable charge pump.

The cost to test chips has risen tremendously. Additionally, the process for testing all functionalities of both analog and digital part is far from simple. One attractive option is moving some or all of the testing functions onto the chip itself leading to the use of built-in self-tests (BISTs). The frequency generator or frequency synthesizer is a key element of the BIST. It generates the clock frequencies needed for testing. A wide-band frequency synthesizer is designed in the project. The architecture of a PLL is analyzed as well as the modifications carried out. The modified structure has three blocks: basic PLL based frequency synthesizer, frequency down-converter, and output selector. Each of these blocks is analyzed and designed. This frequency synthesizer system overcomes challenges faced by the traditional PLL based frequency synthesizer.

The frequency synthesizer, which performs the main role of carrier generation for the down-conversion/up-conversion operations, is a key building block in radio transceiver front-ends. The design of a synthesizer for a 2.4 GHz IEEE 802.15.4/Zigbee transceiver forms the core of this work. This thesis provides a step-by-step procedure for the design of a frequency synthesizer in a transceiver environment, from the mapping of standard-specifications to its integrated circuit implementation in a CMOS technology. The results show that careful system level planning leads to high-performance realizations of the synthesizer. A strategy of using different supply voltages to enhance the performance of each building block is discussed. A section is presented on layout and board level issues, especially for radio-frequency systems, and their effect on synthesizer performance. The synthesizer consumes 15.5 mW and meets the specifications of the 2.4 GHz IEEE 802.15.4/Zigbee standard. It is capable of 5 GHz operation with a VCO sensitivity of 135 MHz/V and a tuning range of 700 MHz. It can be seen that the adopted methodology can be used for the design of high-performance frequency synthesizers for any narrow-band wireless standard.

This thesis presents a low power consumption and low phase noise CMOS integer-N frequency synthesizer, and it bases on a charge-pump PLL topology. The frequency synthesizer can be used for IEEE 802.16b unlicensed band of WiMAX(World Interoperability for Microwave Access) from 5.725GHz to 5.825GHz. It provides the one ration frequency ranged from 5.13GHz to 5.22GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage-controlled oscillator, and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator to achieve low power consumption and low phase noise. Moreover divider is implemented by an optimal extended true single-phase clock-base prescaler. It can achieve high-resolution frequency operation and reduction of power consumption. This chip is fabricated in a TSMC 0.18£gm CMOS 1P6M technology process. The whole chip area is 1.1 mm2.

Analog and mixed signal device testing is resource intensive due to the spectral and temporal speci cations of the input/output interface signals. These devices and circuits are commonly validated by parametric speci fication tests to ensure compliance with the required performance criteria. Analog signal complexity increases resource requirements for the Automatic Test Equipment (ATE) systems used for commercial testing, making mixed signal testing resource ine cient as compared to digital structural testing. This dissertation proposes and implements a test ecosystem to address these constraints where Built In Self Test (BIST) modules are designed for internal stimulus generation. Data learning and processing algorithms are developed for output response shaping. This modi ed output response is then compared against the established performance matrices to maintain test quality with low cost receiver hardware. BIST modules reduce dependence on ATE resources for stimulus and output observation while improving capability to test multiple devices in parallel. Data analysis algorithms are used to predict specification parameters based on learning methods applied to measurable device parameters. Active hardware resources can be used in conjunction with post processing resources to implement complex speci cation based tests within the hardware limitations. This dissertation reviews the results obtained with the consolidated approach of using BIST, output response analysis and active hardware resources to reduce test cost while maintaining test quality. / text

abstract: As residential photovoltaic (PV) systems become more and more common and widespread, their system architectures are being developed to maximize power extraction while keeping the cost of associated electronics to a minimum. An architecture that has become popular in recent years is the "DC optimizer" architecture, wherein one DC-DC converter is connected to the output of each PV module. The DC optimizer architecture has the advantage of performing maximum power-point tracking (MPPT) at the module level, without the high cost of using an inverter on each module (the "microinverter" architecture). This work details the design of a proposed DC optimizer. The design incorporates a series-input parallel-output topology to implement MPPT at the sub-module level. This topology has some advantages over the more common series-output DC optimizer, including relaxed requirements for the system's inverter. An autonomous control scheme is proposed for the series-connected converters, so that no external control signals are needed for the system to operate, other than sunlight. The DC optimizer in this work is designed with an emphasis on efficiency, and to that end it uses GaN FETs and an active clamp technique to reduce switching and conduction losses. As with any parallel-output converter, phase interleaving is essential to minimize output RMS current losses. This work proposes a novel phase-locked loop (PLL) technique to achieve interleaving among the series-input converters. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2014

Orientador: Nobuo Oki / Banca: Carlos Antonio Alves / Banca: Ailton Akira Shinoda / Banca: José Raimundo de Oliveira / Banca: José Ricardo Descardeci / Resumo: Sintetizadores de frequência são circuitos críticos usados largamente em muitas aplicações de temporização. Circuitos PLL apresentam uma boa solução para temporização, mas utilizam geralmente blocos analógicos que são facilmente influenciados em desempenho devidos a instabilidades inerentes aos processos de fabricação e ruídos. Com a evolução dos circuitos e ferramentas para sistemas digitais foi possível a implementação de circuitos que utilizem somente recursos digitais tais como os DLL. Um dos papéis dos sintetizadores é equalizar a fase de um sinal de clock em relação a uma segunda referência adicionando fase entre os sinais. Este trabalho tem como objetivo o desenvolvimento de um circuito DLL com arquitetura flexível e programável para utilização no ajuste de fase e recuperação de sinais. Os blocos digitais foram implementados utilizando ferramentas de alto nível de abstração para avaliação do comportamento funcional. O objetivo final é a implementação do circuito validado em tecnologia CMOS 350 nm da AMS / Abstract: Frequency Synthesizers are critical circuits widely used in timing applications. PLLs devices had showed a good solution for timing, but they normally because the use analog building blocks that are often influenced by the subtract building process and noises. Nevertheless, after the evolution of complex circuits and development tools it had been possible the implementation of systems that implement only digital resource such as DLL. One of major goals of synthesizers is to equalize the phase between a clock signal and a second reference. This work aims to develop DLL devices that are built in a flexible and reprogrammable architecture for using in decrements or increments in the phase and clock recovery. Digital blocks were implemented using high level abstraction tools for analysis of functional behavior. The main objective is the circuit implementation and validations in CMOS .35 AMS process / Doutor

Submitted by isabela.moljf@hotmail.com (isabela.moljf@hotmail.com) on 2017-02-14T11:04:49Z No. of bitstreams: 1 luisclaudiogamboalopes.pdf: 7099738 bytes, checksum: b7593ec87a0bf197f35c720c3c819ab6 (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2018-03-22T11:16:28Z (GMT) No. of bitstreams: 1 luisclaudiogamboalopes.pdf: 7099738 bytes, checksum: b7593ec87a0bf197f35c720c3c819ab6 (MD5) / Made available in DSpace on 2018-03-22T11:16:28Z (GMT). No. of bitstreams: 1 luisclaudiogamboalopes.pdf: 7099738 bytes, checksum: b7593ec87a0bf197f35c720c3c819ab6 (MD5) Previous issue date: 2006-08-25 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Esta dissertação descreve as etapas de desenvolvimento de um sistema experimental de geração de energia elétrica de 30 kW baseado em painéis solares fotovoltaicos montado no Campus da Universidade Federal de Juiz de Fora (UFJF). São apresentados detalhes do sistema fotovoltaico como: tipo e técnicas de chaveamento dos conversores estáticos CC-CC e CC-CA, modelos digitais das partes do sistema, algoritmos de controle, circuitos de condicionamento, entre outros. A energia CC proveniente dos painéis fotovoltaicos é processada por conversores CC-CC boost. Esses conversores são controlados para rastrear o ponto de máxima potência (MPPT - “Maximum Power Point Tracking”) dos painéis fotovoltaicos. Dois inversores fonte de tensão (VSI - “Voltage Source Inverter”) conectados em série através de transformadores injetam a energia processada pelos conversores CC-CC na rede elétrica CA. Os conversores VSIs utilizam uma técnica de chaveamento multipulso com eliminação seletiva de harmônicos. Todos os algoritmos de controle dos conversores CC-CC e CC-CA são implementados em processadores de sinais digitais (DSP -“Digital Signal Processor”). Um sistema supervisório foi desenvolvido para monitorar as variáveis e ajustar a operação do sistema como compensador estático ou como sistema de geração disperso. Resultados de simulações digitais obtidos com o programa ATP/EMTP (Alternative version of Electromagnetic Transient Program) e com um programa emulador de DSPs são usados para validar as estratégias de controle e de chaveamento propostas. Finalmente resultados experimentais demonstram o funcionamento do sistema e validam o trabalho. / This dissertation describes the development steps of an experimental photovoltaic system of electric energy generation of 30 kW installed on the Federal University of Juiz de Fora Campus (UFJF). Details of the photovoltaic system are presented such as: CC-CC and CC-CA converters topologies and switching strategy, digital models, control algorithms, conditioning circuits, among others. The DC energy from the photovoltaic panels is processed by DC-DC type boost converters. These converters are controlled to track the maximum power point (MPPT) of the photovoltaic panels. Two voltage source inverters (VSI), series connected through two transformers, inject the energy processed by the boost converters into the AC network. The VSI’s output voltages use multipulse technique with a selective harmonic elimination. All control algorithms of the DC-DC and DC-AC converters are designed and implemented in digital signal processors (DSP). A supervisory system is designed and developed to monitor the system variables and to control the operation of the system as static synchronous compensator or as dispersed generation system. Simulation results, obtained with ATP/EMTP (Alternative version of Electromagnetic Transient Program) and with a DSP emulator program, are used to validate the proposed control and switching strategies. Finally experimental results demonstrate the operation of the photovoltaic generation system and are used to validate this work.