The computation of a piecewise smooth function that approximates a finite set of data points is decomposed into two decoupled tasks: first, the computation of the locally smooth models, and hence, the segmentation of the data into classes that consist on the sets of points best approximated by each model, and second, the computation of the normalized discriminant functions for each induced class. The approximating function is then computed as the optimal estimator with respect to this measure field. Applications to image processing and time series prediction are presented as well.

Rapid scaling in technology has introduced new challenges in the realm of traditional analog design. Scaling of supply voltage directly impacts the available voltage-dynamic-range. On the other hand, nanometric technologies with fT in the hundreds of GHz range open opportunities for time-resolution-based signal processing. With reduced available voltage-dynamic-range and improved timing resolution, it is more convenient to devise analog circuits whose performance depends on edge-timing precision rather than voltage levels. Thus, instead of representing the data/information in the voltage-mode, as a difference between two node voltages, it should be represented in time-mode as a time-difference between two rising and/or falling edges. This dissertation addresses the feasibility of employing time-mode analog circuit design in different applications. Specifically: 1) Time-mode-based quanitzer and feedback DAC of SigmaDelta ADC. 2) Time-mode-based low-THD 10MHz oscillator, 3) A Spur-Frequency Boosting PLL with -74dBc Reference-Spur Rejection in 90nm Digital CMOS. In the first project, a new architectural solution is proposed to replace the DAC and the quantizer by a Time-to-Digital converter. The architecture has been fabricated in 65nm and shows that this technology node is capable of achieving a time-matching of 800fs which has never been reported. In addition, a competitive figure-of-merit is achieved. In the low-THD oscillator, I proposed a new architectural solution for synthesizing a highly-linear sinusoidal signal using a novel harmonic rejection approach. The chip is fabricated in 130nm technology and shows an outstanding performance compared to the state of the art. The designed consumes 80% less power; consumes less area; provides much higher amplitude while being composed of purely digital circuits and passive elements. Last but not least, the spur-frequency boosting PLL employs a novel technique that eliminates the reference spurs. Instead of adding additional filtering at the reference frequency, the spur frequency is boosted to higher frequency which is, naturally, has higher filtering effects. The prototype is fabricated in 90nm digital CMOS and proved to provide the lowest normalized reference spurs ever reported.

Nas últimas três décadas os phase locked loops (PLLs) totalmente digitais têm recebido muita atenção devido, principalmente, às vantagens que eles oferecem em comparação aos PLLs analógicos. Essas vantagens incluem melhor desempenho, maior velocidade e confiabilidade, tamanho reduzido e menor custo. Os PLLs também são amplamente utilizados em sistemas de comunicações e em outras aplicações digitais. A presente dissertação é uma contribuição no campo dos PLLs digitais adaptativos e otimizados para a sua implementação em hardware. É feito uma análise de suas características dinâmicas e proposta uma nova estrutura de PLL digital capaz de melhorar a resposta da malha em termos de tempo de aquisição e largura de banda. A Malha Síncrona Digital \"Tanlock\" com Estimação de Frequência e Ganho Adaptativo para Convergência Rápida, como é chamada, foi desenvolvida a partir da malha digital \"Tanlock\", utilizando-se teoremas de ponto fixo e mapas contrativos para determinar as condições de ganho que garantam convergência rápida e melhor utilização da largura de banda. Resultados das simulações são comparados com os obtidos teoricamente para avaliar o desempenho da malha proposta. / In the last three decades, fully-digital Phase-Locked-Loops (PLLs) systems have received a lot of attention due to its advantages in comparison with analog PLLs. These advantages include improved transient response, reliability and also reduced size and cost. The PLLs are widely used in communications systems and many other digital applications. This dissertation is a contribution to the field of digital adaptive PLLs optimized to hardware implementation. Here, a new PLL structure is presented; the Frequency Sensing Adaptive TDTL is an improvement to the classic Time-Delay Tanlock structure, alowing fast convergence to the synchronous states, using fixed-point theorems and contractive maps to determine the gain conditions which ensure the rapid convergence and also providing wider bandwidth. The results of simulations are compared with those obtained theoretically in order to assess the loop performance.

This work deals with analysis of protocol APRS Automatic Positioning System for telemetry. There is analyzed the structure of the most important frames and their application. It discusses the processing of GPS data and subsequent modulation of the selected frequency. This work also describes and discusses the proposed peripheral devices and the used firmware.

Clock multipliers are among the most critical elements in high speed digital circuits. Power consumption, area, jitter and wide tuning range are key design metrics in these circuits. To provide a wide range of clock frequencies, Digitally Controlled Ring Oscillators (DCROs), whose frequencies are discretely tuned using a Frequency Code Word (FCW), have been investigated in recent studies. They have several advantages over LC-based Voltage Controlled Oscillators (VCO) including simplicity of design, small die area (i.e. no large inductors), better compatibility with deep submicron CMOS processes,ability to offer multiple output phases, and wider tuning range.A compact differential Injection Locked Clock Multiplier (ILCM) based on an injection locked DCRO is implemented in this thesis. As the transistor features continuously shrink and the supply voltage is reduced, ILCMs are becoming more prone to issues such as increased effect of random mismatch, increased device noise, susceptibility of the design to noise coupling and vulnerability to Process Voltage and Temperature (PVT) variations. Furthermore, ILCMs in recent System on a Chip (SoCs) have stringent design requirements including accurate frequency tuning, fine fractional resolution, high levels of integration and better amenability to technology scaling. In the proposed ILCM, multiple techniques were used to address deep submicron CMOS design challenges, as well as modern applications’ requirements. The design is fully digital, synthesizable and automatically placed and routed. All circuit blocks were implemented using digital design flow and designed using a Hardware Description Language (HDL). This allows the design to be more easily ported to deep submicron processes. Online or offline PVT calibration can be performed using a replica oscillator and high speed digital counters to track frequency drifts with PVT variations. A DCRO based on a matrix structure has been utilized to reduce period variations due to random mismatch. The DCRO is built up from pseudo differential delay cells to enhance design immunity to noise coupling. The key thesis contributions are implementing a new DCRO structure using fully syntheziable differential structure, utilizing a novel PVT calibrator that can compensate for frequency mismatch between the main DCRO and its replica, and using a low complexity fractional ILCM technique that achieves a fine fractional resolution with few number of ring oscillator stages.Designed in a TSMC 65 nm GP CMOS process with no analog or RF enhancements, the proposed ILCM frequency ranges from 1.0 to 1.8 GHz and occupies 124:5 m 170 m of chip area. The ILCM can operate in integer or fractional mode for multiplication ratios up to 9. At 1.7 GHz and 1.1 V, the measured integrated RMS jitter (1 kHz to 30 MHz) for the 3rd and 9th multiplication factors are 197 fs and 381 fs, respectively. The ILCM consumes 13.25 mW of power and has a fraction resolution of fref=32. Furthermore, it achieves a jitter-power FOM of −241 dB, when measured at room temperature and 1.1 V. When tested in the presence of switching noise, it provides up to 7 dB improvement in phase noise when compared to a single ended version of the ILCM. In the presence of voltage variations (from 0.9 V to 1.1 V) and temperature variations (from 30 C to 70 C), the maximum integrated RMS jitter variation observed was 50 fs.

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O presente trabalho propõe-se a oferecer respostas à questão de como a informação é preservada num sistema, focalizando-se na distinção entre os papéis desempenhados pelos constituintes elementares e pelos estruturais na preservação da memória desse sistema. Os sistema simulados circunscreveram-se a malhas, com diferentes graus de regularidade, compostas pelo acoplamento de osciladores não-lineares que apresentam comportamento coerente no estado de equilíbrio. Malhas de Sincronismo de Fase, também conhecidas por PLLs (Phase Locked Loops), foram adotadas como elementos constituintes básicos dos sistemas analisados. Para tanto, utilizou-se a plataforma de cálculo MATLAB-SIMULINK, acompanhando-se as evoluções dos diversos sistemas e de seus parâmetros dinâmicos associados, possibilitando o estabelecimento da correspondência entre os valores dos referidos parâmetros dinâmicos com parâmetros gráficos \"sensíveis\" à estrutura das malhas. Os resultados obtidos indicam a coexistência/cooperação das componentes estrutural e elementar na determinação dos valores dos parâmetros dinâmicos no estado de equilíbrio do sistema. No entanto, evidencia-se que tais componentes apresentam importâncias distintas na determinação dos diferentes parâmetros dinâmicos. / This work was conceived aiming to present some answers to how the information is preserved in a system. The focus was laid on the distinction between the tasks played by the elementary components and the structure of the system. The simulated systems were composed by coupled oscillators, more precisely by PLLs (Phase Locked Loops), arranged in networks of different regularities. Simulations were performed using Matlab-Simulink software to build a correlation between the final state dynamical parameters of the system and its degree of regularity. Results show the influence of both elementary and structural components on the system attained state. However the responses of characteristics parameters of the system to changes in the regularity of the structured network may greatly differ from one parameter to another. This behavior may suggest different strategies to preserve information of the system according to the information to be kept.

A distribuição de sinais de tempo é um fator essencial em muitas aplicações de engenharia como, por exemplo, redes de telecomunicações, circuitos digitais integrados e sistemas de automação. Nas últimas décadas essa tarefa foi realizada, predominantemente, com redes mestre-escravo nas quais existem osciladores de referência que distribuem o sinal de tempo para osciladores escravos (PLLs) construídos para extrair a base de tempo a partir do sinal da linha. Recentemente, entretanto, o surgimento de redes de comunicação wire-less com conectividade dinâmica e o aumento dos tamanhos e das freqüências de operação dos circuitos digitais integrados indicam a necessidade de utilização de estratégias de distribuição de sinais de tempo baseadas em redes mutuamente conectadas. Nesse trabalho são estudadas redes mutuamente conectadas de PLLs para a determinação de condições para a obtenção do sincronismo de redes desse tipo em função dos parâmetros individuais dos nós e da conectividade da rede. Determinou-se também, através de simulações numéricas, a validade dos resultados analíticos obtidos. Finalmente foi estabelecido um método, baseado em algoritmos evolutivos, para a otimização dos parâmetros da rede considerando objetivos de robustez e capacidade de rejeição de ruídos na rede. / Clock-distribution is an essential feature in many engineering applications as, for example, telecommunications networks and digital integrated circuits. In the last few decades this problem was predominantly addressed using master-slave strategies. In this type of strategy there are precise reference oscillators in the network called masters and their signals are distributed in the network, other oscillators called slaves (PLLs) extract the time basis from the line signals. Recently the development of wireless communication networks and the increasing size of digital integrated circuits and their rising operation frequencies indicate the need for the use of mutually-connected networks for the issue of clock-distribution. In this work mutually-connected networks of PLLs are studied in order to obtain conditions for the acquisition of a synchronous state for the network concerning the node parameters and the connection pattern of the network. Furthermore, numerical experiments were conducted to validate analytic results. Finally, a method is proposed, based on evolutionary algorithms, for the optimization of the network parameters considering the robustness and the ability to reject noise in the network as objectives.

The work was based on digitally controlled oscillator for an all-digital PLL in 65nm process. Phase locked loop’s were used in most of the application for clock generation and recovery as well. As the technology grows faster in the existinggeneration, there has to be quick development with the technique. In such case ananalog PLL which was used earlier gradually getting converted to digital circuit.All-digital PLL blocks does the same work as an analog PLL blocks, but thecircuits and other control circuitry designed were completely in digital form, becausedigital circuit has many advantages over analog counterpart when they arecompared with each other. Digital circuit could be scaled down or scaled up evenafter the circuits were designed. It could be designed for low power supply voltageand easy to construct in a 65 nm process. The digital circuit was widely chosento make life easier. In most of the application PLL’s were used for clock and data recovery purpose,from that perspective jitter will stand as a huge problem for the designers. Themain aim of this thesis was to design a DCO that should bring down the jitter asdown as possible which was designed as standalone, the designed DCO would belater placed in an all-digital PLL. To understand the concept and problem aboutjitter at the early stage of the project, an analog PLL was designed in block leveland tested for different types of jitter and then design of a DCO was started. This document was about the design of a digitally controlled oscillator whichoperates with the center frequency of 2.145 GHz. In the first stage of the projectthe LC tank with NMOS structure was built and tested. In the latter stage the LCtank was optimized by using PMOS structure as negative resistance and eventuallyended up with NMOS and PMOS cross coupled structure. Tuning banks were oneof the main design in this project which plays a key role in locking the system ifthe DCO is placed in an all-digital PLL system. So, three types of tuning bankswere introduced to make the system lock more precisely. The control circuits andthe varactors built were all digital and hence it is called as digitally controlledoscillator. Digital control circuits, other sub-blocks like differential to single endedand simple buffers were also designed to optimize the signal and the results wereshown.DCO and tuning banks were tested using different types of simulation and were tested for different jitter qualities and analysis. The simulation results are shownin the final chapter simulation and results.