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Os elevados níveis de potência e desempenho solicitados pelas presentes e futuras aplicações de conversores estáticos de potência podem ser atingidos pela interconexão de unidades básicas menores (multiconversor). Com a utilização de uma estratégia de controle adequada consegue-se não apenas a potência total desejada e sua correta divisão entre as várias unidades básicas como também uma redução no conteúdo harmônico das correntes e tensões resultantes. Neste trabalho, algumas topologias de multiconversores monofásicos do tipo fonte de tensão são modeladas, analisadas e comparadas quanto às solicitações de corrente e tensão nos diversos componentes, e quanto ao espectro da corrente resultante. Desta discussão conclui-se que a \"Conexão em Paralelo de Conversores Sem Transformador\" (PCTL- parallel connection/transformerless) é viável, levando-se em conta as demais topologias e a tecnologia disponível em semicondutores de potência. A análise do modelo matemático e da matriz de controlabilidade do caso PCTL trifásico resulta em métodos de desacoplamento das entradas do multiconversor. Baseando-se nestes métodos, são propostas três estratégias de controle utilizando controladores de corrente monofásicos individuais. Dois deles utilizam PWM com portadora triangular, e o outro, um PWM por banda de tolerância. Para um dos casos, baseados em PWM a portadora triangular, propõe-se um processo de minimização de harmônicos de corrente, injetando-se à referência de cada modulador PWM um sinal de \"seqüência zero instantânea\", obtido a partir da solução de um problema de otimização. Para o caso baseado em banda de tolerância, conseguem-se satisfazer os critérios de desacoplamento pela sincronização e igual defasagem das funções de chaveamento dos diversos conversores via malhas PLL, e também pela injeção de uma corrente fictícia de \"seqüência zero instantânea\" às referências do controlador de corrente. Para os controladores propostos, discute-se a operação do PCTL durante a ocorrência de falhas ou manutenção. Apenas os conversores do tipo fonte de tensão são abordados neste trabalho. / The high power and performance levels required for the present and future power electronics converters can be achieved by connecting a set of smaller power units (multiconverter). By using appropriate control, not only perfect sharing of the power among the converters, but also harmonics reduction is obtained. This thesis presents, analyses and compares some multiconverter topologies, based on the values of the voltages and currents in the main components and in the spectra of the resulting current. As a result, the transformerless parallel connection of converters PCTL is shown to be a feasible solution, taking into account the existing power devices technology. The analysis of the three phase PCTL model and its controllability matrix suggests methods for decoupling the PCTL inputs. This results in two methods using carrier based current controller and one method using a \"tolerance band (TB)\" based controller. For the carrier based one, the injection of an optimized zero sequence reference voltage produces a reduction in the ripple of the individual currents. For the tolerance based one, the inputs coupling is reduced by the use of PLL synchronized PWM and by the injection of a \"fictitious zero sequence current in the TB controller. The operation of the PCTL under faults and maintenance condition is discussed. Only the voltage source converter is studied here.

Os elevados níveis de potência e desempenho solicitados pelas presentes e futuras aplicações de conversores estáticos de potência podem ser atingidos pela interconexão de unidades básicas menores (multiconversor). Com a utilização de uma estratégia de controle adequada consegue-se não apenas a potência total desejada e sua correta divisão entre as várias unidades básicas como também uma redução no conteúdo harmônico das correntes e tensões resultantes. Neste trabalho, algumas topologias de multiconversores monofásicos do tipo fonte de tensão são modeladas, analisadas e comparadas quanto às solicitações de corrente e tensão nos diversos componentes, e quanto ao espectro da corrente resultante. Desta discussão conclui-se que a \"Conexão em Paralelo de Conversores Sem Transformador\" (PCTL- parallel connection/transformerless) é viável, levando-se em conta as demais topologias e a tecnologia disponível em semicondutores de potência. A análise do modelo matemático e da matriz de controlabilidade do caso PCTL trifásico resulta em métodos de desacoplamento das entradas do multiconversor. Baseando-se nestes métodos, são propostas três estratégias de controle utilizando controladores de corrente monofásicos individuais. Dois deles utilizam PWM com portadora triangular, e o outro, um PWM por banda de tolerância. Para um dos casos, baseados em PWM a portadora triangular, propõe-se um processo de minimização de harmônicos de corrente, injetando-se à referência de cada modulador PWM um sinal de \"seqüência zero instantânea\", obtido a partir da solução de um problema de otimização. Para o caso baseado em banda de tolerância, conseguem-se satisfazer os critérios de desacoplamento pela sincronização e igual defasagem das funções de chaveamento dos diversos conversores via malhas PLL, e também pela injeção de uma corrente fictícia de \"seqüência zero instantânea\" às referências do controlador de corrente. Para os controladores propostos, discute-se a operação do PCTL durante a ocorrência de falhas ou manutenção. Apenas os conversores do tipo fonte de tensão são abordados neste trabalho. / The high power and performance levels required for the present and future power electronics converters can be achieved by connecting a set of smaller power units (multiconverter). By using appropriate control, not only perfect sharing of the power among the converters, but also harmonics reduction is obtained. This thesis presents, analyses and compares some multiconverter topologies, based on the values of the voltages and currents in the main components and in the spectra of the resulting current. As a result, the transformerless parallel connection of converters PCTL is shown to be a feasible solution, taking into account the existing power devices technology. The analysis of the three phase PCTL model and its controllability matrix suggests methods for decoupling the PCTL inputs. This results in two methods using carrier based current controller and one method using a \"tolerance band (TB)\" based controller. For the carrier based one, the injection of an optimized zero sequence reference voltage produces a reduction in the ripple of the individual currents. For the tolerance based one, the inputs coupling is reduced by the use of PLL synchronized PWM and by the injection of a \"fictitious zero sequence current in the TB controller. The operation of the PCTL under faults and maintenance condition is discussed. Only the voltage source converter is studied here.

Made available in DSpace on 2014-06-11T19:30:32Z (GMT). No. of bitstreams: 0 Previous issue date: 2009-11-25Bitstream added on 2014-06-13T21:01:20Z : No. of bitstreams: 1 oliveira_vjs_dr_ilha.pdf: 2584742 bytes, checksum: ae7b3113a196a5051a808dbb371dece4 (MD5) / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS... / In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture

In this work concepts and circuits for local clock generation in low-power heterogeneous multiprocessor systems-on-chip (MPSoCs) are researched and developed. The targeted systems feature a globally asynchronous locally synchronous (GALS) clocking architecture and advanced power management functionality, as for example fine-grained ultra-fast dynamic voltage and frequency scaling (DVFS). To enable this functionality compact clock generators with low chip area, low power consumption, wide output frequency range and the capability for ultra-fast frequency changes are required. They are to be instantiated individually per core. For this purpose compact all digital phase-locked loop (ADPLL) frequency synthesizers are developed. The bang-bang ADPLL architecture is analyzed using a numerical system model and optimized for low jitter accumulation. A 65nm CMOS ADPLL is implemented, featuring a novel active current bias circuit which compensates the supply voltage and temperature sensitivity of the digitally controlled oscillator (DCO) for reduced digital tuning effort. Additionally, a 28nm ADPLL with a new ultra-fast lock-in scheme based on single-shot phase synchronization is proposed. The core clock is generated by an open-loop method using phase-switching between multi-phase DCO clocks at a fixed frequency. This allows instantaneous core frequency changes for ultra-fast DVFS without re-locking the closed loop ADPLL. The sensitivity of the open-loop clock generator with respect to phase mismatch is analyzed analytically and a compensation technique by cross-coupled inverter buffers is proposed. The clock generators show small area (0.0097mm2 (65nm), 0.00234mm2 (28nm)), low power consumption (2.7mW (65nm), 0.64mW (28nm)) and they provide core clock frequencies from 83MHz to 666MHz which can be changed instantaneously. The jitter performance is compliant to DDR2/DDR3 memory interface specifications. Additionally, high-speed clocks for novel serial on-chip data transceivers are generated. The ADPLL circuits have been verified successfully by 3 testchip implementations. They enable efficient realization of future low-power MPSoCs with advanced power management functionality in deep-submicron CMOS technologies. / In dieser Arbeit werden Konzepte und Schaltungen zur lokalen Takterzeugung in heterogenen Multiprozessorsystemen (MPSoCs) mit geringer Verlustleistung erforscht und entwickelt. Diese Systeme besitzen eine global-asynchrone lokal-synchrone Architektur sowie Funktionalität zum Power Management, wie z.B. das feingranulare, schnelle Skalieren von Spannung und Taktfrequenz (DVFS). Um diese Funktionalität zu realisieren werden kompakte Taktgeneratoren benötigt, welche eine kleine Chipfläche einnehmen, wenig Verlustleitung aufnehmen, einen weiten Bereich an Ausgangsfrequenzen erzeugen und diese sehr schnell ändern können. Sie sollen individuell pro Prozessorkern integriert werden. Dazu werden kompakte volldigitale Phasenregelkreise (ADPLLs) entwickelt, wobei eine bang-bang ADPLL Architektur numerisch modelliert und für kleine Jitterakkumulation optimiert wird. Es wird eine 65nm CMOS ADPLL implementiert, welche eine neuartige Kompensationsschlatung für den digital gesteuerten Oszillator (DCO) zur Verringerung der Sensitivität bezüglich Versorgungsspannung und Temperatur beinhaltet. Zusätzlich wird eine 28nm CMOS ADPLL mit einer neuen Technik zum schnellen Einschwingen unter Nutzung eines Phasensynchronisierers realisiert. Der Prozessortakt wird durch ein neuartiges Phasenmultiplex- und Frequenzteilerverfahren erzeugt, welches es ermöglicht die Taktfrequenz sofort zu ändern um schnelles DVFS zu realisieren. Die Sensitivität dieses Frequenzgenerators bezüglich Phasen-Mismatch wird theoretisch analysiert und durch Verwendung von kreuzgekoppelten Taktverstärkern kompensiert. Die hier entwickelten Taktgeneratoren haben eine kleine Chipfläche (0.0097mm2 (65nm), 0.00234mm2 (28nm)) und Leistungsaufnahme (2.7mW (65nm), 0.64mW (28nm)). Sie stellen Frequenzen von 83MHz bis 666MHz bereit, welche sofort geändert werden können. Die Schaltungen erfüllen die Jitterspezifikationen von DDR2/DDR3 Speicherinterfaces. Zusätzliche können schnelle Takte für neuartige serielle on-Chip Verbindungen erzeugt werden. Die ADPLL Schaltungen wurden erfolgreich in 3 Testchips erprobt. Sie ermöglichen die effiziente Realisierung von zukünftigen MPSoCs mit Power Management in modernsten CMOS Technologien.

Cette thèse traite de synthétiseurs de fréquence, et plus précisément de diviseurs de fréquence fractionnaires qui sont des blocs critiques en radiocommunications. Une nouvelle méthode pour la division de fréquence fractionnaire y est présentée : Elle est basée sur la répartition aléatoire de l'erreur de phase. Deux implémentations de cette méthode sont proposées. Le spectre du bruit de phase en sortie de diviseur est débarrassé de toute raie parasite. L'énergie habituellement contenue dans ces raies étant uniformément répartie sur l'ensemble du spectre, ce dernier adopte un profil plat. La solution proposée peut être implémentée dans des synthétiseurs de fréquence tels que les Boucles à Verrouillage de Phase (PLL). Puisque aucune mise en forme du bruit n'est appliquée par le diviseur, la bande passante de la PLL peut être optimisée. Dans ces conditions, la possibilité d'une modulation directe haut débit de la PLL résultante est étudiée. Pour finir, des solutions d'optimisation du système résultant sont étudiées. / This dissertation deals with frequency synthesis and more specifically with the fractional frequency divider, one of the most critical blocks in radio frequency systems. A new fractional division method is presented along with two possible embodiments. It is based on a random dithering of the phase error. The divider output spectrum is cleaned from any fractional spurious tone. The spurious tones energy is uniformly spread on the whole spectrum, without noise shaping. The proposed solution can be implemented in frequency synthesizers like Phase Locked Loops (PLL). As no noise shaping is applied, the PLL bandwidth can be optimized. In this context, the possibility of high data-rate direct modulation is studied. Finally, solutions for the optimization of the resulting system are inspected.

In this work concepts and circuits for local clock generation in low-power heterogeneous multiprocessor systems-on-chip (MPSoCs) are researched and developed. The targeted systems feature a globally asynchronous locally synchronous (GALS) clocking architecture and advanced power management functionality, as for example fine-grained ultra-fast dynamic voltage and frequency scaling (DVFS). To enable this functionality compact clock generators with low chip area, low power consumption, wide output frequency range and the capability for ultra-fast frequency changes are required. They are to be instantiated individually per core. For this purpose compact all digital phase-locked loop (ADPLL) frequency synthesizers are developed. The bang-bang ADPLL architecture is analyzed using a numerical system model and optimized for low jitter accumulation. A 65nm CMOS ADPLL is implemented, featuring a novel active current bias circuit which compensates the supply voltage and temperature sensitivity of the digitally controlled oscillator (DCO) for reduced digital tuning effort. Additionally, a 28nm ADPLL with a new ultra-fast lock-in scheme based on single-shot phase synchronization is proposed. The core clock is generated by an open-loop method using phase-switching between multi-phase DCO clocks at a fixed frequency. This allows instantaneous core frequency changes for ultra-fast DVFS without re-locking the closed loop ADPLL. The sensitivity of the open-loop clock generator with respect to phase mismatch is analyzed analytically and a compensation technique by cross-coupled inverter buffers is proposed. The clock generators show small area (0.0097mm2 (65nm), 0.00234mm2 (28nm)), low power consumption (2.7mW (65nm), 0.64mW (28nm)) and they provide core clock frequencies from 83MHz to 666MHz which can be changed instantaneously. The jitter performance is compliant to DDR2/DDR3 memory interface specifications. Additionally, high-speed clocks for novel serial on-chip data transceivers are generated. The ADPLL circuits have been verified successfully by 3 testchip implementations. They enable efficient realization of future low-power MPSoCs with advanced power management functionality in deep-submicron CMOS technologies. / In dieser Arbeit werden Konzepte und Schaltungen zur lokalen Takterzeugung in heterogenen Multiprozessorsystemen (MPSoCs) mit geringer Verlustleistung erforscht und entwickelt. Diese Systeme besitzen eine global-asynchrone lokal-synchrone Architektur sowie Funktionalität zum Power Management, wie z.B. das feingranulare, schnelle Skalieren von Spannung und Taktfrequenz (DVFS). Um diese Funktionalität zu realisieren werden kompakte Taktgeneratoren benötigt, welche eine kleine Chipfläche einnehmen, wenig Verlustleitung aufnehmen, einen weiten Bereich an Ausgangsfrequenzen erzeugen und diese sehr schnell ändern können. Sie sollen individuell pro Prozessorkern integriert werden. Dazu werden kompakte volldigitale Phasenregelkreise (ADPLLs) entwickelt, wobei eine bang-bang ADPLL Architektur numerisch modelliert und für kleine Jitterakkumulation optimiert wird. Es wird eine 65nm CMOS ADPLL implementiert, welche eine neuartige Kompensationsschlatung für den digital gesteuerten Oszillator (DCO) zur Verringerung der Sensitivität bezüglich Versorgungsspannung und Temperatur beinhaltet. Zusätzlich wird eine 28nm CMOS ADPLL mit einer neuen Technik zum schnellen Einschwingen unter Nutzung eines Phasensynchronisierers realisiert. Der Prozessortakt wird durch ein neuartiges Phasenmultiplex- und Frequenzteilerverfahren erzeugt, welches es ermöglicht die Taktfrequenz sofort zu ändern um schnelles DVFS zu realisieren. Die Sensitivität dieses Frequenzgenerators bezüglich Phasen-Mismatch wird theoretisch analysiert und durch Verwendung von kreuzgekoppelten Taktverstärkern kompensiert. Die hier entwickelten Taktgeneratoren haben eine kleine Chipfläche (0.0097mm2 (65nm), 0.00234mm2 (28nm)) und Leistungsaufnahme (2.7mW (65nm), 0.64mW (28nm)). Sie stellen Frequenzen von 83MHz bis 666MHz bereit, welche sofort geändert werden können. Die Schaltungen erfüllen die Jitterspezifikationen von DDR2/DDR3 Speicherinterfaces. Zusätzliche können schnelle Takte für neuartige serielle on-Chip Verbindungen erzeugt werden. Die ADPLL Schaltungen wurden erfolgreich in 3 Testchips erprobt. Sie ermöglichen die effiziente Realisierung von zukünftigen MPSoCs mit Power Management in modernsten CMOS Technologien.

In use today are ‘normal’ DC-DC switching regulators with considerable switching noise and ringing, which is bad for noise-sensitive applications. This project involves a solution based on ‘Silent Switchers’ to prove its effectiveness in reducing noise. This idea is then coupled into identifying the susceptibility of a PLL synthesizer to ensure we understand the sensitivity of this type of component and if this can be used with a silent switcher. A particular PLL synthesizer evaluation board is currently powered by linear regulators, which is used as a basis for comparing results. A new board involving silent switchers is designed and manufactured. Phase noise measurements are done to evaluate if silent switchers are a suitable alternative for power supply. / Idag används ’vanliga’ DC-DC switching regulatorer med betydande kopplingsbrus och ringningar, vilket är dåligt för bruskänsliga applikationer. Detta projekt innefattar en lösning baserad på Silent Switchersför att bevisa dess effektivitet när det gäller att minska bruset från dessa regulatorer. Denna lösning används sedan till att identifiera känsligheten hos en PLL-synthesizer för att se till att vi förstår känsligheten hos denna typ av component och om den kan användas med en Silent Switcher". Som referens för studien används ett särskilt PLL-synthesizer- utvärderingskort, drivet av linjära regulatorer. Ett nytt kort med Silent Switchers"istället för linjära regulatorer har konstruerats och tillverkats. Fasbrusmätningar görs på båda korten för att utvärdera om Silent Switchers"är ett lämpligt alternativ för denna applikation.

First, a frequency synthesizer for IEEE 802.15.4 / ZigBee transceiver applications that employs dynamic True Single Phase Clocking (TSPC) circuits in its frequency dividers is presented and through the analysis and measurement results of this synthesizer, the need for low power circuit techniques in frequency dividers is discussed. Next, Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cells are explored for implementing radio-frequency (RF) frequency dividers of low power frequency synthesizers. DCVSL ip- ops offer small input and clock capacitance which makes the power consumption of these circuits and their driving stages, very low. We perform a delay analysis of DCVSL circuits and propose a closed-form delay model that predicts the speed of DCVSL circuits with 8 percent worst case accuracy. The proposed delay model also demonstrates that DCVSL circuits suffer from a large low-to-high propagation delay ( PLH) which limits their speed and results in asymmetrical output waveforms. Our proposed enhanced DCVSL, which we call DCVSL-R, solves this delay bottleneck, reducing PLH and achieving faster operation. We implement two ring-oscillator-based voltage controlled oscillators (VCOs) in 0.13 mu m technology with DCVSL and DCVSL-R delay cells. In measurements, for the same oscillation frequency (2.4GHz) and same phase noise (-113dBc/Hz at 10MHz), DCVSL-R VCO consumes 30 percent less power than the DCVSL VCO. We also use the proposed DCVSL-R circuit to implement the 2.4GHz dual-modulus prescaler of a low power frequency synthesizer in 0.18 mu m technology. In measurements, the synthesizer exhibits -135dBc/Hz phase noise at 10MHz offset and 58 mu m settling time with 8.3mW power consumption, only 1.07mWof which is consumed by the dual modulus prescaler and the buffer that drives it. When compared to other dual modulus prescalers with similar division ratios and operating frequencies in literature, DCVSL-R dual modulus prescaler demonstrates the lowest power consumption. An all digital phase locked loop (ADPLL) that operates for a wide range of frequencies to serve as a multi-protocol compatible PLL for microprocessor and serial link applications, is presented. The proposed ADPLL is truly digital and is implemented in a standard complementary metal-oxide-semiconductor (CMOS) technology without any analog/RF or non-scalable components. It addresses the challenges that come along with continuous wide range of operation such as stability and phase frequency detection for a large frequency error range. A proposed multi-bit bidirectional smart shifter serves as the digitally controlled oscillator (DCO) control and tunes the DCO frequency by turning on/off inverter units in a large row/column matrix that constitute the ring oscillator. The smart shifter block is completely digital, consisting of standard cell logic gates, and is capable of tracking the row/column unit availability of the DCO and shifting multiple bits per single update cycle. This enables fast frequency acquisition times without necessitating dual loop fi lter or gear shifting mechanisms. The proposed ADPLL loop architecture does not employ costly, cumbersome DACs or binary to thermometer converters and minimizes loop filter and DCO control complexity. The wide range ADPLL is implemented in 90nm digital CMOS technology and has a 9-bit TDC, the output of which is processed by a 10-bit digital loop filter and a 5-bit smart shifter. In measurements, the synthesizer achieves 2.5GHz-7.3GHz operation while consuming 10mW/GHz power, with an active area of 0.23 mm2.