Computer memories now play a key role in our everyday life given the increase in the number of connected smart devices and wearables. Recently post-CMOS memory technologies are gaining significant research attention along with the regular ones. Spin Transfer Torque Magnetoresistive RAM (STT-MRAM) is one such post-CMOS memory technology with a rapidly growing commercial interest and potential across diverse application platforms. Research has shown the ability of STT-MRAM to replace different levels of memory hierarchy as well. In brief, STT-MRAM possesses all the favorable properties of a universal memory technology. In this dissertation we have explored the roles of this emerging memory technology beyond traditional storage. The purpose is to enhance the overall performance of the application platform that STT-MRAM is a part of. The roles that we explored are computation and security. We have discussed how the intrinsic properties of STT-MRAM can be used for computation and authentication. The two properties that we are interested in are the dipolar coupling between the magnetic memory cells and the variations in the geometries of the memory cell. Our contributions here are a 22nm CMOS integrated STT-MRAM based logic-in-memory architecture and a geometric variation based STT-MRAM signature generation. In addition we have explored the device physics and the dynamics of STT-MRAM cells to propose a STT based clocking mechanism that is friendlier with the logic-in-memory setup. By investigating the logic layouts and propagation style in the architecture, we have also proposed different techniques that can improve the logic density and performance of the architecture.

The goal of this study was to quantify the ambient air concentrations of polybrominated diphenyl ethers (PBDEs) from three locations within the Howard Curren Wastewater Treatment Facility located in Tampa, Florida. PBDEs have been linked to endocrine disruption, cancer, developmental concerns in children, as well as other toxic effects; however their precise roles concerning these deleterious effects remains to be determined. The present study was motivated by these potential health concerns posed by inhalational exposure to PBDEs. Ambient air was monitored with a Tisch Environmental PUF high volume sampler for 48 hours with collection on three types of media-quarts filter, PUF (polyurethane foam) and XAD-2 resin. The samples were then analyzed with GC/MS (gas chromatography/mass spectrometry) for eight PBDEs that are routinely detected. The results showed elevated levels of PBDEs at the 2nd and 3rd sampling locations indicating a possible increased presence in the ambient air at the facility. Levels of PBDE 47 ranked highest amongst the detected congeners. PBDE 209 was not detected at any site. The present results indicate that PBDEs may lead to an inhalational exposure, thus future experimentation is needed to fully evaluate the health complications associated with inhalational exposure route to PBDEs.

abstract: Digital systems are increasingly pervading in the everyday lives of humans. The security of these systems is a concern due to the sensitive data stored in them. The physically unclonable function (PUF) implemented on hardware provides a way to protect these systems. Static random-access memories (SRAMs) are designed and used as a strong PUF to generate random numbers unique to the manufactured integrated circuit (IC). Digital systems are important to the technological improvements in space exploration. Space exploration requires radiation hardened microprocessors which minimize the functional disruptions in the presence of radiation. The design highly efficient radiation-hardened microprocessor for enabling spacecraft (HERMES) is a radiation-hardened microprocessor with performance comparable to the commercially available designs. These designs are manufactured using a foundry complementary metal-oxide semiconductor (CMOS) 55-nm triple-well process. This thesis presents the post silicon validation results of the HERMES and the PUF mode of SRAM across process corners. Chapter 1 gives an overview of the blocks implemented on the test chip 25. It also talks about the pre-silicon functional verification methodology used for the test chip. Chapter 2 discusses about the post silicon testing setup of test chip 25 and the validation of the setup. Chapter 3 describes the architecture and the test bench of the HERMES along with its testing results. Chapter 4 discusses the test bench and the perl scripts used to test the SRAM along with its testing results. Chapter 5 gives a summary of the post-silicon validation results of the HERMES and the PUF mode of SRAM. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017

付記する学位プログラム名: 充実した健康長寿社会を築く総合医療開発リーダー育成プログラム / 京都大学 / 0048 / 新制・課程博士 / 博士(薬科学) / 甲第21712号 / 薬科博第103号 / 新制||薬科||11(附属図書館) / 京都大学大学院薬学研究科薬科学専攻 / (主査)教授 二木 史朗, 教授 中山 和久, 教授 掛谷 秀昭 / 学位規則第4条第1項該当 / Doctor of Pharmaceutical Sciences / Kyoto University / DFAM

The theme of the thesis is Physical Unclonable Functions (PUF). The following objectives were assigned: to provide a literature research concerning PUFs, to perform a property analysis to select appropriate type of PUF for implementation and to realize an authentication cryptosystem based on the chosen PUF. Based on the research, the cryptosystem was designed based on ring oscillator PUF. The proposed cryptosystem is tested in several scenarios with the maximal rate of successful authentication of 81%. The cryptosystem also allows to be used for device identification. Furthermore, the results were discussed and suitable improvements of design was proposed. Besides the cryptosystem itself, the thesis also introduced a unique comparison of existing types of PUFs.

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Master of Science / We are in an ever-increasing demand for computing power to sustain our technological advancements. A significant driving factor of our progress is the size and speed of memory we possess. Modern computer architectures use DDR4-based DRAM (Dynamic Random Access Memory) to hold all the immediate information for processing needs. Each bit in a DRAM memory module is implemented with a tiny capacitor and a transistor. Since the capacitors are prone to charge leakage, each bit must be frequently rewritten with its old value. A dedicated memory controller handles the periodic refreshes. If the cells aren't refreshed, the bits lose their charge and lose the information stored by flipping to either 0 or 1 (depending upon the design). Due to manufacturing variations, every tiny capacitor fabricated will have different physical characteristics. Charge leakage depends upon capacitance and other such physical properties. Hence, no two DRAM modules can have the same properties and decay pattern and cannot be reproduced again accurately. This DRAM attribute can be considered a source of 'Physically Unclonable Functions' and is sought after in the Cryptography domain. This thesis aims to characterize the decay patterns of commercial DDR4 DRAM modules. I implemented a custom System On Chip on AMD/Xilinx's ZCU104 FPGA platform to interface different DDR4 modules with a primitive memory controller (without refreshes). Additionally, I introduced electric and magnetic fields close to the DRAM module to investigate their effects on the decay characteristics.

Modern Field-Programmable Gate Arrays (FPGAs) can accommodate complex system-on-chip designs and require extensive intellectual-property (IP) support. However, current IP protection mechanisms in FPGAs are limited, and do not reach beyond whole-design bitstream encryption. This work presents an architecture and protocol for securing IP based designs in programmable platforms. The architecture is reprsented by the Secure Authentication Module (SAM), an enabler for next-generation intellectual-property exchange in complex FPGAs. SAM protects hardware, software, application data, and also provides mutual assurances for the end-user and the intellectual-property developer. Further, this work demonstrates the use of SAM in a secure video messaging device on top of a Virtex-II Pro development system. / Master of Science