Intensity modulation direct detection (IMDD) transmission scheme has been the mainstay in optical communication ever since semiconductor lasers were put to use as the choice transmission sources. With the development of new improved laser types, this method will continue to dominate the third generation light wave networks where bit rates have steadily risen beyond 10Gbps mark. The main attraction of this scheme lies in its simplicity. With EDFA amplifiers providing a cost effective solution to the attenuation problem, long haul network capacity under the scheme has greatly increased. At the design stage of such systems, it is essential to accurately predict the behavior of each system component right from the laser transmitter up to the optical receiver under custom specific operating conditions and laser diodes are one of the key components for a wide range of light wave communication systems. For this purpose, computer-aided simulation techniques based on behavioral models of laser diodes have been developed and validated for a variety of applications [4-8]. A ‘representative’ behavior model, which closely approximates the device’s actual physical model, is essential to the system designer. Unfortunately, the component vendor or manufacturer may not be able to provide all the information needed to predict such behavior. The only information that can be made available, are certain measured variables over a specified measurement range. The designer therefore, needs a tool to effectively convert this data into a useful model with sufficiently accurate parameters for predicting behavior. As the complexity of the model increases, more detailed knowledge of the laser is required and the computation time for system performance calculation increases. While sophisticated models provide considerable insight into important characteristics of the lasers, for system simulation purposes a relatively simple model is often adequate. In this thesis we will propose a very robust and efficient procedure for estimating the modal parameters and go on to propose a complete solution to the 0D laser model extending to such domains as the below threshold dynamics and temperature effects. / Thesis / Master of Engineering (ME)

This dissertation presents the systematic analysis and the critical assessment of the AC side soft-switching inverters in electric vehicle (EV) applications. Although numerous soft-switching inverter techniques were claimed to improve the inverter performance, compared with the conventional hard-switching inverter, there is the lack of comprehensive investigations of analyzing and evaluating the performance of soft-switching inverters. Starting with an efficiency comparison of a variety of the soft-switching inverters using analytical calculation, the dissertation first reveals the effects of the auxiliary circuit's operation and control on the loss reduction. Three types of soft-switching inverters realizing the zero-voltage-transition (ZVT) or zero-current-transition (ZCT) operation are identified to achieve high efficiency operation. Then one hard-switching inverter and the chosen soft-switching inverters are designed and implemented with the 55 kW power rating for the small duty EV application. The experimental evaluations on the dynamometer provide the accurate description of the performance of the soft-switching inverters in terms of the loss reductions, the electromagnetic interference (EMI) noise, the total harmonic distortion (THD) and the control complexity. An analysis of the harmonic distortion caused by short pulses is presented and a space vector modulation scheme is proposed to alleviate the effect. To effectively analyze the soft-switching inverters' performance, a simulation based electrical modeling methodology is developed. Not only it extends the EMI noise analysis to the higher frequency region, but also predicts the stress and the switching losses accurately. Three major modeling tasks are accomplished. First, to address the issues of complicated existing scheme, a new parameter extraction scheme is proposed to establish the physics-based IGBT model. Second, the impedance based measurement method is developed to derive the internal parasitic parameters of the half-bridge modules. Third, the finite element analysis software is used to develop the model for the laminated bus bar including the coupling effects of different phases. Experimental results from the single-leg operation and the three-phase inverter operation verify the effectiveness of the presented systematic electrical modeling approach. With the analytical tools verified by the testing results, the performance analysis is further extended to different power ratings and different bus voltage designs. / Ph. D.

The goal of this dissertation is to present a systematic approach to integrating the multidisciplinary design process in power electronics through the integration of existing CAD tools, multidisciplinary modeling and system optimization. Two major benefits are expected from the utilization of the proposed integrated design methodology. Firstly, it will significantly speed up the design process and will eliminate errors resulting from repeated manual data entry and information exchange. Secondly, the integrated design optimization will result in better utilization of materials and components. In order to understand the basic relationship between electrical and thermal phenomena, the self-heating effect of a simple copper conductor is modeled analytically. Based on these models, a guideline for copper trace design is proposed. The next step towards developing an integrated design methodology is to create threedimensional solid-body-based models that characterize the electrical, thermal and mechanical properties. The electrical model of an integrated power electronics module (IPEM), including parasitic parameters, is developed and experimentally verified with impedance measurements. Together with the thermal model, it lays the foundation for the integrated electrical and thermal analysis and design. The software integration framework is presented along with the software tools chosen for this study, which include Saber for electrical circuit simulation, Maxwell Q3D Extractor for parameter extraction, and I-DEAS for geometry and thermal modeling. Each of these software tools is controlled via its own macro language files. iSIGHT is then used to interface with these tools in order to achieve software integration. The DC-DC IPEM layout design is investigated and improved upon by using the integrated design methodology. Several examples of parametric study are presented. The first example shows the tradeoff between electrical and thermal performance for different ceramic layer thicknesses of module substrate. The next example looks at the commonmode noise problem that exists in different direct-bonded copper (DBC) layouts. / Ph. D.

Selon la feuille de route des industriels de la microélectronique (ITRS), la dimension critiqueminimum des MOSFET en 2026 ne devrait être que de 6 nm [1]. La miniaturisation du CMOS reposeessentiellement sur deux approches, à savoir la réduction des dimensions géométriques physiques etdes dimensions équivalentes. La réduction géométrique des dimensions conduit à la diminution desdimensions critiques selon la « loi » de Moore, qui définit les tendances de l’industrie dessemiconducteurs. Comme la taille des dispositifs est réduite de façon importante, davantage d’effortssont consentis pour maintenir les performances des composants en dépit des effets de canaux courts,des fluctuations induites par le nombre de dopants…. [2-4]. D’autre part, la réduction des dimensionséquivalentes devient de plus en plus importante de nos jours et de nouvelles solutions pour laminiaturisation reposant sur la conception et les procédés technologiques sont nécessaires. Pour cela,des solutions nouvelles sont nécessaires, en termes de matériaux, d’architectures de composants et detechnologies, afin d’atteindre les critères requis pour la faible consommation et les nouvellesfonctionnalités pour les composants futurs (“More than Moore” et “Beyond CMOS”). A titred’exemple, les transistors à film mince (TFT) sont des dispositifs prometteurs pour les circuitsélectroniques flexibles et transparents. / Novel advanced metal-oxide semiconductor (MOS) devices such as fully-depleted-silicon-on-insulator (FD-SOI) Tri-gate transistor, junctionless transistor, and amorphous-oxide-semiconductor thin film transistor were developed for continuing down-scaling trend and extending the functionality of CMOS technology, for example, the transparency and the flexibility. In this dissertation, the electrical characteristics and modeling of these advanced MOS devices are presented and they are analyzed. The sidewall mobility trends with temperature in multi-channel tri-gate MOSFET showed that the sidewall conduction is dominantly governed by surface roughness scattering. The degree of surface roughness scattering was evaluated with modified mobility degradation factor. With these extracted parameters, it was noted that the effect of surface roughness scattering can be higher in inversion-mode nanowire-like transistor than that of FinFET. The series resistance of multi-channel tri-gate MOSFET was also compared to planar device having same channel length and channel width of multi-channel device. The higher series resistance was observed in multi-channel tri-gate MOSFET. It was identified, through low temperature measurement and 2-D numerical simulation, that it could be attributed to the variation of doping concentration in the source/drain extension region in the device. The impact of channel width on back biasing effect in n-type tri-gate MOSFET on SOI material was also investigated. The suppressed back bias effects was shown in narrow device (Wtop_eff = 20 nm) due to higher control of front gate on overall channel, compared to the planar device (Wtop_eff = 170 nm). The variation of effective mobility in both devices was analyzed with different channel interface of the front channel and the back channel. In addition, 2-D numerical simulation of the the gate-to-channel capacitance and the effective mobility successfully reconstructed the experimental observation. The model for the effective mobility was inherited from two kinds of mobility degradations, i.e. different mobility attenuation along lateral and vertical directions of channel and additional mobility degradation in narrow device due to the effect of sidewall mobility. With comparison to inversion-mode (IM) transistors, the back bias effect on tri-gate junctionless transistors (JLTs) also has been investigated using experimental results and 2-D numerical simulations. Owing to the different conduction mechanisms, the planar JLT shows more sensitive variation on the performance by back biasing than that of planar IM transistors. However, the back biasing effect is significantly suppressed in nanowire-like JLTs, like in extremely narrow IM transistors, due to the small portion of bulk neutral channel and strong sidewall gate controls. Finally, the characterization method was comprehensively applied to a-InHfZnO (IHZO) thin film transistor (TFT). The series resistance and the variation of channel length were extracted from the transfer curve. And mobility values extracted with different methods such as split C-V method and modified Y-function were compared. The static characteristic evaluated as a function of temperature shows the degenerate behavior of a-IHZO TFT inversion layer. Using subthreshold slope and noise characteristics, the trap information in a-IHZO TFT was also obtained. Based on experimental results, a numerical model for a-IHZO TFT was proposed, including band-tail states conduction and interface traps. The simulated electrical characteristics were well-consistent to the experimental observations. For the practical applications of novel devices, the electrical characterization and proper modeling are essential. These attempts shown in the dissertation will provides physical understanding for conduction of these novel devices.

No description available.

Honigbienen (Apis mellifera L.) sind in der Lage mit ihren Komplexaugen visuelle Muster wahrzunehmen und die Musterinformation im Zentralen Nervensystem zu speichern und für Ähnlichkeitsbewertungen wieder abzurufen. Die vorliegende Arbeit zeigt klare Evidenz gegen eine ausschließliche Bewertung von Schwarzweißmustern mit Hilfe von Template-Matching-Mechanismen. Mit systematisch abgewandelten Dressurparadigmen trainierte Bienen bewerteten Muster unabhängig von der erfolgten Dressur stets bevorzugt gemäß eher grober Mustereigenschaften, wie zum Beispiel die Parameter "schwarzer Musterzentralbereich" und "Musterzerstreutheit". Veränderte man in einem weiteren Versuchansatz die Musterinformation der Schwarzweißmuster zudem gezielt durch geeignete Fourier-Filterung, zeigte sich, dass Bienen zur Musterdiskriminierung bereits die Frequenzinformation von 2 - 8 Schwingungen/Bildbreite genügte. Diese Unschärfe der bewerteten Bildinformation ließ sich nicht ausschließlich aus den optischen Eigenschaften des visuellen Apparates der Bienen ableiten. Videodokumentationen und Einzelbildanalyse des Flugverhaltens der Bienen vor den Mustern ergaben zudem keinerlei Hinweise für eine Nutzung des Flugverhaltens als Bewertungsgrundlage zur Musterdiskriminierung. Die erhaltenen Ergebnisse zur Musterdiskriminierung wurden vor dem Hintergrund eines ökonomischen Entscheidungsmodells für menschliches Verhalten, den Frugalheuristiken, diskutiert und Hinweise auf eine ökonomische Bewertungsstrategie der Bienen entsprechend einer Take-The-Best-Heuristik gefunden. / Honeybees (Apis mellifera L.) are able to perceive visual patterns through their compound eyes and store the visual information in the central nervous system for subsequent use in pattern discrimination tasks. This thesis provides clear evidence against the assumption that pattern discrimination relies exclusively on template matching mechanisms. Bees discriminated pairs of patterns preferential using extracted pattern parameters. Within this thesis the preferred parameters of the bees following the training paradigms were coarse parameters such as "black centre" and "pattern disruption". In experiments with Fourier filtered patterns the frequency information of the patterns were additionally reduced. The results showed that bees could discriminate patterns using only 2 - 8 cycles/pattern-width of the frequency information. The fuzziness of the exploited visual information could not be assigned to restrictions of the visual system of bees. Additional documentation and single picture analysis of the videotaped flight behaviour in front of the patterns provided no evidence for bees using their flight behaviour in order to enhance the pattern discrimination ability. Application of economic human decision models (frugal heuristics) to the behavioural results showed clues that bees'' decisions could be explained with the help of the Take-The-Best-heuristic.

Une des principales solutions technologiques liées à la réduction d’échelle de la technologie CMOS est aujourd’hui clairement orientée vers les transistors MOSFET faiblement dopés à multiples grilles. Ceux-ci proposent une meilleure immunité contre les effets canaux courts comparés aux transistors MOSFET bulk planaires (cf. ITRS 2011). Parmi les MOSFETs à multiples grilles, le transistor FinFET SOI est un candidat intéressant de par la similarité de son processus de fabrication avec la technologie des transistors planaires. En parallèle, il existe une réelle attente de la part des concepteurs et des fonderies à disposer de modèles compacts efficaces numériquement, précis et proches de la physique, insérés dans les « design tools » permettant alors d’étudier et d’élaborer des circuits ambitieux en technologie FinFET. Cette thèse porte sur l’élaboration d’un modèle compact orienté conception du transistor FinFET valide aux dimensions nanométriques. Ce modèle prend en compte les effets canaux courts, la modulation de longueur de canal, la dégradation de la mobilité, leseffets de mécanique quantique et les transcapacités. Une validation de ce modèle est réalisée par des comparaisons avec des simulations TCAD 3D. Le modèle compact est implémenté en langage Verilog-A afin de simuler des circuits innovants à base de transistors FinFET. Une modélisation niveau-porte est développée pour la simulation de circuits numériques complexes. Cette thèse présente également un modèle compact générique de transistors MOSFET SOI canaux long faiblement dopés à multiple grilles. La dépendance à la température est prise en compte. Selon un concept de transformation géométrique, notre modèle compact du transistor MOSFET double grille planaire est étendu pour s’appliquer à tout autre type de transistor MOSFET à multiple grille (MuGFET). Une validation expérimentale du modèle MuGFET sur un transistor triple grille est proposée. Cette thèse apporte enfin des solutions pour la modélisation des transistors MOSFET double grille sans jonction. / One of the main technological solutions related to downscaling of CMOS technology is now clearly oriented to lightly doped multigate MOSFETs. They offer better immunity against short channel effects compared to planar bulk MOSFETs (see ITRS 2011). Among the multigate MOSFETs, the SOI FinFET transistor is an interesting candidate because of the similarity of its manufacturing process with the planar transistor technology. In parallel, there is a real expectation on the part of designers and foundries to have compact models numerically efficient, accurate and close to the physics, and then inserted in to the design tools in order to study and develop ambitious circuits in FinFET technology. This thesis focuses on the development of a design-oriented compact model of FinFET transistor valid to nanoscale dimensions. This model takes into account the short channel effects, the channel length modulation, the mobility degradation, the quantum mechanic effects and the transcapacitances. A validation of this model is carried out by comparisons with 3DTCAD simulations. The compact model is implemented in Verilog-A to simulate innovative FinFET-based circuits. A gate-level modeling is developed for the simulation of complex digital circuits. This thesis also presents a generic compact modeling of multigate SOI MOSFETs with lightly doped channels and temperature dependent. According to a concept of geometric transformation, our compact model of the planar double-gate MOSFET is extended to be applied to any other type of multigate MOSFETs (MuGFET). An experimental validation of the MuGFET compact model with a triple gate transistor is proposed. This thesis finally brings solutions for the modeling of junction less double-gate MOSFET.

Les propriétés électriques et physiques de structures à faible dimensionalité ont été étudiées pour des applications dans des domaines divers comme l’électronique, les capteurs. La mesure du bruit bruit à basse fréquence est un outil très utile pour obtenir des informations relatives à la dynamique des porteurs, au piègeage des charges ou aux mécanismes de collision. Dans cette thèse, le transport électronique et le bruit basse fréquence mesurés dans des structures à faible dimensionnalité comme les dispositifs multi-grilles (FinFET, JLT…), les nanofils 3D en Si/SiGe, les nanotubes de carbone ou à base de graphène sont présentés. Pour les approches « top-down » et « bottom-up », l’impact du bruit est analysé en fonction de la dimensionalité, du type de conduction (volume vs surface), de la contrainte mécanique et de la présence de jonction metal-semiconducteur. / Electrical and physical properties of low-dimensional structures have been studied for the various applications such as electronics, sensors, and etc. Low-frequency noise measurement is also a useful technique to give more information for the carrier dynamics correlated to the oxide traps, channel defects, and scattering. In this thesis, the electrical transport and low-frequency noise of low-dimensional structure devices such as multi-gate structures (e.g. FinFETs and Junctionless FETs), 3-D stacked Si/SiGe nanowire FETs, carbon nanotubes, and graphene are presented. From the view point of top-down and bottom-up approaches, the impacts of LF noise are investigated according to the dimensionality, conduction mechanism (surface or volume conduction), strain technique, and metal-semiconductor junctions.

Le principal objectif de ce travail est d’étudier les cellules solaires organiques de type hétérojonction en volume à l’aide d’un modèle bidimensionnel spécifique incluant un état intermédiaire pour la dissociation des charges dans les matériaux organiques. Ce modèle est mis en place dans un logiciel de simulation par éléments finis. Après validation, il est comparé à deux approches existant dans la littérature. Le grand nombre de paramètres requis pour décrire le mécanisme complexe de génération de charges nécessite un algorithme robuste, basé sur l’exploitation de chaînes de Markov, pour extraire ces paramètres physiques à partir de données expérimentales. Le modèle ainsi que la procédure d’extraction de paramètres sont utilisés dans un premier temps pour étudier le mécanisme de dissociation associé à une cellule comportant une nouvelle molécule. Ensuite le comportement en température de cellules à base de P3HT : PCBM est simulé et comparé à des mesures expérimentales. / The main objective of this work is to study bulk heterojunction organic solar cells with a specific two dimensional model that takes into account an intermediate state specific to organic materials. The model is solved numerically by a finite element software. After its validation, it is compared to two existing approaches in the literature. The large number of parameters needed to describe the complex charge generation mechanism requires a robust parameter extraction algorithm, based on the operation of Markov chains, in order to extract these physical parameters from experimental characterizations. The model and the parameter extraction method are then used to study the charge dissociation mechanism of a cell with a newly synthesized molecule. Finally, the temperature evolution of P3HT : PCBM solar cells are simulated and compared to experimental measurements.

No description available.