This diploma thesis concerns with analysis and dividing of frequency synthesizers and design of DDS, PLL synthesizers. Base types of frequency synthesizers are described including differences between methods of their operation. Base circuits of both – DDS and PLL synthesizers and other important circuits are described in details at design part of this thesis. Design of DDS and PLL synthesizer is described in particular sections. Both synthesizers are directly realized and stand-alone control applications are created. PLL synthesizer is also ready to control thru Agilent VEE program environment. Particular example application is designed in Agilent VEE. This application is used as basis of attached lab project.

Die Spezifikationen und Toleranzbereiche heutiger Hochgeschwindigkeitsdatenübertragungstechnologien nehmen immer weiter an Komplexität, aufgrund der steigenden Informationsmenge, zu. Zur Verarbeitung von Daten in Frequenzbereichen oberhalb von einem Gigahertz sind Referenzsignale notwendig, welche ein äußerst geringes Phasenrauschen aufweisen um benachbarte Kanäle nicht zu beeinflussen. Diese Referenzsignale werden in Mischerschaltungen zur Modulation oder Demodulation zwischen radio frequency (RF)- und intermediate frequency (IF)-Signalen verwendet. Die benötigte Signalform ist eine Sinusschwingung, die nicht durch digitale Schaltungsblöcke erzeugt werden kann. Daher ist die Notwendigkeit von analogen LC-Oszillatoren gegeben. Die Erzeugung von höchst stabilen und hochfrequenten Signalen war lange Zeit teuren Silizium-Germanium-Technologien vorbehalten. Jedoch erfordert der steigende Integrationsgrad und der hart umkämpfte Markt, die Entwicklung von RF-Schaltungen in günstigen CMOS-Technologien. In Zusammenarbeit mit der Landshut Silicon Foundry soll dazu eine monolithisch integrierte Phase-Locked Loop (PLL) mit einer mittleren Ausgangsfrequenz von 2,44 GHz und einem Phasenrauschen kleiner -115 dBc/Hz bei einem Abstand von 1 MHz vom Träger entwickelt werden. Dabei wird das Hauptaugenmerk auf den Kern der PLL gelegt, welcher einen spannungsgesteuerten Oszillator, einen Phasen-/Frequenzdetektor, eine Ladungspumpe, einen Schleifenfilter und einen Frequenzteiler beinhaltet. Außerdem sollen Testszenarien vorgestellt werden, um die Eigenschaften der gefertigten PLL zu bestimmen und zu vergleichen.

Les circuits de récupération d'horloge et de données sont nécessaires au bon fonctionnement de plusieurs systèmes de communication sans fil. Les travaux effectués dans le cadre de cette thèse concernent le développement de ces circuits avec d'une part la réalisation, en technologie HCMOS9 0,13 μm de STMICROELECTRONICS, de circuits CDR analogiques à 1 et 54 Mbit/s, et d'autre part, la mise en œuvre de fonctions CDR numériques programmables à bas débit. Un circuit CDR fonctionnant à plus bas débit (1 Mbit/s) a été conçu dans le cadre de la gestion d'énergie d'un récepteur ULB impulsionnel non cohérent. Ces deux structures ont été réalisées à l'aide de PLL analogiques du 3ème ordre. Un comparateur de phase adapté aux impulsions issues du détecteur d'énergie a été proposé dans cette étude. Les circuits ont ensuite été dimensionnés dans le but d'obtenir de très bonnes performances en termes de jitter et de consommation. En particulier, les performances mesurées (sous pointes) du circuit CDR à 1 Mbit/s permettent d'envisager une gestion d'énergie efficace (réduction de plus de 97% de la consommation du récepteur). Dans le cadre d'une chaîne de télémesure avion vers sol, deux circuits CDR numériques ont également été réalisés durant cette thèse. Une PLL numérique du second degré a été implémentée en vue de fournir des données et une horloge synchrone de celles-ci afin de piloter une chaîne SOQPSK entièrement numérique. Un circuit ELGS a également mis au point pour fonctionner au sein d'un récepteur PCM/FM. / Clock and data recovery circuits are required in many wireless communication systems. This thesis is about development of such circuits with: firstly, the realization, in HCMOS9 0.13 μm of STMICROELECTRONICS technology, of 1 and 54 Mb/s analog CDR circuits, and secondly, the implementation of programmable digital circuits at low rates. In the aim of an impulse UWB transceiver dealing with video transmission, a CDR circuit at 54 Mb/s rate has been realized to provide clock signal synchronously with narrow pulses (their duration is about a few nanoseconds) from the energy detector. Another CDR circuit has been built at 1 Mb/s rate in a non-coherent IR- UWB receiver power management context. Both circuits have been implemented as 3rd order analog PLL. In this work, a phase comparator suitable for “RZ low duty cycle” data from the energy detector has been proposed. Circuits have been sized to obtain very good performances in terms of jitter and power consumption. Particularly, measured performances of the 1 Mb/s CDR circuit allow to plan an efficient power management (a decrease of more than 97% of the receiver total power consumption). In the context of a telemetry system from aircraft to ground, two digital CDR circuits have also been implemented. A second order digital PLL has been adopted in order to provide synchronous clock and data to an SOQPSK digital transmitter. Also, a digital ELGS circuit has been proposed to work in a PCM/FM receiver. For both CDR structures, the input signal rate is programmable and varies globally from 1 to 30 Mb/s.

This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use of a low multiplication factor of 4 and a fully differential topology for rejection of common mode interference signals. The PLL is composed of a voltage controlled oscillator (VCO), injection-locked frequency divider (ILFD) for the first divide-by-two stage, a static master-slave flip-flop (MSFF) divider for the second divide-by-two stage and a Gilbert cell mixer phase detector (PD). The circuit has been fabricated using a standard CMOS 0.18-um process based on its relatively low cost and ready availability. The PLL frequency multiplier generates an output signal at 26 GHz and is the highest operational frequency PLL in the technology node reported to date. Time domain phase plane analysis is used for prediction of PLL locking range based on initial conditions of phase and frequency offsets. Tracking range of the PLL is limited by the inherent narrow locking range of the ILFD, and is confirmed via experimental results. The performance benefits of the fully differential PLL are experimentally confirmed by the injection of differential- and common-mode interfering signals at the VCO control lines. A comparison of the common- and differential-mode modulation indices reveals that a common mode rejection ratio (CMRR) of greater than 20 dB is possible for carrier offset frequencies of less than 1 MHz. Closed-loop frequency domain transfer functions are used for prediction of the PLL phase noise response, with the PLL being dominated by the reference and VCO phase noise contributions. Regions of dominant phase noise contributions are presented and correlated to the overall PLL phase noise performance. Experimental verifications display good agreement and confirm the usefulness of the techniques for PLL performance prediction. The PLL clock multiplier has an operational output frequency of 26.204 to 26.796 GHz and a maximum output frequency step of 16 MHz. Measured phase noise at 1 MHz offset from the carrier is -103.9 dBc/Hz. The PLL clock multiplier core circuit (VCO/ILFD/MSFF Divider/PD) consumes 186 mW of combined power from 2.8 and 4.3 V DC rails. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-04-24 11:31:35.384

The intentions of the so-called "More Electrical Aircraft" (MEA) are higher efficiency and lower weight. A main topic here is the application of electrical instead of hydraulical, pneumatical and mechanical systems. The necessary power electronic devices have intermediate DC-links, which are typically supplied by a three-phase system with active B6 and passive B12 rectifiers. A possible alternative is the B6 diode bridge in combination with an active power filter (APF). Due to the parallel arrangement, the APF offers a higher power density and is able to compensate for harmonics from several devices. The use of the diode bridge rectifier alone is not permitted due to the highly distorted phase current. The following investigations are dealing with the development of an active power filter for a three-phase supply with variable frequency from 360 to 800 Hz. All relevant components such as inductors, EMC-filters, power modules and DC-link capacitor are designed. A particular focus is put on the customized power module with SiC-MOSFETs and SiC-diodes, which is characterized electrically and thermally. The maximum supply frequency slope has a value of 50 Hz/ms, which requires a high dynamic and robustness on the control algorithm. Furthermore, the content of 5th and 7th harmonics must be reduced to less than 2 %, which demands a high accuracy. To cope with both requirements, a two-stage filter algorithm is developed and implemented in two independent signal processors. Simulations and laboratory experiments confirm the performance and robustness of the control algorithm. This work comprehensively presents the design of aerospace rectifiers. The results were published in conferences and patents. / Hauptziele des sogenannten "More Electrical Aircraft" (MEA) sind Effizienzerhöhung und Gewichtseinsparung. Ein Schwerpunkt hierbei ist die Nutzung von elektrischen statt hydraulischen, pneumatischen und mechanischen Systemen. Die notwendigen Leistungselektroniken haben DC-Zwischenkreise, welche mittels aktiven B6 und passiven B12 Gleichrichtern aus dem Dreiphasennetz gespeist werden. Eine mögliche Alternative ist die B6 Diodenbrücke in Kombination mit einem aktiven Netzfilter, welcher aufgrund der parallelen Anordnung eine höhere Leistungsdichte aufweist und darüber hinaus mehrere Geräte gleichzeitig entstören kann. Die alleinige Nutzung einer Diodenbrücke ist aufgrund des hohen Anteils von Stromharmonischen nicht zulässig. Diese Arbeit beschäftigt sich mit der Entwicklung eines aktiven Filters für ein Dreiphasensystem mit variabler Frequenz von 360 bis 800 Hz. Es werden alle relevanten Bauteile wie Induktivitäten, EMV-Filter, Leistungsmodule und Zwischenkreiskondensator ausgelegt. Besonderes Augenmerk liegt auf dem kundenspezifischen Modul mit SiC-Dioden und SiCMOSFETs, welches vollständig elektrisch und thermisch charakterisiert wird. Die Änderung der Netzfrequenz beträgt bis zu 50 Hz/ms, was eine hohe Dynamik und Robustheit von der Filterregelung verlangt. Weiterhin ist im statischen Fall eine hohe Genauigkeit gefordert, da die 5. und 7. Harmonische auf unter 2% geregelt werden müssen. Um beiden Anforderungen gerecht zu werden, wird ein zweistufiger Regelungsalgorithmus entwickelt der auf zwei digitalen Signalprozessoren implementiert wird. Simulationen und Labormessungen bestätigen die Robustheit des Regelungskonzeptes. Diese Arbeit stellt umfassend die Entwicklung von Luftfahrtgleichrichtern dar. Die Ergebnisse wurden in Konferenzen und Patenten veröffentlicht.

The necessity to incorporate renewable energy systems into existing electric power grid and need of efficient utilization of electrical energy are growing every day. A shunt connected Voltage Source Inverter(VSI) capable of bidirectional power flow and fast control has become one of the building block to address such requirements. However with growing number of grid connected VSI, new requirements related to harmonic injection, higher overall efficiency and better performances during short term grid disturbances have emerged as challenges. For this purpose a grid connected three phase four wire VSI with LCL filter can be considered as a general module to study different control approaches and system behavior under ideal and non-ideal grid conditions. This work focuses on achieving enhanced performance by analyzing effect of non-ideal conditions on system level and relating it to individual control blocks. In this work a phase locked loop structure has been proposed which is capable of extracting positive sequence fundamental phase information under non-ideal grid conditions. It can also be used in a single phase system without any structural modification. The current control for the three phase four wire VSI system has been implemented using Proportional Resonant (PR) controller in a per phase basis in stationary reference frame. A simplified controller design procedure based on asymptotic representation of the system transfer function is proposed. Using this method expressions for controller gains can be derived. A common mode model of the inverter system has been derived for low frequencies. Using this model a controller is designed to mitigate DC bus imbalance caused by sensor and ADC channel offsets. A multi-rate approach for digital implementation of PR controller with low resource consumption, that is suitable for an FPGA like digital controller ,is proposed. This multi-rate method can maintain resonance frequency accuracy even at low sampling frequency and can easily be frequency adaptive. Anti-wind up methods for PI controller have been studied to find suitable anti-wind up methods for PR controller. The tracking anti-wind up method is shown to be suitable for use with a PR controller. The effectiveness of this method under sudden disconnection and reconnection of VSI from grid is experimentally verified. A resonant integrator based second order filter is shown to be useful for active damping of LCL filter resonance with a wide range of grid inductance variation. The proposed method utilizes the LCL filter capacitor voltage to estimate resonance frequency current. Suitability of fundamental current PR controller for active damping alone, and with the proposed method show the superiority of the proposed method especially for low switching frequencies. Design oriented analysis of the above topics are included in the thesis. The theoretical understandings developed have been verified through experiments in the laboratory and can be readily implemented in industrial power electronic systems.

Je rapporte dans ce manuscrit une étude théorique et expérimentale d’une source compacte, fiable et bas coût d’ondes électromagnétiques continues et cohérentes de 30 Hz de largeur de raie, accordables de 1 GHz à 500 GHz par pas de 1 GHz. Ces ondes sont générées par un photo-mélange de deux diodes lasers DFB (Distributed Feedback) très accordables autour de 1550 nm, stabilisées avec des polarisations orthogonales sur une même cavité Fabry-Perot optique fibrée. J’ai conçue des électroniques de correction très rapides pour chaque laser permettant d’avoir une bande passante d’asservissement de 7 MHz limitée par la longueur de la boucle. Je démontre des suppressions de bruit de phase jusqu’à -60 dBc/ Hz à 1 kHz et de -90 dBc/Hz à 100 kHz d’écart d’une porteuse électrique à 92 GHz. Je mesure aussi une dérive de fréquence de ~170 kHz d’un battement à 10 GHz à long terme sur 7,5 heures de verrouillage continu. Je montre une conception optimisée d’une boucle d’asservissement intégrée de quelques dizaines de cm de longueur qui réduit le bruit de phase de 18 dB à 1 MHz d’écart à la porteuse optique et des couplages phase-amplitude réduits dans la cavité d’un facteur 50 par rapport à ceux estimés expérimentalement. L’ajout d’un troisième laser DFB stabilisé en phase sur un oscillateur local permettrait d’avoir une source continûment accordable sur 1 THz. La source d’ondes continues permettrait également de générer à partir de fibres hautement non linéaires et dispersives des impulsions pico- ou femtosecondes à un taux de répétition fixe en remplacement les lasers DFB par des lasers plus stables. Je calcule par simulation une gigue temporelle de 7,2 fs sur un temps d’intégration de 1 ms à 40 GHz de taux de répétition. / I report in this manuscript a theoretical and experimental study of a compact, reliable and low cost source of 30 Hz linewidth, continuous and coherent electromagnetic waves tunable from 1 GHz to 500 GHz in steps of 1 GHz. These waves are generated by photomixing two distributed feedback (DFB) laser diodes at 1550 nm which are frequency stabilized with orthogonal polarizations on the same optical fibered Fabry-Perot cavity. I have designed very fast electronic control filters for each laser allowing a 7 MHz servo bandwidth limited by the loop length. I demonstrate phase noise suppressions down to -60 dBc/Hz at 1 kHz and -90 dBc/Hz at 100 kHz offset frequencies from a 92 GHz electrical carrier. I also measure a ~170 kHz frequency drift of the beat note at 10 GHz on the long term over a continuous 7.5 hour locking period. I show an optimized design of an integrated servo loop of few tens of cm length which reduces the phase noise by 18 dB at 1 MHz optical carrier offset frequency and the phase-amplitude couplings in the cavity by a factor of 50 compared to the experimental one. The addition of a third DFB laser phase stabilized on a local oscillator allows the possibility to have continuously tunable source over 1 THz. The continuous wave source also makes it possible to generate fixed repetition rate pico- or femtosecond pulses from highly non-linear and dispersive fibers, replacing the DFB lasers by further stable lasers. I have calculated by simulation 7.2 fs temporal jitter at 40 GHz repetition rate over a 1 ms integration time.

Die mikromechanische Gleichspannungswandlung basierend auf verschiebungsabhängigen Kapazitäten stellt eine Alternative zu etablierten rein elektronischen Wandlern für den Spezialfall der kapazitiven oder piezoelektrischen Verbraucher dar. Durch ihre kleine Bauform und den Verzicht auf Induktivitäten bietet sie den Vorteil der On-Chip-MEMS- und CMOS-Integration und ermöglicht die Bereitstellung hoher elektrischer Gleichspannungen aus den verfügbaren Grundspannungen der Elektronik (z. B. 3, 5 bzw. 12 V). Von hohen Polarisationsspannungen profitieren nicht nur kapazitive Sensoren und Aktoren, sondern auch piezoelektrische Messverfahren. Diese Arbeit stellt eine umfangreiche Übersicht und Bewertung der möglichen Bauformen mikromechanischer Gleichspannungswandler sowie die konkrete Umsetzung, Charakterisierung und Modellbildung eines resonant arbeitenden Wandlers vor. Es wird auf Besonderheiten und Probleme im Entwurf eingegangen und ausgehend von den Ergebnissen ein Konzeptentwurf für einen optimierten resonanten Gleichspannungswandler erarbeitet.:1 Einleitung 2 Theoretische Grundlagen 3 Ausführungsvarianten von MEMS-DC/DC-Wandlern 4 Designstudie und Umsetzung des resonanten Funktionsprinzips 5 Zusammenfassung und Ausblick / Micromechanical DC/DC conversion based on variable capacitances is an alternative to established electronic voltage converters, which does not require bulky inductors and is suitable for capacitive and piezoelectric loads. The converters are capable of boosting up the polarization voltage from CMOS and electronic levels (3, 5, 12 V), which is beneficial not only for capacitive sensors and actuators but also for piezoelectric sensing. Advantages of this method are the on-chip- and CMOS-integrability. This thesis introduces a comprehensive overview and evaluation of possible designs as well as the practical application, characterization and modeling of a resonant micromechanical DC/DC converter. Innovative claims include a test board for the characterization of resonant DC/DC converters and a SPICE behavioral model of the device, considering parasitic effects. Characteristics and problems of the design are discussed and the results are used to demonstrate an optimized conceptual design of a resonant DC/DC converter.:1 Einleitung 2 Theoretische Grundlagen 3 Ausführungsvarianten von MEMS-DC/DC-Wandlern 4 Designstudie und Umsetzung des resonanten Funktionsprinzips 5 Zusammenfassung und Ausblick

The main aim of the thesis is to develop a solution of a frequency synthesizer for a microwave communication systems. Specifically, it suggests a design for frequency synthesizer with phase-locked loop. At beginning of the thesis the principle and basic properties of this method of signal generation are explained. Then it is followed by a brief discussion of the parameters of synthesizers and their influence on design. Another part of the work is the analysis of circuit the frequency synthesizer with the phase-locked loop MAX2871, which is followed by a proposal for the design of the frequency synthesizer module hardware. The last part of the work deals with practical implementation, verification of function and measurement of achieved parameters and their evaluation.

The presented thesis deals with the design and assembly of the generator for pulse magnetron sputtering. The designed device is capable of generating two square wave signals via its counter-working outputs. Both signals have independently adjustable frequency, pulse count and duty ratio. Both signals originate from two frequency syntheses controlled by microcontroller PIC16F877A. All the settings are entered by four buttons and are shown on an alphanumeric display with 16x4 characters. The duty ratio is adjusted using a special module.