Extremsökande reglering (ESC) är en modellfri adaptiv reglermetod som kan användas för att lokalisera den optimala arbetspunkten i olinjära processer. Det har nyligen visats att det finns problem med traditionell ESC om det reglerade systemet är dynamiskt. I den här avhandlingen behandlar vi en ny metod för extremsökande reglering som är applicerbar för både statiska och dynamiska system. Metoden är baserad på att reglera processens arbetspunkt tills det lokala fasskiftet hos processen når ⇡/2. Resultatet är baserat på det faktum att fasskiftet hos processer generellt förändras kraftigt kring optimum, och för låga frekvenser motsvarar optimum ett fasskift på ⇡/2radianer. Regulatorstrukturen som används liknar en faslåst slinga (PLL). Ett olinjärt Kalmanfilter används för att estimera fasen och en integrerande regulator används för att justera arbetspunkten tills fasen når det önskade fasskiftet. Resultaten är illustrerade i ett exempel där den nya regulatorstrukturen används för att optimera produktionen i en kemisk reaktor. / Extremum Seeking Control (ESC) is a model-free adaptive control method to locate and track the optimal working point for nonlinear plants. However, as shown recently, traditional ESC methods may not work well for dynamic systems. In this thesis, we consider a novel ESC loop to locate the optimal operating point for both static and dynamic systems. Considering that the phase-lag of the system undergoes a large shift near a steady-state optimum and reaches the value of ⇡/2attheoptimaloperatingpoint, thenovelESC applies the phase-lag of the target system to track the optimum. An ex-tended Kalman filter is used to ensure the accuracy of the phase estimation. The structure of a phase locked loop (PLL) is employed in combination with an integral controller to lock the phase near ⇡/2, such that the target system will operate near the optimal working point. The controller is demonstrated by application to optimization of the substrate conversion in a chemical re-actor.

Cette distinction est également valable pour le genre des individus (homme/femme). L'étude menée a montré que l'approche utilisant l'information spectrale des contours des phalanges permet une identification par seulement trois phalanges, à un taux EER (Equal Error Rate) inférieur à 0.24 %. Par ailleurs, il a été constaté « de manière surprenante » que la technique fondée sur les rapports de vraisemblance entre les phalanges permet d'atteindre un taux d'identification de 100 % et un taux d'EER de 0.37 %, avec une seule phalange. Hormis l'aspect identification/authentification, notre étude s'est penchée sur l'optimisation de la dose de rayonnement permettant une identification saine des individus. Ainsi, il a été démontré qu'il était possible d'acquérir plus de 12500/an d'images radiographiques de la main, sans pour autant dépasser le seuil administratif de 0.25 mSvL'avancement de la communication numérique optique dans les réseaux longue distance et d'accès a déclenché les technologies émergentes dans le domaine micro-ondes / ondes millimétriques. Ces systèmes hybrides sont fortement influencés non seulement par les déficiences de liens optiques mais aussi des effets de circuits électriques. Les effets optiques et électriques peuvent être ainsi étudiés en même temps en utilisant des outils assistés par ordinateur en développant des modèles de circuit équivalent de l'ensemble des composants de liaison tels que les lasers à semi-conducteurs, modulateurs, photo-détecteurs et fibre optique. Dans cette thèse, les représentations de circuit des composants de liaison photoniques sont développées pour étudier des architectures différentes. Depuis la source de lumière optique est le principal facteur limitant de la liaison optique, une attention particulière est accordée aux caractéristiques, y compris les plus importants de simples lasers en mode semi-conducteurs. Le modèle de circuit équivalent de laser qui représente l'enveloppe du signal optique est modifié pour inclure les propriétés de bruit de phase du laser. Cette modification est particulièrement nécessaire d'étudier les systèmes où le bruit de phase optique est important. Ces systèmes comprennent des systèmes de télécommande hétérodynes optiques et des systèmes auto-hétérodynes optiques. Les résultats de mesure des caractéristiques de laser sont comparés aux résultats de simulation afin de valider le modèle de circuit équivalent dans des conditions différentes. Il est démontré que le modèle de circuit équivalent peut prédire avec précision les comportements des composants pour les simulations au niveau du système. Pour démontrer la capacité du modèle de circuit équivalent de la liaison photonique pour analyser les systèmes micro-ondes / ondes millimétriques, le nouveau modèle de circuit du laser avec les modèles comportementaux des autres composants sont utilisés pour caractériser différents radio sur fibre (RoF) liens tels que la modulation d'intensité - détection directe (IM-DD) et les systèmes RoF hétérodynes optique. Signal sans fil avec des spécifications conformes à la norme de IEEE 802.15.3c pour la bande de fréquence à ondes millimétriques est transmis sur les liens RoF. La performance du système est analysée sur la base de l'évaluation de l'EVM. L'analyse montre que l'analyse efficace des systèmes de photonique micro-ondes / ondes millimétriques est obtenue en utilisant des modèles de circuit qui nous permet de prendre en compte les comportements à la fois électriques et optiques en même temps / The advancement of digital optical communication in the long-haul and access networks has triggered emerging technologies in the microwave/millimeter-wave domain. These hybrid systems are highly influenced not only by the optical link impairments but also electrical circuit effects. The optical and electrical effects can be well studied at the same time using computer aided tools by developing equivalent circuit models of the whole link components such as semiconductor lasers, modulators, photo detectors and optical fiber. In this thesis, circuit representations of the photonic link components are developed to study different architectures. Since the optical light source is the main limiting factor of the optical link, particular attention is given to including the most important characteristics of single mode semiconductor lasers. The laser equivalent circuit model which represents the envelope of the optical signal is modified to include the laser phase noise properties. This modification is particularly necessary to study systems where the optical phase noise is important. Such systems include optical remote heterodyne systems and optical self-heterodyne systems. Measurement results of the laser characteristics are compared with simulation results in order to validate the equivalent circuit model under different conditions. It is shown that the equivalent circuit model can precisely predict the component behaviors for system level simulations. To demonstrate the capability of the equivalent circuit model of the photonic link to analyze microwave/millimeter-wave systems, the new circuit model of the laser along with the behavioral models of other components are used to characterize different radio-over-fiber (RoF) links such as intensity modulation – direct detection (IM-DD) and optical heterodyne RoF systems. Wireless signal with specifications complying with IEEE 802.15.3c standard for the millimeter-wave frequency band is transmitted over the RoF links. The system performance is analyzed based on EVM evaluation. The analysis shows that effective analysis of microwave/millimeter-wave photonics systems is achieved by using circuit models which allows us to take into account both electrical and optical behaviors at the same time

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / In this paper design and development of a PC- Based S- Band Down Converter/ FM Telemetry Receiver are discussed. With the advent of Direct Digital Synthesis (DDS) & Phase Locked Loop (PLL) technology, availability of GaAs & Silicon MMICs, Coaxial Resonator Oscillator (CRO), SAW Oscillator, SAW Filters and Ceramic Filters, realisation of single card PC- Based Down Converter and Telemetry Receiver has become a reality. With the availability of Direct Digital Synthesis and Phase Locked Loop devices having microprocessor bus compatibility, opens up many application in Telemetry and Telecommunications. In this paper design of local oscillator based on hybrid DDS & PLL technique, Coaxial Resonator Oscillator and Front-end are discussed in detail.

International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / Presentation of Alcatel Espace last studies and developments regarding TT&C receiver Products for satellite. This document lays on 3 parts: · a technical point of view showing digital demodulation principles used (base band recovery, analytical head, PM or FM demodulation) and their related offered possibilities(digital controlling loop, lock status detection, jammer detection,....) · a technology/design description · a synthesis showing performance and results

The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator is designed to extract the subtle response from the system so that target parameters can be predicted. Different testing methodologies are applied different specification testing as well. Finally, an on chip phase-locked loop design is implemented for reference spur calibration. The phase-locked loop is designed with a programmable reference spur range. A static phase offset detector is included to identify the optimal setting of reference spur in the feedback system. The integrated jitter performance is improved by the calibration mechanism. The results of this thesis serve as an on-chip built-in self-test and self-calibration solution for embedded phase-locked loops in a high integration system.

Cette thèse porte sur les aspects de conception d'un synthétiseur de fréquence pour les émetteurs-récepteurs dans les architectures multi-radios cognitives. La largeur de bande couverte par ce synthétiseur multi-radio correspond à la bande de fréquences des normes de communication sans fil les plus diffusées, fonctionnant dans la bande de fréquence de 800 MHz à 6 GHz. Du fait que l'opération multi-standard est indispensable, le synthétiseur doit répondre aux exigences les plus strictes et parfois contradictoires. Compte tenu de ces exigences, une nouvelle approche pour une synthèse de fréquence multi-mode a été conçue. Un synthétiseur de fréquence hybride, basé sur le principe de la boucle à verrouillage de phase a été proposé et un nouveau protocole de commutation a été présenté et validé sur une carte d'évaluation expérimentale. Cette approche combine les modes fractionnel et entier avec une topologie de filtre à bande commuté. Par rapport aux techniques standard, la configuration hybride permet une grande souplesse en matière de reconfiguration et d'ailleurs, elle offre une complexité des circuits relativement faible ainsi qu'une faible consommation électrique. Cette architecture assure la reconfiguration de la bande passante de la boucle ainsi que la résolution, le niveau du bruit de phase et du temps d'accrochage et, par conséquent, elle peut s'adapter à des besoins divers, imposés par les normes concernées. Des analyses correspondantes, des simulations et des mesures ont été réalisées afin de vérifier les performances et les fonctionnalités de la solution proposée. A part la conception du synthétiseur de fréquence multi-radio, une campagne de mesures régionales de l'utilisation du spectre radio a été réalisée dans le cadre de la recherche de cette thèse. Ces mesures sont fondées sur le principe de détection de l'énergie et nous démontrent le degré d'utilisation du spectre radio dans les différentes régions, notamment dans la ville de Brno en République Tchèque et dans la ville de Paris et sa banlieue en France. L'objectif de cette campagne de mesures expérimentales a été d'estimer le degré d'utilisation du spectre radio dans des environnements différents et de souligner le fait qu'une nouvelle approche pour la gestion du spectre radio est inévitable / This doctoral thesis deals with design aspects of a reconfigurable frequency synthesizer for flexible radio transceivers in future cognitive multi-radios. The frequency bandwidth to be covered by this multi-radio synthesizer corresponds to the frequency bands of the most diffused wireless communication standards in the frequency band 800 MHz to 6 GHz. Since multi-standard operation is required, the synthesizer must fulfil the most stringent and sometimes conflicting requirements. Given these requirements, a novel approach for multi-mode frequency synthesis has been conceived. A hybrid phase locked loop based frequency synthesizer has been proposed and a novel switching protocol has been presented and validated on an experimental evaluation board. This approach combines fractional-N and integer-N modes of operation with switched loop filter topology. Compared to standard PLL techniques, the hybrid configuration provides a great flexibility in terms of reconfiguration and moreover, it offers relatively low circuit complexity and low power consumption. This architecture provides reconfiguration of the loop bandwidth, frequency resolution, phase noise and settling time performance and hence, it can adapt itself to diverse requirements given by the concerned wireless communication standards. Corresponding analyses, simulations and measurements have been carried out in order to verify the performance and functionality of the proposed solution. A part from the design of the multiband frequency synthesizer, a set of regional measurements of the radio spectrum utilization has been carried out in the framework of this dissertation research. These measurements are based on the energy detection principle and provide a close look at the degree of radio spectrum utilization in different regions, namely in the city of Brno in the Czech Republic and in the city of Paris and one of its suburbs in France. The goal of the experimental measurement campaign has been to estimate the degree of radio spectrum usage in a particular environment and to point out the fact that a new approach for radio spectrum management is inevitable

The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power consumption. Clock generators are essential components in numerous circuits, for instance, frequency synthesizers for high speed transceivers, clock sources for microprocessors, noise suppressed zero-delay buffers in system-on-chips (SOCs), and clock and data recovery (CDR) systems. Furthermore, clock generators are required to provide low jitter and high precision clocks in fully integrated image reject receivers and an ultra-wide tunability in time-interleaved applications. We explore several circuit design techniques and implementations of low jitter clock generator in this thesis. Firstly, a low jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated using a dual path digital loop filter (DLF). In order to mitigate the phase jitter in the phase detector (PD), we implement the separate loop filter and the output is not affected by the proportional path. For the stable operation, a 4 ~ 8 GHz linear phase interpolator (PI) is implemented in the proportional path. In addition, we design a low phase noise digitally controlled oscillator (DCO) using inductive tuning technique based on switched mutual coupling for wide operating range. The proposed DPLL implemented in 65 nm CMOS technology shows an outstanding figure-of-merit (FOM) over other state-of-art DPLLs in term of root mean square (RMS) and deterministic jitter (DJ). Secondly, we discuss a radiation-hardened-by-design (RHBD) PLL using a feedback voltage-controlled oscillator (FBVCO) in order to reduce DJ due to the radiation attack on the control voltage. Different from a conventional open loop VCO, the proposed FBVCO has a negative control loop and is composed of an open loop VCO, an integrator and a switched-capacitor resistor. Since the input to output of the FBVCO has a low-pass characteristic, any disturbance on the control voltage should be filtered and cannot affect the output phase. We are able to reduce the output frequency variation approximately 75% compared to the conventional PLL when the radiation pulse strikes on the control voltage. The proposed RHBD PLL is implemented in 130 nm and consumes 6.2 mW at 400 MHz operating frequency. Thirdly, a novel adaptive-bandwidth PLL is illustrated to optimize the jitter performance in a wide operating frequency range. We achieve a constant ratio of bandwidth and reference frequency with a closed loop VCO and an overdamping system with a charge pump (CP) current proportional to the VCO frequency for the adaptive-bandwidth technique. The proposed adaptive-bandwidth PLL presents 0.6% RMS jitter over the entire frequency range from 320 MHz to 2.56 GHz, which is 70% smaller than the conventional fixed-bandwidth PLL. Finally, we have developed a new feedback DCO to achieve a linear gain of DCO so that the DPLL can provide stability and a wide operating range in different process variations. Due to the negative feedback loop of the proposed DCO, the feedback DCO presents a linear gain from an input digital word to an output frequency. Moreover, we can control the bandwidth of the feedback DCO to optimize the total output phase noise in DPLL. In simulation, we can obtain 17 MHz/LSB of the peak-to-peak gain of the feedback DCO, which is reduced 96% over the conventional DCO.

Ionospheric scintillation is a phenomenon caused by varying concentrations of charged particles in the upper atmosphere that induces deep fades and rapid phase rotations in satellite signals, including GPS. During periods of scintillation, carrier tracking loops often lose lock on the signal because the rapid phase rotations generate cycle slips in the PLL. One solution to mitigating this problem is by employing decision-directed carrier recovery algorithms that achieve data wipe-off using differential bit detection techniques. Other techniques involve PLLs with variable bandwidth and variable integration times. Since nearly 60% of the GPS signal repeats between frames, this thesis explores PLLs utilizing variable integration times and decision-directed algorithms that exploit the repeating data as a training sequence to aid in phase error estimation. Experiments conducted using a GPS signal generator, software radio, and MATLAB scintillation testbed compare the bit error rate of each of the receiver models. Training-based methods utilizing variable integration times show significant reductions in the likelihood of total loss of lock.

Variations in ionospheric plasma density can cause large amplitude and phase changes in the radio waves passing through this region. Ionospheric weather can have detrimental effects on several communication systems, including radars, navigation systems such as the Global Positioning Sytem (GPS), and high-frequency communications. As a result, creating models of the ionospheric density is of paramount interest to scientists working in the field of satellite communication. Numerous empirical and theoretical models have been developed to study the upper atmosphere climatology and weather. Multiple measurements of plasma density over a region are of marked importance while creating these models. The lack of spatially distributed observations in the upper atmosphere is currently a major limitation in space weather research. A constellation of CubeSat platforms would be ideal to take such distributed measurements. The use of miniaturized instruments that can be accommodated on small satellites, such as CubeSats, would be key to acheiving these science goals for space weather. The accepted instrumentation techniques for measuring the electron density are the Langmuir probes and the Plasma Impedance Probe (PIP). While Langmuir probes are able to provide higher resolution measurements of relative electron density, the Plasma Impedance Probes provide absolute electron density measurements irrespective of spacecraft charging. The central goal of this dissertation is to develop an integrated architecture for the PIP that will enable space weather research from CubeSat platforms. The proposed PIP chip integrates all of the major analog and mixed-signal components needed to perform swept-frequency impedance measurements. The design's primary innovation is the integration of matched Analog-to-Digital Converters (ADC) on a single chip for sampling the probes current and voltage signals. A Fast Fourier Transform (FFT) is performed by an off-chip Field-Programmable Gate Array (FPGA) to compute the probes impedance. This provides a robust solution for determining the plasma impedance accurately. The major analog errors and parametric variations affecting the PIP instrument and its effect on the accuracy and precision of the impedance measurement are also studied. The system clock is optimized in order to have a high performance ADC. In this research, an alternative clock generation scheme using C-elements is described to reduce the timing jitter and reference spurs in phase locked loops. While the jitter performance and reference spur reduction is comparable with prior state-of-the-art work, the proposed Phase Locked Loop (PLL) consumes less power with smaller area than previous designs.

As demand for higher bandwidth I/O grows, the front end design of serial link becomes significant to overcome stringent timing requirements on noisy and bandwidthlimited channels. As a clock reconstructing module in a receiver, the recovered clock quality of Clock and Data Recovery is the main issue of the receiver performance. However, from unknown incoming jitter, it is difficult to optimize loop dynamics to minimize steady-state and dynamic jitter. In this thesis a 10 Gb/s adaptive loop bandwidth clock and data recovery circuit with on-chip loop filter is presented. The proposed system optimizes the loop bandwidth adaptively to minimize jitter so that it leads to an improved jitter tolerance performance. This architecture tunes the loop bandwidth by a factor of eight based on the phase information of incoming data. The resulting architecture performs as good as a maximum fixed loop bandwidth CDR while tracking high speed input jitter and as good as a minimum fixed bandwidth CDR while suppressing wide bandwidth steady-state jitter. By employing a mixed mode predictor, high updating rate loop bandwidth adaptation is achieved with low power consumption. Another relevant feature is that it integrates a typically large off-chip filter using a capacitance multiplication technique that employs dual charge pumps. The functionality of the proposed architecture has been verified through schematic and behavioral model simulations. In the simulation, the performance of jitter tolerance is confirmed that the proposed solution provides improved results and robustness to the variation of jitter profile. Its applicability to industrial standards is also verified by the jitter tolerance passing SONET OC-192 successfully.