A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.

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This thesis focuses on analyzing the synchronization of time delays between mutually coupled phase-locked loops (PLLs) in a flat hierarchy. Mutual synchronization refers to decentralized synchronization where there is no primary or secondary unit or control source. Consequently, it is an inherently self-organizing system in which each unit has equal rights, making it a democratic system. In this research, a dynamic nonlinear time-domain model is used to describe mutually delayed coupled oscillators. The predictions of this model are evaluated against experimental measurements. The time-domain model is based on the Kuramoto model. The Kuramoto model describes a network of coupled oscillators. As a first impression, this Kuramoto model is first analyzed for understanding of the effects of time delays between oscillators. The time domain model is based on a conventional PLL architecture modified to allow mutual coupling. The modifications include a circuit section that sums and weights all incoming phase differences. Overall, the measured results of this research study are in good agreement with the theoretical predictions of the time-domain model. The analysis allows the identification of the transient dynamics and the mechanisms that lead to mutual coupling and the formation of synchronized states through self-organized synchronization. The results show that the mutual coupling can self-organize its dynamics to synchronize even at time delays where the phenomenon of multistability of synchronized states occurs. A critical time delay beyond which a stable synchronized state cannot be achieved has been identified. The work also analyzes the dynamics and noise of synchronized states and finds that the dynamics near a synchronized state are correlated due to mutual coupling, leading to a reduction in noise. The noise correlation is affected by the direction of coupling, the number of nodes in the network, and the network topology. An improvement in phase noise of up to 14.42 dBc/Hz at 100 kHz offset from the carrier and 49.47ns delay was achieved using all-to-all coupling with four nodes. Furthermore, the hybrid approach, the combination of hierarchical and self-organizing synchronization architectures, is investigated. The dissertation presents an experimental study to understand how this affects a network of mutually delayed delay-coupled oscillators and whether the network of mutually coupled nodes can be abstracted as a secondary oscillator. A range in which the mutually delay-coupled network can be successfully synchronized by an external reference oscillator, depending on the synchronized state, is identified. In summary, this thesis provides valuable insights into the properties of mutually delay-coupled PLLs and their synchronization in flat hierarchies, and contributes to the understanding, design, and optimization of more practical networks of mutually delayed PLLs.:Abstract/Zusammenfassung Symbols and Abbreviations Previous Publications 1 Introduction 1.1 Classifications of Synchronization 1.2 A Historical Perspective on Mutual Synchronization 1.3 Extending the Understanding of Mutual Synchronization 1.4 Definitions and Methodologies 2 Model of Networks of Mutually Coupled PLLs 2.1 Coupled Oscillators – Kuramoto Model 2.1.1 Consequences of a Time Delay between Oscillators 2.1.2 Arbitrary Time Delays between Oscillators 2.2 Time-Domain Model of Delay-Coupled PLLs 2.2.1 Phase Detection 2.2.2 Loop-Filter 2.2.3 Voltage Controlled Oscillator 2.3 Prediction and Stability Analysis of Synchronized States 2.3.1 Assessing the Linear Stability of Synchronized States 2.3.2 Stability Consideration for Two Identical PLL Nodes 2.3.3 The Notion of Mode Locking 2.3.4 Effects of Heterogeneity on Synchronized States 2.4 Dynamics and Noise in Synchronized States 2.4.1 Gain and Phase Margin of a PLL Node 2.4.2 Phase Noise 2.5 Key Findings of the Theoretical Model 3 Design of Phase-Locked-Loops for Mutual Synchronization 3.1 PLL Nodes Dedicated for Mutual Synchronization 3.1.1 Phase Detection Circuitry 3.1.2 Adder Chain 3.2 Additional Circuitry for Implementing a Time Delay 4 Experimental Analysis of Mutually Time-Delayed Coupled PLLs 4.1 Synchronized States Including Oscillator Nonlinearity 4.2 Stability of Multistable Synchronized States 4.3 Critical Time Delay Between Two Coupled Nodes 4.4 Combining Hierarchical and Flat Synchronization Concepts 4.4.1 Entrainment of a Chain Network Topology 4.4.2 Entrainment of a Ring Network Topology 4.5 Heterogeneous Time Delays between Coupled PLLs 4.6 Phase Noise Analysis of Time Delay Coupled PLLs 4.6.1 Phase Noise for Two Mutually Coupled Nodes 4.6.2 The Impact of Coupling Directionality 4.6.3 Long Term Frequency Stability 4.6.4 Effect of Time Delay on Phase Noise 4.6.5 Network Topology Dependency on Phase Noise 5 Conclusion and Future Prospects Bibliography Own Publications – Periodicals Own Publications – Conference Proceedings Co-Authored Publications Other References List of Figures List of Tables Acknowledgement Curriculum Vitae / Diese Arbeit befasst sich mit der Analyse der Auswirkungen von Zeitverzögerungen auf die Synchronisation von gegenseitig gekoppelten Phasenregelschleifen (engl. phase-locked loop (PLL)) in einer flachen Hierarchie. Gegenseitige Synchronisation bezieht sich auf eine dezentrale Synchronisation, bei der es keine primäre oder sekundäre Einheit oder Steuerquelle gibt. Folglich ist es ein inhärent selbstorganisierendes System, in dem jede Einheit gleichberechtigt ist, was es zu einem demokratischen System macht. Für die Untersuchung wird ein dynamisches nichtlineares Zeitbereichsmodell verwendet, um gegenseitig verzögert gekoppelte Oszillatoren zu modellieren und die Vorhersagen dieses Modells anhand experimenteller Messungen zu bewerten. Dieses Zeitbereichsmodell basiert auf dem sogenannten Kuramoto-Modell, das ein Netzwerk gekoppelter Oszillatoren beschreibt. Um einen ersten Eindruck zu erhalten, wird zunächst dieses Kuramoto-Modell analysiert, um die Auswirkungen von Zeitverzögerungen zwischen den Oszillatoren zu verstehen. Das Zeitbereichsmodell basiert auf einer konventionellen PLL-Architektur, die modifiziert wurde, um eine gegenseitige Kopplung zu ermöglichen. Die Modifikationen beinhalten einen Schaltungsteil, der alle eingehenden Phasendifferenzen summiert und gewichtet. Die gemessenen Ergebnisse dieser Untersuchung stimmen insgesamt gut mit den theoretischen Vorhersagen des Zeitbereichsmodells überein. Die Analyse erlaubt es, die transiente Dynamik und die Mechanismen zu identifizieren, die zur gegenseitigen Synchronisation und zur Bildung synchronisierter Zustände durch selbstorganisierte Synchronisation führen. Die Ergebnisse zeigen, dass selbst bei Zeitverzögerungen, bei denen das Phänomen der Multistabilität synchronisierter Zustände auftritt, die gegenseitige Kopplung ihre Dynamik selbst organisieren kann, um sich zu synchronisieren. Die Untersuchung identifizierte eine kritische Zeitverzögerung, bei der kein stabiler synchronisierter Zustand erreicht werden kann. Die Arbeit analysiert auch die Dynamik und das Rauschen von synchronisierten Zuständen und stellt fest, dass die Dynamik in der Nähe eines synchronisierten Zustands aufgrund der gegenseitigen Kopplung korreliert ist, was zu einer Reduktion des Rauschens führt. Die Richtung der Kopplung und die Anzahl der Knoten im Netzwerk sowie die Netzwerktopologie beeinflussen die Korrelation des Rauschens. Eine Verbesserung des Phasenrauschens von bis zu 14.42 dBc/Hz bei einem Versatz von 100 kHz zum Träger und einer Verzögerung von 49.47 ns wurde durch eine globalen oder All-to-All-Kopplung mit vier Knoten erreicht. Des Weiteren wird der hybride Ansatz, die Kombination von hierarchischen und selbstorganisierenden Synchronisationsarchitekturen, untersucht. Die Arbeit präsentiert eine experimentelle Studie, um zu verstehen, wie dies ein Netzwerk von gegenseitig verzögert gekoppelten Oszillatoren beeinflusst und ob das Netzwerk von gegenseitig gekoppelten Knoten als sekundärer Oszillator abstrahiert werden kann. Dabei wird eine vom synchronisierten Zustand abhängige Domäne identifiziert, in der das wechselseitig gekoppelte Netzwerk durch einen externen Referenzoszillator erfolgreich synchronisiert werden kann. Insgesamt liefert diese wissenschaftliche Arbeit wertvolle Erkenntnisse über die Eigenschaften von gegenseitig verzögerungsgekoppelten PLLs und deren Synchronisation in einer flachen Hierarchie und trägt zum Verständnis, zum Entwurf und zur Optimierung von praktisch realisierten Netzwerken gegenseitig verzögerungsgekoppelter PLLs bei.:Abstract/Zusammenfassung Symbols and Abbreviations Previous Publications 1 Introduction 1.1 Classifications of Synchronization 1.2 A Historical Perspective on Mutual Synchronization 1.3 Extending the Understanding of Mutual Synchronization 1.4 Definitions and Methodologies 2 Model of Networks of Mutually Coupled PLLs 2.1 Coupled Oscillators – Kuramoto Model 2.1.1 Consequences of a Time Delay between Oscillators 2.1.2 Arbitrary Time Delays between Oscillators 2.2 Time-Domain Model of Delay-Coupled PLLs 2.2.1 Phase Detection 2.2.2 Loop-Filter 2.2.3 Voltage Controlled Oscillator 2.3 Prediction and Stability Analysis of Synchronized States 2.3.1 Assessing the Linear Stability of Synchronized States 2.3.2 Stability Consideration for Two Identical PLL Nodes 2.3.3 The Notion of Mode Locking 2.3.4 Effects of Heterogeneity on Synchronized States 2.4 Dynamics and Noise in Synchronized States 2.4.1 Gain and Phase Margin of a PLL Node 2.4.2 Phase Noise 2.5 Key Findings of the Theoretical Model 3 Design of Phase-Locked-Loops for Mutual Synchronization 3.1 PLL Nodes Dedicated for Mutual Synchronization 3.1.1 Phase Detection Circuitry 3.1.2 Adder Chain 3.2 Additional Circuitry for Implementing a Time Delay 4 Experimental Analysis of Mutually Time-Delayed Coupled PLLs 4.1 Synchronized States Including Oscillator Nonlinearity 4.2 Stability of Multistable Synchronized States 4.3 Critical Time Delay Between Two Coupled Nodes 4.4 Combining Hierarchical and Flat Synchronization Concepts 4.4.1 Entrainment of a Chain Network Topology 4.4.2 Entrainment of a Ring Network Topology 4.5 Heterogeneous Time Delays between Coupled PLLs 4.6 Phase Noise Analysis of Time Delay Coupled PLLs 4.6.1 Phase Noise for Two Mutually Coupled Nodes 4.6.2 The Impact of Coupling Directionality 4.6.3 Long Term Frequency Stability 4.6.4 Effect of Time Delay on Phase Noise 4.6.5 Network Topology Dependency on Phase Noise 5 Conclusion and Future Prospects Bibliography Own Publications – Periodicals Own Publications – Conference Proceedings Co-Authored Publications Other References List of Figures List of Tables Acknowledgement Curriculum Vitae

Un microscope à force atomique (AFM) est utilisé pour caractériser des matériaux isolant ou semi-conducteur avec une résolution pouvant atteindre l'échelle atomique. Ce microscope est constitué d'un capteur de force couplé à une électronique de contrôle pour pouvoir correctement caractériser ces matériaux. Parmi les différents modes (statique et dynamique), nous nous focalisons essentiellement sur le mode dynamique et plus particulièrement sur le fonctionnement sans contact à modulation de fréquence (FM-AFM). Dans ce mode, le capteur de force est maintenu comme un oscillateur harmonique par le système d'asservissement. Le projet ANR Pnano2008 intitulé : ”Cantilevers en carbure de silicium à piézorésistivité métallique pour AFM dynamique à très haute fréquence" a pour objectif d'augmenter significativement les performances d'un FM-AFM en développant un nouveau capteur de force très haute fréquence. Le but est d'augmenter la sensibilité du capteur et de diminuer le temps nécessaire à l'obtention d'une image de la surface du matériau. Le système de contrôle associé doit être capable de détecter des variations de fréquence de 100mHz pour une fréquence de résonance de 50MHz. Etant donné que les systèmes présents dans l'état de l'art ne permettent pas d'atteindre ces performances, l'objectif de cette thèse fut de développer un nouveau système de contrôle. Celui-ci est entièrement numérique et il est implémenté sur une carte de prototypage basée sur un FPGA. Dans ce mémoire, nous présentons le fonctionnement global du système ainsi que ses caractéristiques principales. Elles portent sur la détection de l'écart de fréquence de résonance du capteur de force. / An atomic force microscope (AFM) is used to characterize insulating materials or semiconductors with a resolution up to the atomic length scale. The microscope includes a force sensor linked to a control electronic in order to properly characterize these materials. Among the various modes (static and dynamic), we focus mainly on the dynamic mode and especially on the frequency modulation mode (FM-AFM). In this mode, the force sensor is maintained as a harmonic oscillator by the servo system. The research project ANR Pnano2008 entitled: "metal piezoresistivity silicon carbide cantilever for very high frequency dynamic AFM" aims to significantly increase the performance of a FM-AFM by developing new very high frequency force sensors. The goal is to increase the sensitivity of the sensor and to decrease the time necessary to obtain topography images of the material. The control system of this new sensor must be able to detect frequency variations as small as 100mHz for cantilevers with resonance frequencies up to 50MHz. Since the state-of-the-art systems doe not present these performances, the objective of this thesis was to develop a new control system. It is fully digital and it is implemented on a FPGA based prototyping board. In this report, we present the system overall functioning and its main features which are related to the cantilever resonant frequency detection. This detection is managed by a phase locked loop (PLL) which is the key element of the system.

There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the advent of many new applications over the last few decades. The number of sensor nodes in these applications has also increased tremendously in the order of few hundreds in recent years. A typical sensor node in a WSN consists of circuits like RF transceivers, micro-controllers or DSP, ADCs, sensors, and power supply circuits. The RF transmitter and receiver circuits mainly the frequency synthesizers(synthesis of RF carrier and local oscillator signals in transceivers) consume a significant percentage of its total power due to its high frequency of operation. A charge-pump phase locked loop (CP-PLL) is the most commonly used frequency synthesizer architecture in these applications. The growing demands of WSN applications, such as low power consumption larger number of sensor nodes, single chip solution, and longer duration operation presents several design challenges for these transmitter and frequency synthesizer circuits in these applications and a few are listed below, Low power frequency synthesizer and transmitter designs with better spectral performance is essential for an energy efficient operation of these applications. The spurious tones in the frequency synthesizer output will mix the interference signals from nearby sensor nodes and from other interference sources present nearby ,to degrade the wireless transmitter and receiver performance[1]. With the increased density of sensor nodes (more number of in-band interference sources) and degraded performance of analog circuits in the nano-meter CMOS process technologies, the spur reduction techniques are essential to improve the performance of frequency synthesizers in these applications. A single chip solution of sensor nodes with its analog and digital circuits integrated on the same die is preferred for its low power, low cost, and reduced size implementation. However, the parasitic interactions between these analog and digital sub-systems integrated on a common substrate, degrade the spectral performance of frequency synthesizers in these implementations[2]. Therefore, techniques to improve the mixed signal integration performance of these circuits are in great demand. In this thesis, we present a custom designed energy efficient 2.4 GHz BFSK/ASK transmitter architecture using a low power frequency synthesizer design technique taking advantage of the CMOS technology scaling benefits. Furthermore, a few design guidelinesandsolutionstoimprovethespectralperformanceoffrequency synthesizer circuits and in-turn the performance of transmitters are also presented. The target application being short distance, low power, and battery operated wireless communication applications. The contributions in this thesis are, Spectral performance improvement techniques The CP mismatch current is a dominant source of reference spurs in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect [3]. In this work, we present a CP mismatch current calibration technique using an adaptive body bias tuning of its PMOS transistors. Chip prototype of 2.4 GHzCP-PLLwith the proposed CP calibration technique was fabricated in UMC 0.13 µm CMOS process. Measurements show a CP mismatch current of less than 0.3 µA(0.55 %) using the proposed calibration technique over the VCO control voltage range 0.3 to 1 V. The closed loop PLL measurements using the proposed technique exhibited a 9dB reduction in the reference spur levels across the PLL output frequency range 2.4 -2.5 GHz. The parasitic interactions between analog and digital circuits through the common substrate severely affects the performance of CP-PLLs. In this work, we experimentally demonstrate the effect of periodic switching noise generated from the digital buffers on the performance of charge-pump PLLs. The sensitivity of PLL performance metrics such as output spur level, phase noise, and output jitter are monitored against the variations in the properties of a noise injector digital signal. Measurements from a 500 MHz CP-PLL shows that the pulsed noise injection with the duty cycle of noise injector signal reduced from 50% to 20%, resulted in a 12.53 dB reduction in its output spur level and a 107 ps reduction in its Pk-Pk deterministic period jitter performance. Low power circuit techniques A low power frequency synthesizer design using a digital frequency multiplication technique is presented. The proposed frequency multiply by 3 digital edge combiner design having a very few logic gates, demonstrated a significant reduction in the power consumption of frequency synthesizer circuits, with an acceptable spectral performance suitable for these relaxed performance applications. A few design guidelines and techniques to further improve its spectral performance are also discussed and validated through simulations. Chip prototypes of 2.4 GHz CP-PLLs with and without digital frequency multiplier circuits are fabricated in UMC 0.13 µm CMOS process. The 2.4 GHz CP-PLL using the proposed digital frequency multiplication technique (10.7 mW) consumed a much reduced power compared to a conventional implementation(20.3 mW). A custom designed, energy efficient 2.4 GHz BFSK/ASK transmitter architecture using the proposed low power frequency synthesizer design technique is presented. The transmitter uses a class-D power amplifier to drive the 50Ω antenna load. Spur reduction techniques in frequency synthesizers are also used to improve the spectral performance of the transmitter. A chip prototype of the proposed transmitter architecture was implemented in UMC0.13 µm CMOS process. The transmitter consume14 mA current from a 1.3V supply voltage and achieve improved energy efficiencies of 0.91 nJ/bit and 6.1 nJ/bit for ASK and BFSK modulations with data rates 20Mb/s & 3Mb/s respectively.

Die Spezifikationen und Toleranzbereiche heutiger Hochgeschwindigkeitsdatenübertragungstechnologien nehmen immer weiter an Komplexität, aufgrund der steigenden Informationsmenge, zu. Zur Verarbeitung von Daten in Frequenzbereichen oberhalb von einem Gigahertz sind Referenzsignale notwendig, welche ein äußerst geringes Phasenrauschen aufweisen um benachbarte Kanäle nicht zu beeinflussen. Diese Referenzsignale werden in Mischerschaltungen zur Modulation oder Demodulation zwischen radio frequency (RF)- und intermediate frequency (IF)-Signalen verwendet. Die benötigte Signalform ist eine Sinusschwingung, die nicht durch digitale Schaltungsblöcke erzeugt werden kann. Daher ist die Notwendigkeit von analogen LC-Oszillatoren gegeben. Die Erzeugung von höchst stabilen und hochfrequenten Signalen war lange Zeit teuren Silizium-Germanium-Technologien vorbehalten. Jedoch erfordert der steigende Integrationsgrad und der hart umkämpfte Markt, die Entwicklung von RF-Schaltungen in günstigen CMOS-Technologien. In Zusammenarbeit mit der Landshut Silicon Foundry soll dazu eine monolithisch integrierte Phase-Locked Loop (PLL) mit einer mittleren Ausgangsfrequenz von 2,44 GHz und einem Phasenrauschen kleiner -115 dBc/Hz bei einem Abstand von 1 MHz vom Träger entwickelt werden. Dabei wird das Hauptaugenmerk auf den Kern der PLL gelegt, welcher einen spannungsgesteuerten Oszillator, einen Phasen-/Frequenzdetektor, eine Ladungspumpe, einen Schleifenfilter und einen Frequenzteiler beinhaltet. Außerdem sollen Testszenarien vorgestellt werden, um die Eigenschaften der gefertigten PLL zu bestimmen und zu vergleichen.

Les transmissions numériques par satellite sont largement utilisées dans plusieurs domaines allant des applications commerciales en orbites terrestres aux missions d'exploration scientifiques en espace lointain (Deep Space). Ces systèmes de transmission fonctionnent sur des très grandes distances et ils disposent des ressources énergétiques très limitées. Cela se traduit par un très faible rapport signal à bruit au niveau de la station de réception terrestre. Une possibilité d'établir une liaison fiable dans ces conditions très défavorables, réside dans l'utilisation de codes correcteurs d'erreurs puissants tels que les Turbo codes et le LDPC. Cependant, les gains de codage sont conditionnés par le bon fonctionnement des étages de la démodulation cohérente en amont, notamment l'étage de synchronisation. L'opération de synchronisation consiste à estimer et compenser le décalage en phase et en fréquence entre le signal reçu et l'oscillateur local du récepteur. Ces décalages sont généralement provoqués par des imperfections matérielles et le phénomène d'effet Doppler. A très faible rapport signal à bruit, les systèmes de synchronisation actuels se trouvent limités et incapables d'assurer les performances requises. Notre objectif est de fiabiliser l'étage de synchronisation du récepteur dans des conditions très difficiles de faible rapport signal sur bruit, d'effet Doppler conséquent avec prise en compte d'un phénomène d'accélération (Doppler rate) et d'une transmission sans pilote. Cette thèse CIFRE traite du problème de la synchronisation porteuse pour la voie descendante d'une transmission Deep Space. Après la réalisation d'une étude de l'état de l'art des techniques de synchronisation, nous avons retenu les boucles à verrouillage de phase (PLL: Phase Locked Loop). Dans un contexte industriel, les PLL offrent le meilleur compromis entre complexité d'implémentation et performances. Plusieurs détecteurs de phase basés le critère du maximum de vraisemblance ont été considérés et modélisés par leurs courbes caractéristiques. En se basant sur les modèles équivalents, nous avons développé une nouvelle étude de la phase d'acquisition non-linéaire d'une PLL du deuxième ordre avec un détecteur de phase semi-sinusoïdal. La deuxième partie de la thèse a été consacrée à l'étude des techniques de combinaison d'antennes. Ces méthodes visent à exploiter la diversité spatiale et améliorer le bilan de liaison de la chaîne de transmission tout en offrant une flexibilité de conception ainsi qu'une réduction considérable du coût d'installation. A l'issue de cette partie, nous avons proposé un nouveau schéma de combinaison d'antenne qui améliore le seuil de fonctionnement des systèmes existants. / In deep space communication systems, the long distance between the spacecraft and the ground station along with the limited capacity of the on-board power generator result a very low signal to noise ratio (SNR). However, such transmission still possible by using near Shannon limit error correction codes (Turbo code and LDPC code). Nevertheless, to take advantage of this coding gain, the coherent demodulation is mandatory, and the carrier phase synchronization must be reliable at more restrictive SNR. At very low SNR, current synchronization systems are limited and unable to provide the required performances. Our goal is to improve the reliability of the receiver synchronization stage under very difficult conditions of a very low SNR, a variable Doppler effect (Doppler rate) and a blind transmission. This thesis deals with the problem of carrier phase synchronization for the downlink of a Deep Space transmission. After the study of the existing solutions, we selected the phase locked loop (Phase Locked Loop: PLL). In an industrial context, PLL offers the best trade-off between complexity and performance. Several phase detectors based on the maximum likelihood criterion were considered and characterized by their S-curves. Based on the equivalent models, we have developed a new study of the non-linear acquisition phase of a second-order PLL with a semi-sinusoidal phase error detector. The second part of the thesis was dedicated to the antennas combining techniques. These methods aim to improve the link budget of the transmission and offer more flexibility. At the end of this part, we proposed a new antennas combining scheme that improves the operating threshold of existing systems.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / O objetivo deste trabalho é contribuir com o desenvolvimento de uma técnica baseada em sistemas inteligentes que possibilite a localização exata ou aproximada do ponto de origem de uma Variação de Tensão de Curta Duração (VTCD) (gerada por uma falta) em um sistema de distribuição de energia elétrica. Este trabalho utiliza um Phase-Locked Loop (PLL) com o intuito de detectar as faltas. Uma vez que a falta é detectada, os sinais de tensão obtidos durante a falta são decompostos em componentes simétricas instantâneas por meio do método proposto. Em seguida, as energias das componentes simétricas são calculadas e utilizadas para estimar a localização da falta. Nesta pesquisa, são avaliadas duas estruturas baseadas em Redes Neurais Artificiais (RNAs). A primeira é projetada para classificar a localização da falta em um dos pontos possíveis e a segunda é projetada para estimar a distância da falta ao alimentador. A técnica aqui proposta aplica-se a alimentadores trifásicos com cargas equilibradas. No desenvolvimento da mesma, considera-se que há disponibilidade de medições de tensões no nó inicial do alimentador e também em pontos esparsos ao longo da rede de distribuição. O banco de dados empregado foi obtido através de simulações de um modelo de alimentador radial usando o programa PSCAD/EMTDC. Testes de sensibilidade empregando validação-cruzada são realizados em ambas as arquiteturas de redes neurais com o intuito de verificar a confiabilidade dos resultados obtidos. Adicionalmente foram realizados testes com faltas não inicialmente contidas no banco de dados a fim de se verificar a capacidade de generalização das redes. Os desempenhos de ambas as arquiteturas de redes neurais foram satisfatórios e demonstram a viabilidade das técnicas propostas para realizar a localização de faltas em redes de distribuição. / The aim of this work is to contribute to the development of a technique based on intelligent systems that allows the accurate location of the Short Duration Voltage Variations (SDVV) origin in an electrical power distribution system. Once the fault is detected via a Phase-Locked Loop (PLL), voltage signals acquired during the fault are decomposed into instantaneous symmetrical components by the proposed method. Then, the energies of the symmetrical components are calculated and used to estimate the fault location. In this work, two systems based on Artificial Neural Networks (ANN) are evaluated. The first one is designed to classify the fault location into one of predefined possible points and the second is designed to estimate the fault distance from the feeder. The technique herein proposed is applies to three-phase feeders with balanced loads. In addition, it is considered that there is availability of voltage measurements in the initial node of the feeder and also in sparse points along the distribution power grid. The employed database was made using simulations of a model of radial feeder using the PSCAD / EMTDC program. Sensitivity tests employing cross-validation are performed for both approaches in order to verify the reliability of the results. Furthermore, in order to check the generalization capability, tests with faults not originally contained in the database were performed. The performances of both architectures of neural networks were satisfactory and they demonstrate the feasibility of the proposed techniques to perform fault location on distribution grids.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / O objetivo deste trabalho é contribuir com o desenvolvimento de uma técnica baseada em sistemas inteligentes que possibilite a localização exata ou aproximada do ponto de origem de uma Variação de Tensão de Curta Duração (VTCD) (gerada por uma falta) em um sistema de distribuição de energia elétrica. Este trabalho utiliza um Phase-Locked Loop (PLL) com o intuito de detectar as faltas. Uma vez que a falta é detectada, os sinais de tensão obtidos durante a falta são decompostos em componentes simétricas instantâneas por meio do método proposto. Em seguida, as energias das componentes simétricas são calculadas e utilizadas para estimar a localização da falta. Nesta pesquisa, são avaliadas duas estruturas baseadas em Redes Neurais Artificiais (RNAs). A primeira é projetada para classificar a localização da falta em um dos pontos possíveis e a segunda é projetada para estimar a distância da falta ao alimentador. A técnica aqui proposta aplica-se a alimentadores trifásicos com cargas equilibradas. No desenvolvimento da mesma, considera-se que há disponibilidade de medições de tensões no nó inicial do alimentador e também em pontos esparsos ao longo da rede de distribuição. O banco de dados empregado foi obtido através de simulações de um modelo de alimentador radial usando o programa PSCAD/EMTDC. Testes de sensibilidade empregando validação-cruzada são realizados em ambas as arquiteturas de redes neurais com o intuito de verificar a confiabilidade dos resultados obtidos. Adicionalmente foram realizados testes com faltas não inicialmente contidas no banco de dados a fim de se verificar a capacidade de generalização das redes. Os desempenhos de ambas as arquiteturas de redes neurais foram satisfatórios e demonstram a viabilidade das técnicas propostas para realizar a localização de faltas em redes de distribuição. / The aim of this work is to contribute to the development of a technique based on intelligent systems that allows the accurate location of the Short Duration Voltage Variations (SDVV) origin in an electrical power distribution system. Once the fault is detected via a Phase-Locked Loop (PLL), voltage signals acquired during the fault are decomposed into instantaneous symmetrical components by the proposed method. Then, the energies of the symmetrical components are calculated and used to estimate the fault location. In this work, two systems based on Artificial Neural Networks (ANN) are evaluated. The first one is designed to classify the fault location into one of predefined possible points and the second is designed to estimate the fault distance from the feeder. The technique herein proposed is applies to three-phase feeders with balanced loads. In addition, it is considered that there is availability of voltage measurements in the initial node of the feeder and also in sparse points along the distribution power grid. The employed database was made using simulations of a model of radial feeder using the PSCAD / EMTDC program. Sensitivity tests employing cross-validation are performed for both approaches in order to verify the reliability of the results. Furthermore, in order to check the generalization capability, tests with faults not originally contained in the database were performed. The performances of both architectures of neural networks were satisfactory and they demonstrate the feasibility of the proposed techniques to perform fault location on distribution grids.

Renewable energy sources normally require power converters to convert their energy into standardized regulated ac output. The motivation for this thesis is to design and control power converters for renewable energy systems to ensure very good power quality, efficiency and reliability. The renewable energy sources considered are low voltage dc sources such as photovoltaic (PV) modules. Two transformer-isolated power circuit topologies with input voltage of less than 50V are designed and developed for low and medium power applications. Various design and control issues of these converters are identified and new solutions are proposed. For low power rating of a few hundred watts, a line-frequency transformer interfaced inverter is developed. In the grid connected operation, it is observed that this topology injects considerable lower order odd and even harmonics in the grid current. The reasons for this are identified. A new current control method using adaptive harmonic compensation technique and a proportional-resonant-integral (PRI) controller is proposed. The proposed current controller is designed to ensure that the grid current harmonics are within the limits set by the IEEE 1547-2003 standard. Phase-locked loops (PLLs) are used for grid synchronization of power converters in grid-tied operation and for closed-loop control reference generation. Analysis and design of synchronous reference frame PLL (SRF-PLL) and second-order generalized integrator (SOGI) based PLLs considering unit vector distortion under the possible non-ideal grid conditions of harmonics, unbalance, dc offsets and frequency deviations are proposed and validated. Both SRF-PLL and SOGI-PLL are low-complexity PLLs. The proposed designs achieve fastest settling time for these PLLs for a given worst-case input condition. The harmonic distortion and dc offsets in the resulting unit vectors are limited to be well within the limits set by the IEEE 1547-2003 standard. The proposed designs can be used to achieve very good performance using conventional low-complexity PLLs without the requirement of advanced PLLs which can be computationally intensive. A high-frequency (HF) transformer interfaced ac link inverter with a lossless snubber is developed medium power level in the order of few kilowatts. The HF transformer makes the topology compact and economical compared to an equally rated line frequency transformer. A new synchronized modulation method is proposed to suppress the possible over-voltages due to current commutation in the leakage inductance of the HF transformer. The effect of circuit non-ideality of turn-on delay time is analyzed. The proposed modulation mitigates the problem of spurious turn-on that can occur due to the turn-on delay time. The HF inverter, rectifier and snubber devices have soft switching with this modulation. A new reliable start-up method is proposed for this inverter topology without any additional start- up circuitry. This solves the problems of over-voltages and inrush currents during start-up. The overall research work reported in the thesis shows that it is possible to have compact, reliable and high performance power converters for renewable energy conversion systems. It is also shown that high control performance and power quality can be achieved using the proposed control techniques of low implementation complexity.