Cheng Sin-hang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 90-92). / Abstracts in English and Chinese. / Chapter Chapter 1 --- Introduction --- p.1 / Chapter Chapter 2 --- Theory of Oscillator Design --- p.4 / Chapter 2.1 --- Open-loop approach --- p.4 / Chapter 2.2 --- One-port approach --- p.6 / Chapter 2.3 --- Two-port approach --- p.9 / Chapter 2.4 --- Voltage controlled oscillator (VCO) design --- p.10 / Chapter 2.4.1 --- Active device selection and biasing --- p.11 / Chapter 2.4.2 --- Feedback circuit design --- p.15 / Chapter 2.4.3 --- Frequency tuning circuit --- p.20 / Chapter Chapter 3 --- Noise in Oscillators --- p.23 / Chapter 3.1 --- Origin of phase noise --- p.23 / Chapter 3.2 --- Impact of phase noise in communication system --- p.28 / Chapter 3.3 --- Phase noise consideration in VCO design --- p.30 / Chapter Chapter 4 --- Low Temperature Co-Fired Ceramic --- p.31 / Chapter 4.1 --- LTCC process --- p.31 / Chapter 4.1.1 --- LTCC fabrication process --- p.32 / Chapter 4.1.2 --- LTCC materials --- p.34 / Chapter 4.1.3 --- Advantages of LTCC technology --- p.35 / Chapter 4.2 --- Passive components realization in LTCC --- p.37 / Chapter 4.2.1 --- Capacitor --- p.37 / Chapter 4.2.2 --- Inductor --- p.42 / Chapter Chapter 5 --- High-Q LTCC Resonator Design --- p.47 / Chapter 5.1 --- Definition of Q-factor --- p.47 / Chapter 5.2 --- Stripline --- p.50 / Chapter 5.3 --- Power losses --- p.52 / Chapter 5.4 --- Laminated stripline resonator design --- p.53 / Chapter 5.4.1 --- λ/4 resonator structure --- p.57 / Chapter 5.4.2 --- Meander-line resonator structure --- p.60 / Chapter 5.4.3 --- Bi-metal-layer resonator structure --- p.63 / Chapter Chapter 6 --- LTCC Voltage Controlled Oscillator Design --- p.67 / Chapter 6.1 --- Circuit design --- p.67 / Chapter 6.2 --- Output filter --- p.68 / Chapter 6.3 --- Embedded capacitor --- p.71 / Chapter 6.4 --- VCO layout and simulation --- p.72 / Chapter Chapter 7 --- Experimental Setup and Results --- p.77 / Chapter 7.1 --- Measured Result: LTCC resonators --- p.77 / Chapter 7.1.1 --- Experimental results --- p.79 / Chapter 7.2 --- Measured results: LTCC voltage controlled oscillators --- p.83 / Chapter Chapter 8 --- Conclusion and Future Work --- p.88 / Reference List --- p.90 / Appendix A: TRL calibration method --- p.93 / Appendix B: Q measurement --- p.103 / Appendix C: Q-factor extraction program listing --- p.109 / Chapter 1. --- Function used to calculate Q from s-parameter --- p.109 / Chapter 2. --- Function used to calculate Q from z-parameter --- p.111

Yip Kim-fung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 95-100). / Abstracts in English and Chinese. / Abstract --- p.I / Acknowledgement --- p.III / Table of Contents --- p.IV / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Objective --- p.6 / Chapter Chapter 2 --- Theory of Oscillators --- p.7 / Chapter 2.1 --- Oscillator Design --- p.7 / Chapter 2.1.1 --- Loop-Gain Method --- p.7 / Chapter 2.1.2 --- Negative Resistance-Conductance Method --- p.8 / Chapter 2.1.3 --- Crossed-Coupled Oscillator --- p.10 / Chapter Chapter 3 --- Noise Analysis --- p.15 / Chapter 3.1 --- Origin of Noise Sources --- p.16 / Chapter 3.1.1 --- Flicker Noise --- p.16 / Chapter 3.1.2 --- Thermal Noise --- p.17 / Chapter 3.1.3 --- Noise Model of Varactor --- p.18 / Chapter 3.1.4 --- Noise Model of Spiral Inductor --- p.19 / Chapter 3.2 --- Derivation of Resonator --- p.19 / Chapter 3.3 --- Phase Noise Model --- p.22 / Chapter 3.3.1 --- Leeson's Model --- p.23 / Chapter 3.3.2 --- Phase Noise Model defined by J. Cranincks and M Steyaert --- p.24 / Chapter 3.3.3 --- Non-linear Analysis of Phase Noise --- p.26 / Chapter 3.3.4 --- Flicker-Noise Upconversion Mechanism --- p.31 / Chapter 3.4 --- Phase Noise Reduction Techniques --- p.33 / Chapter 3.4.1 --- Conventional Tank Circuit Structure --- p.33 / Chapter 3.4.2 --- Enhanced Q tank circuit Structure --- p.35 / Chapter 3.4.3 --- Tank Circuit with parasitics --- p.37 / Chapter 3.4.4 --- Reduction of Up-converted Noise --- p.39 / Chapter Chapter 4 --- CMOS Technology and Device Modeling --- p.42 / Chapter 4.1 --- Device Modeling --- p.42 / Chapter 4.1.1 --- FET model --- p.42 / Chapter 4.1.2 --- Layout of Interdigitated FET --- p.46 / Chapter 4.1.3 --- Planar Inductor --- p.48 / Chapter 4.1.4 --- Circuit Model of Planar Inductor --- p.50 / Chapter 4.1.5 --- Inductor Layout Consideration --- p.54 / Chapter 4.1.6 --- CMOS RF Varactor --- p.55 / Chapter 4.1.7 --- Parasitics of PMOS-type varactor --- p.57 / Chapter Chapter 5 --- Design of Integrated CMOS VCOs --- p.59 / Chapter 5.1 --- 1.5GHz CMOS VCO Design --- p.59 / Chapter 5.1.1 --- Equivalent circuit model of differential LC VCO --- p.59 / Chapter 5.1.2 --- Reference Oscillator Circuit --- p.61 / Chapter 5.1.3 --- Proposed Oscillator Circuit --- p.62 / Chapter 5.1.4 --- Output buffer --- p.63 / Chapter 5.1.5 --- Biasing Circuitry --- p.64 / Chapter 5.2 --- Spiral Inductor Design --- p.65 / Chapter 5.3 --- Determination of W/L ratio of FET --- p.67 / Chapter 5.4 --- Varactor Design --- p.68 / Chapter 5.5 --- Layout (Cadence) --- p.69 / Chapter 5.6 --- Circuit Simulation (SpectreRF) --- p.74 / Chapter Chapter 6 --- Experimental Results and Discussion --- p.76 / Chapter 6.1 --- Measurement Setup --- p.76 / Chapter 6.2 --- Measurement results: Reference Oscillator Circuit --- p.81 / Chapter 6.2.1 --- Output Spectrum --- p.81 / Chapter 6.2.2 --- Phase Noise Performance --- p.82 / Chapter 6.2.3 --- Tuning Characteristic --- p.83 / Chapter 6.2.4 --- Microphotograph --- p.84 / Chapter 6.3 --- Measurement results: Proposed Oscillator Circuit --- p.85 / Chapter 6.3.1 --- Output Spectrum --- p.85 / Chapter 6.3.2 --- Phase Noise Performance --- p.86 / Chapter 6.3.3 --- Tuning Characteristic --- p.87 / Chapter 6.3.4 --- Microphotograph --- p.88 / Chapter 6.4 --- Comparison of Measured Results --- p.89 / Chapter 6.4.1 --- Phase Noise Performance --- p.89 / Chapter 6.4.2 --- Tuning Characteristic --- p.90 / Chapter Chapter 7 --- Conclusion and Future Work --- p.93 / Chapter 7.1 --- Conclusion --- p.93 / Chapter 7.2 --- Future Work --- p.94 / References --- p.95 / Author's Publication --- p.100 / Appendix A --- p.101 / Appendix B --- p.104 / Appendix C --- p.106

Digital communication systems invariably employ an underlying analog communication channel. At the transmitter, data is modulated to obtain an analog waveform which is input to the channel. At the receiver, the output of the channel needs to be mapped back into the discrete domain. To this effect, the continuous-time received waveform is sampled at instants chosen by the timing recovery block. Therefore, timing recovery is an essential component of digital communication systems. A widely used timing recovery method is based on a phase-locked loop (PLL), which updates its timing estimates based on a decision-directed device. Timing recovery performance is a strong function of the reliability of decisions, and hence, of the channel signal-to-noise ratio (SNR). Iteratively decodable error-control codes (ECCs) like turbo codes and LDPC codes allow operation at SNRs lower than ever before, thus exacerbating timing recovery. We propose iterative timing recovery, where the timing recovery block, the equalizer and the ECC decoder exchange information, giving the timing recovery block access to decisions that are much more reliable than the instantaneous ones. This provides significant SNR gains at a marginal complexity penalty over a conventional turbo equalizer where the equalizer and the ECC decoder exchange information. We also derive the Cramer-Rao bound, which is a lower bound on the estimation error variance of any timing estimator, and propose timing recovery methods that outperform the conventional PLL and achieve the Cramer-Rao bound in some cases. At low SNR, timing recovery suffers from cycle slips, where the receiver drops or adds one or more symbols, and consequently, almost always the ECC decoder fails to decode. Iterative timing recovery has the ability to corrects cycle slips. To reduce the number of iterations, we propose cycle slip detection and correction methods. With iterative timing recovery, the PLL with cycle slip detection and correction recovers most of the SNR loss of the conventional receiver that separates timing recovery and turbo equalization.

A Delay-Locked Loop (DLL) for the generation of multiple clock phases/delays is proposed. Several new techniques are used to help enhance the DLLs performance, specifically, to achieve wide lock range, short locking time, and reduced jitter. The DLL can be used for a variety of applications which require precise time intervals or phase shifts. The phase detector (PD), charge pump (CP), and voltage-controlled delay line (VCDL) are the three most important blocks in a DLL. In our research, we have proposed a novel structure which integrates the functionality of both the PD and CP. By using this structure, a fast switching speed can be achieved. Moreover, the combined PD and CP also lead to reduced chip area and better jitter performance. A novel phase detection algorithm is developed and implemented in the combined PD and CP structure. This algorithm also involves a start-control circuit to avoid locking failure or false lock to harmonics. With the help of this algorithm, the proposed DLL is able to achieve lock as long as the minimum VCDL delay is less than one reference clock cycle, which is the largest possible lock range that can be achieved by the DLL. The VCDL uses fully differential signaling to minimize jitter. The delay stage of the VCDL is built with a differential topology using symmetrical loads and replica-feedback biasing, which provides a low sensitivity to supply and substrate noise as well as a wide tuning range. In addition, a shift-averaging technique is used to improve the matching between delay stages and thus to equalize the delay of each individual stage.

The object of this research is to develop robust wire-line systems which demonstrate high performance while simultaneously consuming low power. The main focus of this work is the Clock and Data Recovery (CDR) system, which is the primary circuit of any modern wire-line transceiver. Different techniques starting from circuit-level to system-level have been investigated in this work to improve the performance of multi-gigabit CDRs. A 62 GHz bandwidth amplifier has been presented to address the need for a scalable amplifier for CDR needs. A new technique has been proposed to improve the radiation immunity of latches, to reduce the BER in CDRs occurring due to package radiations. An injection-lock based clock recovery method was investigated as an alternative to PLL based CDRs as they can be used for burst-mode wire-line communication. The investigation yielded the vulnerability of the method to jitter (false-locking and high jitter transfer), the attenuation of which is critical to commercial CDRs. A novel false-lock detector system has been proposed and demonstrated for the first time as a robust solution to the issue of false-locking of CDRs due to repetitive patterns. The implementation of the final CDR system required the use of an L-C tank VCO, the components of which are generic for all commercial CDRs. A new systematic layout technique for the VCO has been proposed and demonstrated in this work to substantially improve the layout area and the associated parasitics, approximately by 70 %. This new layout addresses a critical yet often neglected part of VCO design. Furthermore, a new concept has been proposed to optimize static dividers with respect to their power consumption and number of devices.

A frequency synthesizer plays a critical role in defining the performance of wireless systems in terms of measures such as operating frequency range, settling time, phase noise and spur performance, and area/power consumption. As the trend in mobile system design has changed from single-standard systems to multi-standard/multi-application systems, the role of frequency synthesizers has become even more important. As the most popular architecture, a phase-locked loop (PLL)-based frequency synthesizer has been researched over the last several decades; however, many unsolved problems related to the PLL-based synthesizer are still waiting for answers. This dissertation addresses key challenges related to fully integrated PLL-based frequency synthesizers, including the problem of large area consumption of passive components, the inherent reference-spur problem, and the problem of trade-offs between integer-N PLLs and fractional-N PLLs. In this dissertation, new techniques and architectures are presented and developed to address those challenges. First, a low-phase-noise ring oscillator and a capacitor multiplier with a high-multiplication factor efficiently minimize the silicon area of sub-components, and a compact programmable delay-locked loop (DLL)-based frequency multiplier is developed to replace the PLL-based frequency synthesizer. Second, the charge-distribution mechanism for suppressing reference spurs is theoretically analyzed, and an edge interpolation technique for implementing the mechanism is developed. Finally, the concept and the architecture of sub-integer-N PLL is proposed and implemented to remove trade-offs between conventional integer-N PLLs and fractional-N PLLs.

Thesis (M.App.Sc.) - Carleton University, 2002. / Includes bibliographical references (p. 93-95). Also available in electronic format on the Internet.

Στα πλαίσια της παρούσας διπλωματικής εργασίας μελετήθηκαν οι βασικές αρχές λειτουργίας και θορύβου στα Phase Locked Loops. Στη συνέχεια σχεδιάστηκε το σχηματικό και το layout ενός PLL μικτού σήματος στο λογισμικό σχεδίασης ολοκληρωμένων κυκλωμάτων, Cadence IC5141. Το κύκλωμα αυτό λειτουργεί σαν συνθέτης συχνοτήτων στην περιοχή των 5GHz, από μία συχνότητα αναφοράς 50MHz, έχει θόρυβο φάσης περίπου 88dBc στο 1MHz από το φορέα και μέση κατανάλωση λιγότερο από 30mW. / Analysis of basic operation principles and noise performance of Phase Locked Loops. Design of a PLL (schematic and layout) in Cadence IC5141.

The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator is designed to extract the subtle response from the system so that target parameters can be predicted. Different testing methodologies are applied different specification testing as well. Finally, an on chip phase-locked loop design is implemented for reference spur calibration. The phase-locked loop is designed with a programmable reference spur range. A static phase offset detector is included to identify the optimal setting of reference spur in the feedback system. The integrated jitter performance is improved by the calibration mechanism. The results of this thesis serve as an on-chip built-in self-test and self-calibration solution for embedded phase-locked loops in a high integration system.

Apresenta-se a evolução dos sitemas de comunicação, com ênfase especial nos sistemas com tecnologia óptica. Discute-se a necessidade contínua do aumento de capacidade de tais sistemas de comunicação, e a consequente repercussão sobre os futuros sistemas ópticos. Em vista da necessidade do aumento de capacidade dos futuros sistemas de comunicação óptica, apresentam-se em seguida duas propostas recentes da literatura, sendo uma referente à realização de um gerador de pulsos ópticos estreitos, e a outra referente à implementação de um extrator de relógio realizado com técnicas ópticas. Apresenta-se um breve resumo da teoria das malhas de sincronismo de fase, ou PLLs, mostrando como as duas propostas discutidas realizam funções típicas desses sistemas. Ressalta-se a necessidade dos PLLs de sistemas ópticos possuirem ganhos de malha (parâmetro K) elevados. Após a caracterização dos requisitos necessários para PLLs de futuros sistemas ópticos, e após um resumo de alguns conceitos necessários da teoria de redes e filtros elétricos, apresentam-se dois tipos de projeto de filtros para aqueles PLLs. As duas formas de projeto tem como objetivo viabilizar o uso de filtros de tipo e ordem arbitrários. Um tipo de projeto visa a realização da função de transferência do PLL com a curva de resposta igual à de um filtro escolhido. O outro tipo de projeto parte da realização do filtro de loop do PLL com as características de um tipo de filtro escolhido, e define métodos para ajustar a função de transferência resultante para esse PLL. Apresentam-se algoritmos para o cálculo de parâmetros importantes nos dois procedimentos. Após a discussão dos dois pontos de vista de projeto, apresentam-se exemplos de realização de PLLs de acordo com as técnicas apresentadas. Para cada exemplo, mostram-se as curvas de resposta em frequência tanto do PLL como do correspondente filtro de loop, bem como o lugar das raízes e a resposta de captura do PLL obtido. O processo de captura foi estudado por simulações que procuram reproduzir o mais fielmente possível as condições reais de implementação, sem entretanto considerar efeitos de ruído. Finalmente, mencionam-se brevemente possíveis linhas de pesquisa futuras, sendo o foco principal o uso de filtros com pólos e zeros finitos. / The evolution of communication systems is discussed, with emphasis on optical technology. Special consideration is given to the continuous need for increasing the capacity of such systems, and the impact over future optical communication. In view of the great demands imposed over the capacity of future optical systems, an overview is presented of two recent proposals found in the literature, one of such proposals being the implementation of a generator of short optical pulses, and the other being a clock extractor device realized through the use of optical techniques. A brief review is made of phase-locked loop (or PLL) theory, to show how the discussed proposals could be used to realize tipical functions found in these systems. The very high loop gains (the so-called parameter K) that must be used in PLLs of optical communication systems are emphasized. After discussion of the necessary characteristics for PLLs of future optical systems, and also after a review of some concepts of the theory of electrical networks and filters, two design procedures for filters to be used in such PLLs are presented. Both designs have the goal of allowing the use of loop filters with any type and order. The first type of design has the objective to realize a PLL transfer function that has a frequency response identical to the response of a chosen type of filter. The other design starts with a chosen type of filter for a PLL loop filter, arriving to an suitable PLL transfer function. Some algorithms for determination of important design parameters are also presented. After the discussion of the two types of design, some examples of PLLs obtained by such methods are presented. For each example, frequency response curves are presented for the PLL and the respective loop filter, as well as the root locus and the capture response for the PLL so obtained. The capture process was studied through the use of simulations with parameters intended to approximate real implementation conditions, although noise effects are not considered. Finally, some possible research lines are discussed, whose main focus is on filters with finite poles and zeros.