Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal systems i. e. top-down design and bottom-up verification methodology is required. This methodology has already been established for digital design. The goal of this research is to propose a new design methodology for mixed signal systems. In the first two chapters of this thesis, the need for a mixed signal design flow based on top-down design methodology will be discussed. The proposed design flow is based on behavioral modeling of the mixed signal system using one of the mixed signal behavioral modeling languages. These models can be used for design and verification through different steps of the design from system level modeling to final physical design. The other advantage of the proposed flow is analog and digital co-design. In the remaining chapters of this thesis, the proposed design flow was verified by designing an 800 MHz mixed signal PLL. The PLL uses a charge pump phase frequency detector, a single capacitor loop filter, and a feed forward error correction architecture using an active damping control circuit instead of passive resistor in loop filter. The design was done in 0. 18- <i>µ</i> m CMOS process technology.

Dissertation (Ph.D.)--Auburn University,2006. / Abstract. Vita. Includes bibliographic references (p.110-113).

Linearity enhancement, especially within the front end of a wireless receiver IC design, is highly desirable since it allows the front-end to withstand strong interferers from co-existing communication standards or other wireless radiators. We propose an interferer suppression method based on feed-forward cancellation that uses an injectionlocked oscillator (ILO) to extract the interferer from the incident spectrum. The technique is expected to be useful in environments where a strong narrowband interferer appears along with a wideband desired signal, such as ultra-wideband (UWB) and emerging cognitive-radio applications. The ILO is further embedded within a phase-locked loop which provides several advantages including ILO center frequency self tuning and automatic phase alignment between the main signal path and the auxiliary path. An IC that uses this approach is implemented in a UMC 0.18[mu]m RFCMOS process. In measurement, the chip demonstrates 20dB suppression for phase and frequency modulated interferers while maintaining around 18dB power gain and noise figure below 5dB, measured with an off-chip balun for the desired signal. Techniques for canceling amplitude modulated interferers, though not included in the integrated circuit, were also demonstrated with an off chip amplitude control loop. Over 20dB rejection was obtained with AM interferers with properly scaled envelop signal applied to the ILO bias port. A second LNA was connected in cascade with the system to emulate the input stage of a down-conversion mixer and the cascaded P1dB was improved over 16dB with cancellation on. Gain compression above 13dB was also observed when auxiliary path was disabled, at the same input level as the P1dB with cancellation applied. / text

The Phase Locked Loops (PLLs) are widely used in contemporary electronic systems for frequency synthesis, clock recovery, frequency multiplication and other purposes. Because of continuous increase in operating frequency of clocking systems the requirements on the clock spectral purity and low jitter became very demanding and are one of major designers' concerns.Frequency synthesizers used in microprocessors are integrated on the same substrate as the rest of the circuit and thus suffer from a substantial switching noise injected into global supply and ground busses. Usually when the reference signal comes from a crystal oscillator, VCO becomes a main source of phase noise. A designer of VCO needs to determine the best circuit structure by considering different prototypical perturbations scenarios and predicting the worst case and jitter response when the perturbation signals are switched on and off. Therefore the time efficient estimation of the jitter effects resulting from many shapes, frequencies and phases of perturbation is critical.The presented dissertation demonstrates simulation methodology for rapid estimation of jitter in oscillators, particularly in VCOs, caused by perturbation sources such as power supply and substrate couplings. The methodology is also extended to these types of PLLs in which the VCO instability is a main contributor to the output timing jitter.Simulation of oscillatory circuits is strongly effected by the round-off errors. Special technique was developed to eliminate these effects.The technique is applicable for predicting timing non-idealities for arbitrary perturbation shapes, frequencies and phases. Different jitter metrics can be easily extracted for all important perturbation scenarios.The methodology utilizes the new concept of the transient multi-cycle Voltage Impulse Sensitivity Function (VISF), which has been developed in the dissertation. It contains information about sensitivity of oscillator to noise injection and also allows for efficient prediction of the transient effects caused by switching on and off the perturbation sources. The methodology offers efficiency and great simplicity of use, which frees designers from complicated, time consuming analysis of data generated by a simulator. The very involved postprocessing of simulation data can be fully automated.

Frequency synthesizers are essential components for modern wireless and wireline communication systems as they provide the local oscillator signal required to transmit and receive data at very high rates. They are also vital for computing devices and microcontrollers as they generate the clocks required to run all the digital circuitry responsible for the high speed computations. Data rates and clocking speeds are continuously increasing to accommodate for the ever growing demand on data and computational power. This places stringent requirements on the performance metrics of frequency synthesizers. They are required to run at higher speeds, cover a wide range of frequencies, provide a low jitter/phase noise output and consume minimum power and area. In this work, we present new techniques and architectures for implementing high speed frequency synthesizers which fulfill the aforementioned requirements. We propose a new architecture and design approach for the realization of wideband millimeter-wave frequency synthesizers. This architecture uses two-step multi-order harmonic generation of a low frequency phase-locked signal to generate wideband mm-wave frequencies. A prototype of the proposed system is designed and fabricated in 90nm Complementary Metal Oxide Semiconductor (CMOS) technology. Measurement results demonstrated that a very wide tuning range of 5 to 32 GHz can be achieved, which is costly to implement using conventional techniques. Moreover the power consumption per octave resembles that of state-of-the art reports. Next, we propose the N-Push cyclic coupled ring oscillator (CCRO) architecture to implement two high performance oscillators: (1) a wideband N-Push/M-Push CCRO operating from 3.16-12.8GHz implemented by two harmonic generation operations using the availability of different phases from the CCRO, and (2) a 13-25GHz millimeter-wave N-Push CCRO with a low phase noise performance of -118dBc/Hz at 10MHz. The proposed oscillators achieve low phase noise with higher FOM than state of the art work. Finally, we present some improvement techniques applied to the performance of phase locked loops (PLLs). We present an adaptive low pass filtering technique which can reduce the reference spur of integer-N charge-pump based PLLs by around 20dB while maintaining the settling time of the original PLL. Another PLL is presented, which features very low power consumption targeting the Medical Implantable Communication Standard. It operates at 402-405 MHz while consuming 600microW from a 1V supply.

The performance of the High voltage dc systems is dependent on the stiffness of the ac bus, it is connected to. With the traditional synchronous reference frame-phase locked loops (SRF-PLL), voltage source converters (VSC) systems with large PLL gains, connected to weak ac networks are shown to be prone to instabilities, when subject to disturbances. In this thesis a new Adaptive PLL is designed with a pre-filter topology which extracts the fundamental positive sequence component of the input voltage, to be fed into the SRF-PLL for tracking of its phase angle. Compared with other traditional PLL topologies, this Adaptive PLL shows superior immunity to voltage distortions, and also has a faster dynamic performance. The thesis presents a comparative analysis of the performance of the traditional SRF-PLL with the Adaptive PLL in a VSC control system, and its impact on stability for VSCs connected to weak ac systems (up to SCR=1.3).

In this work, a programmable frequency divider suitable for millimeter wave phase-lock loops is presented. The frequency divider has been implemented in a 90 nm standard CMOS technology. To the extent of maximizing the operative input frequency, the higher frequency digital blocks of the frequency divider have been realized using dynamic precharge-evaluation logic. Moreover, a non-conventional method to implement non-power-of-2 division ratios has been used for the higher frequency divider stages (input stages).

Thesis (M.App.Sc.) - Carleton University, 2002. / Includes bibliographical references (p. 215-223). Also available in electronic format on the Internet.

Thesis (M. App. Sc.)--Carleton University, 2003. / Includes bibliographical references (p. 140-143). Also available in electronic format on the Internet.

Thesis (M. App. Sc.)--Carleton University, 2003. / Includes bibliographical references (p. 94-96). Also available in electronic format on the Internet.