Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.

With the move of the broadband cellular network towards 5G taking off and the preparatory work on 6G and beyond starting, the need for low-complexity, low-power, and high-performance frequency synthesis using Phase-Locked Loop (PLL)s increases. As we get deeper into the mm-wave frequencies and push towards frequencies in the order of 50-70 GHz design challenges with existing PLL architectures, such as limited technology scaling and limited in-band noise performance become more apparent. Other designs have tried overcoming these problems, for example by using single-bit phase detection at the cost of increased complexity when trying to control the bandwidth, or designing the loop with lower bandwidth to suppress in-band noise at the cost of requiring a lower noise and thus more power hungry oscillator. This thesis proposes a new Phase-locked loop architecture implemented in a 22nm node to combat these issues, utilizing a Pulse-Shrinking Time-To-Digital Converter (PS-TDC) offering sub-pico-second resolution with minimal power consumption in lock. The results found in this thesis have shown the viability of such a design, offering good in-band performance, allowing for wide bandwidth, and the use of a cheaper low-power Digital-Controlled Oscillator (DCO). The PS-TDC architecture combined with control logic implemented in this project can drastically decrease power consumption in lock while being able to compensate for process variations to optimize jitter performance. Additionally, by utilizing a Phase-Frequency Detector (PFD) and gear-shifting logic it has been shown that robust and fast locking can be achieved. / Med övergången till 5G i mobila bredbandsnätverk och förberedelserna för 6G på gång ökar behovet av lågkomplexa, lågeffekts- och högpresterande frekvenssyntes. När vi beger oss djupare in i millimetervågsfrekvenserna och strävar efter frekvenser uppemot 50-70 GHz blir designutmaningar med befintliga faslåsta loopar, såsom begränsad teknologiskalning och dålig prestanda för inband-brus, alltmer tydliga. Andra designer har försökt att övervinna dessa problem genom att till exempel använda enbitars fasdetektion till priset av ökad komplexitet vid styrning av systemets bandbredd, eller genom att designa loopen med lägre bandbredd för att vidare dämpa inband-brus, vilket kommer till priset av en oscillator med lägre brus och därmed högre effektförbrukning. Denna avhandling föreslår en ny arkitektur för faslåsta loopar för att överkomma dessa problem genom att använda en pulskrympande tids-till-digital omvandlare som erbjuder sub-pikosekunds upplösning med minimal effektförbrukning när frekvensen är låst. Resultaten som presenteras i denna avhandling har visat att en sådan design är möjlig, med god in-band prestanda, möjlighet till hög bandbredd och därmed användning av en billigare lågeffekt DCO. Den pulsskalande TDC-arkitekturen i kombination med kontrolllogik implementerad i detta projekt kan dramatiskt minska effektförbrukningen när frekvensen är låst, samtidigt som den kan kompensera för processvariationer för att optimera jitterprestanda. Sist har det visats att en robust och snabb låsning av frekvensen kan uppnås genom att använda en PFD.

Le projet HODISS dans le cadre duquel s'effectue nos travaux adresse la problématique de la synchronisation globale des systèmes complexes sur puce (System-on-Chip ou SOCs, par exemple un multiprocesseur monolithique). Les approches classiques de distribution d'horloges étant devenues de plus en plus obsolètes à cause de l'augmentation de la fréquence d'horloge, l'accroissement des temps de propagation, l'accroissement de la complexité des circuits et les incertitudes de fabrication, les concepteurs s’intéressent (pour contourner ces difficultés) à d'autres techniques basées entre autres sur les oscillateurs distribués. La difficulté majeure de cette dernière approche réside dans la capacité d’assurer le synchronisme global du système. Nous proposons un système d'horlogerie distribuée basé sur un réseau d’oscillateurs couplés en phase. Pour synchroniser ces oscillateurs, chacun d'eux est en fait une boucle à verrouillage de phase qui permet ainsi d'assurer un couplage en phase avec les oscillateurs des zones voisines. Nous analysons la stabilité de l'état synchrone dans des réseaux cartésiens identiques de boucles à verrouillage de phase entièrement numériques (ADPLLs). Sous certaines conditions, on montre que l'ensemble du réseau peut synchroniser à la fois en phase et en fréquence. Un aspect majeur de cette étude réside dans le fait que, en l'absence d'une horloge de référence absolue, le filtre de boucle dans chaque ADPLL est piloté par les fronts montants irréguliers de l'oscillateur local et, par conséquent, n'est pas régi par les mêmes équations d'état selon que l'horloge locale est avancée ou retardée par rapport au signal considéré comme référence. Sous des hypothèses simples, ces réseaux d'ADPLLs dits "auto-échantillonnés" peuvent être décrits comme des systèmes linéaires par morceaux dont la stabilité est notoirement difficile à établir. L'une des principales contributions que nous présentons est la définition de règles de conception simples qui doivent être satisfaites sur les coefficients de chaque filtre de boucle afin d'obtenir une synchronisation dans un réseau cartésien de taille quelconque. Les simulations transitoires indiquent que cette condition nécessaire de synchronisation peut également être suffisante pour une classe particulière d'ADPLLs "auto-échantillonnés". / The HODISS project, context in which this work is achieved, addresses the problem of global synchronization of complex systems-on-chip (SOCs, such as a monolithic multiprocessor). Since the traditional approaches of clock distribution are less used due to the increase of the clock frequency, increased delay, increased circuit complexity and uncertainties of manufacture, designers are interested (to circumvent these difficulties) to other techniques based among others on distributed synchronous clocks. The main difficulty of this latter approach is the ability to ensure the overall system synchronization. We propose a clock distribution system based on a network of phase-coupled oscillators. To synchronize these oscillators, each is in fact a phase-locked loop which allows to ensure a phase coupling with the nearest neighboring oscillators. We analyze the stability of the synchronized state in Cartesian networks of identical all-digital phase-locked loops (ADPLLs). Under certain conditions, we show that the entire network may synchronize both in phase and frequency. A key aspect of this study lies in the fact that, in the absence of an absolute reference clock, the loop-filter in each ADPLL is operated on the irregular rising edges of the local oscillator and consequently, does not use the same operands depending on whether the local clock is leading or lagging with respect to the signal considered as reference. Under simple assumptions, these networks of so-called “self-sampled” all-digital phase-locked-loops (SS-ADPLLs) can be described as piecewise-linear systems, the stability of which is notoriously difficult to establish. One of the main contributions presented here is the definition of simple design rules that must be satisfied by the coefficients of each loop-filter in order to achieve synchronization in a Cartesian network of arbitrary size. Transient simulations indicate that this necessary synchronization condition may also be sufficient for a specific class of SS-ADPLLs.

Ultra narrow-band filters and the use of two loops in a cascade configuration dominate current clock conditioners based on phase-locked-loop (PLL) schemes. Since a PLL exhibits a low-pass transfer function with respect to the reference clock, the noise performance at very close-to-carrier offset frequencies is still determined by the input signal. Although better cleaning can be achieved with extremely narrow loops, an ultra low cut-off frequency could not be selected since the stability of the configuration deteriorates as the filter bandwidth is reduced. This fact suggests that a full-spectrum clock conditioning is not possible using traditional PLL architectures, and an alternative scheme is necessary to attenuate the very-close-to-carrier phase noise (PN). In addition, ultra-narrow loop filters can compromise on-chip integration because of the large size capacitors needed when chosen as passive. Input signal attenuation with relaxed bandwidth requirements becomes the main aspect that a comprehensive clock cleaner must address to effectively regenerate a reference signal. This dissertation describes the Band-Reject Nested-PLL (BRN-PLL) scheme, a modified PLL-based architecture that provides an effective signal cleaning procedure by introducing a notch in the input transfer function through inner and outer loops and a high-pass filter (HPF). This modified response attenuates the reference-signal PN and reduces the size of the loop-filter capacitors substantially. Ultra narrow loops are no longer required because the notch size is related to the system bandwidth. The associated transfer function for the constitutive blocks (phase detectors and local oscillators) show that the output close-to-carrier and far-from-carrier PN sections are mainly dominated by the noise from the inner-PLL phase detector (PD) and local oscillator (LO) located in the outer loop, respectively. The inner-PLL PD transfer function maintains a low-pass characteristic with a passband gain inversely proportional to the PD gain becoming the main contribution around the carrier signal. On the other hand, the PN around the transition frequency is determined mainly by the reference and the inner-PLL LO. Their noise contributions to the output will depend on the associated passband local maxima, which is located at the BRN-PLL transition frequency. Hence, in this region, the inner-PLL LO is selected so that its effect can be held below that of the outer-PLL PD. The BRN-PLL can use a high-Q MEMS-based VCO to further improve the transition region of the output PN profile and an LC-VCO as outer-PLL LO to reduce the noise floor of the output signal. In particular, two tuning mechanisms are explored for the MEMS-VCO: series tuning using varactors and phase shifting of a resonator operating in nonlinear regime. Both schemes are implemented to generate a tunable oscillator with no PN-performance degradation.

La thèse a pour but de développer des algorithmes robustes de poursuite de phase multifréquence en environnement dégradé. L’objectif est d’élaborer de nouvelles structures pouvant opérer à des niveaux de rapport signal à bruit inférieurs aux limites des algorithmes actuellement implémentés dans des récepteurs grand public. Les problèmes de robustesse des algorithmes d’estimation de phase étant en grande partie causés par le phénomène de sauts de cycle, les différents axes de recherche se sont focalisés sur des nouvelles approches de développement de phase au sein des structures de poursuite. Pour ce faire, deux approches ont été étudiées et testées. Dans un premier temps, deux structures de poursuite monofréquence basées sur une DPLL conventionnelle ont été développées. Ces structures disposent d’un système externe de développement de phase visant à prédire et pré-compenser la sortie du discriminateur grâce à l’analyse des sorties du discriminateur ou des sorties du filtre de boucle. La réduction de la dynamique à estimer va alors permettre de réduire l’apparition des sauts de cycle se produisant au niveau du discriminateur. Par la suite, ce système de développement de phase a été adapté à la poursuite de phase multifréquence. Grâce à l’exploitation de la diversité en fréquence offerte par les signaux de navigation (i.e., de la proportionnalité des fréquences Doppler), il a été possible de mettre en place une étape de fusion de données qui a permis d’améliorer la précision de la prédiction de la sortie du discriminateur et donc d’améliorer la robustesse de la structure. Dans un second temps, les travaux de recherche se son taxés sur une nouvelle approche de poursuite de phase et de correction du phénomène de sauts de cycle basée sur une technique de filtrage Bayésien variationnel. Toujours en exploitant la diversité en fréquence des signaux de navigation, cette méthode suppose un modèle de dynamique de phase Markovien qui va imposer une certaine continuité de l’estimation et va permettre de fournir une estimation de phase développée. / This thesis aims at introducing multifrequency phase tracking algorithms operating in low C/N0environment. The objective is to develop new structures whose tracking limits are lower than thatof current algorithms used in mass market receivers. Phase tracking suffers from a lack of robustnessdue to the cycle slip phenomenon. Works have thus been focused on elaborating new phaseunwrapping systems. To do so, two different tracking approaches were studied. First, we have developed new monofrequency tracking loops based on a conventional DPLL. These structures aimat predicting the discriminator output by analyzing, thanks to a polynomial model, the last outputsamples of either the discriminator or the loop filter. Once the discriminator output is predicted,the estimated value is pre-compensated so that the phase dynamics to be tracked is reduced aswell as the cycle slip rate. Then, the unwrapping structure analyzing the loop filter outputs hasbeen extended to multifrequency signals. Using a data fusion step, the new multifrequency structuretakes advantage of the frequency diversity of a GNSS signal (i.e., proportionality of Dopplerfrequencies) to improve the tracking performances. Secondly, studies have been focused on developing a new multifrequency tracking algorithm using variational Bayesian filtering technique.This tracking method, which also uses the GNSS frequency diversity, assumes a Markovian phasedynamics that enforces the smoothness of the phase estimation and unwraps it.

Renewable energy sources normally require power converters to convert their energy into standardized regulated ac output. The motivation for this thesis is to design and control power converters for renewable energy systems to ensure very good power quality, efficiency and reliability. The renewable energy sources considered are low voltage dc sources such as photovoltaic (PV) modules. Two transformer-isolated power circuit topologies with input voltage of less than 50V are designed and developed for low and medium power applications. Various design and control issues of these converters are identified and new solutions are proposed. For low power rating of a few hundred watts, a line-frequency transformer interfaced inverter is developed. In the grid connected operation, it is observed that this topology injects considerable lower order odd and even harmonics in the grid current. The reasons for this are identified. A new current control method using adaptive harmonic compensation technique and a proportional-resonant-integral (PRI) controller is proposed. The proposed current controller is designed to ensure that the grid current harmonics are within the limits set by the IEEE 1547-2003 standard. Phase-locked loops (PLLs) are used for grid synchronization of power converters in grid-tied operation and for closed-loop control reference generation. Analysis and design of synchronous reference frame PLL (SRF-PLL) and second-order generalized integrator (SOGI) based PLLs considering unit vector distortion under the possible non-ideal grid conditions of harmonics, unbalance, dc offsets and frequency deviations are proposed and validated. Both SRF-PLL and SOGI-PLL are low-complexity PLLs. The proposed designs achieve fastest settling time for these PLLs for a given worst-case input condition. The harmonic distortion and dc offsets in the resulting unit vectors are limited to be well within the limits set by the IEEE 1547-2003 standard. The proposed designs can be used to achieve very good performance using conventional low-complexity PLLs without the requirement of advanced PLLs which can be computationally intensive. A high-frequency (HF) transformer interfaced ac link inverter with a lossless snubber is developed medium power level in the order of few kilowatts. The HF transformer makes the topology compact and economical compared to an equally rated line frequency transformer. A new synchronized modulation method is proposed to suppress the possible over-voltages due to current commutation in the leakage inductance of the HF transformer. The effect of circuit non-ideality of turn-on delay time is analyzed. The proposed modulation mitigates the problem of spurious turn-on that can occur due to the turn-on delay time. The HF inverter, rectifier and snubber devices have soft switching with this modulation. A new reliable start-up method is proposed for this inverter topology without any additional start- up circuitry. This solves the problems of over-voltages and inrush currents during start-up. The overall research work reported in the thesis shows that it is possible to have compact, reliable and high performance power converters for renewable energy conversion systems. It is also shown that high control performance and power quality can be achieved using the proposed control techniques of low implementation complexity.

Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014

El objetivo de este trabajo es el desarrollo de técnicas para la simulación y optimización del diseño de circuitos osciladores y lazos de enganche en fase de microondas. La intención de estas técnicas es que puedan ser utilizadas por el diseñador para optimizar las prestaciones de este tipo de circuitos durante la etapa de diseño. Por este motivo, se ha intentado que en todo momento las técnicas puedan ser utilizadas en combinación con un programa comercial de simulación de circuitos de microondas.En el caso de los circuitos osciladores, inicialmente se han optimizado sus prestaciones cuando se utilizan como osciladores controlados por tensión. De esta forma, se han desarrollado una serie de técnicas que, en combinación con simulaciones en un programa comercial, permiten la linealización y extensión de la característica tensión-frecuencia. Mediante una técnica de control de estabilidad, se ha optimizado la respuesta dinámica del oscilador ante entradas variantes en el tiempo. En concreto, se ha aumentado la rapidez de respuesta eliminando transitorios lentos oscilantes que distorsionan la señal de salida deseada. Esta técnica se ha aplicado al caso particular de osciladores controlados por tensión utilizados para generar señales chirp, como puede ser en radares Frequency Modulated Continuos Wave (FMCW). Se ha analizado también el fenómeno del "injection-pulling", en el que una señal interferente desplaza la frecuencia de oscilación. Para ello, se ha desarrollado una formulación tipo transitorio de envolvente cuyos coeficientes pueden ser identificados mediante simulaciones de balance armónico en un simulador comercial. La técnica permite incrementar la robustez del circuito oscilador ante estas señales interferentes. Dados los problemas observados en el simulador comercial para simular la característica de ruido de fase en osciladores con estructuras acopladas, se ha desarrollado una técnica de simulación de ruido de fase que solventa estos problemas. La técnica obtiene la característica de ruido de fase a través de simulaciones de transitorio de envolvente en combinación con el uso de generadores auxiliares. Estas simulaciones pueden realizarse sin problemas usando un simulador comercial. Los resultados de todas las técnicas han sido corroborados mediante medidas en varios tipos de osciladores de microondas. Finalmente, se ha realizado un estudio preliminar para combinar el uso de series de Volterra con la técnica de transitorio de envolvente para la simulación de la respuesta transitoria de los osciladores.En el caso de los lazos de enganche en fase, se ha desarrollado un programa propio que realiza un análisis no lineal de lazos acoplados o "Coupled Phase-Locked Loops" (CPLL). Estos sistemas son utilizados en aplicaciones tales como en control de apuntamiento de antenas "phased-array". El programa, basado en una formulación tempo-frecuencial del sistema, permite la obtención de los rangos de operación del CPLL mediante una caracterización no lineal de los elementos que componen el lazo. Se delimitan los rangos de histéresis, y se analiza la variación de estos rangos en función de los parámetros del sistema. Se analiza la estabilidad de las soluciones estacionarias, teniendo en cuenta parámetros tales como el retardo del lazo. Mediante el control de la estabilidad y un análisis de tipo transitorio de envolvente, se optimiza la rapidez del sistema en el seguimiento de entradas moduladas. Finalmente, se analiza el ruido de fase, separando la perturbación en fase en distintas componentes. Esta separación permite clarificar el efecto del ruido en el control de apuntamiento de un array de antenas. Las predicciones de las técnicas han sido validadas mediante medidas en un sistema CPLL a 2 GHz. / The objective of this work is the development of techniques for the simulation and optimization of the design of microwave oscillator circuits and phase-locked loops. The intention of these techniques is that they can be used by the designer to optimize the features of these kinds of circuits during the design stage. For this reason, a lot of effort has been put along this thesis to ensure that the techniques can be used in combination with commercial microwave circuit simulators.In the case of the oscillator circuits, initially, their features have been optimized when used as voltage controlled oscillators (VCO). In this way, different techniques are proposed for the computer aided design of these circuits. The first technique allows setting the operation frequency band for specific values of the tuning voltage. The second technique imposes a linear frequency-voltage characteristic with the aid of an auxiliary generator. To follow this characteristic, the circuit is solved in terms of an ideal capacitance, synthesized, at a later stage, with the tuning varactor embedded in a linear network. In the third technique, the oscillator response to a sawtooth input, used to generate a chirp signal, is improved, eliminating spurious frequencies, not observable in steady state. To illustrate the techniques, a VCO operating in the C-band has been optimized and used to generate a chirp signal with low nonlinear frequency distortion. The injection-pulling phenomenon in oscillator circuits has been also analyzed. Injection pulling by interference signals is an undesired phenomenon in front-end oscillators, which causes a shift of the oscillation frequency and degrades the output spectrum. A semi-analytical formulation for the insightful analysis of injection-pulling phenomena in the presence of a modulated carrier or chirp signal is presented. The formulation enables an efficient analysis of interference problems difficult to simulate with harmonic balance or standard envelope transient. It allows the modification of the original design in order to reduce the injection pulling to the desired levels. The techniques have been applied to an oscillator at 6 GHz. Considering the problems found in commercial software to simulate the phase noise characteristic of coupled oscillator topologies, a numerical technique for the determination of the phase-noise spectrum of free-running oscillators is presented. The technique is based on envelope transient and can be applied to any commercial simulator on which this analysis method is available. The main advantage of the technique is that it allows simulating the near carrier phase noise spectrum, including possible resonances. The elements providing the oscillator phase-noise spectrum are obtained from envelope-transient simulations of low-computational cost. Comparisons are performed between the presented technique and other existing techniques, such as the carrier modulation approach. The technique has been successfully tested on the simulation of the near carrier phase noise spectrum of an oscillator circuit at 6.3 GHz. Finally, a preliminary study has been carried out to combine the use of Volterra series with the envelope transient technique for the simulation of oscillator transients.Regarding the phase-locked loops, in this thesis, harmonic-balance (HB) and envelope-transient formulations of coupled phase-locked loops (CPLLs) are presented. The CPLL has the added difficulty of its autonomous behavior since no reference oscillator is present. The new formulation takes into account the autonomy of the system, introducing a special set of state variables, which depend on the autonomous frequencies. The hysteresis phenomenon in CPLLs is analyzed in detail, efficiently obtaining the pull-in and hold-in ranges through HB. The pole analysis of the perturbed HB system enables an accurate prediction of instabilities and resonances. Due to the CPLL autonomy, there exists an inherent noise accumulation effect. This effect is taken into account, analyzing the perturbation in terms of accumulation and deviation components. The envelope formulation allows simulating the CPLL behavior in presence of modulation signals. The influence of the stability of the steady-state solution on the modulated signals is investigated. The simulation results have been successfully compared with the measurements in a manufactured CPLL system at 2 GHz.

L'Electrogravimetria AC empra una microbalança de quars electroquímica (EQCM) en règim dinàmic. En l'EQCM un dels elèctrodes d'or depositats sobre el cristall és recobert amb una fina pelolícula d'un polímer electroactiv i és emprat com a elèctrode de treball (WE) dins d'una celola electroquímica. Les variacions de la freqüència de ressonància de la microbalança de quars (QCM) permeten obtindre la resposta massa associada amb la transferència de càrrega que es dóna en la interfície polímer-electròlit. L'Electrogravimetria AC va ser proposta a fi de caracteritzar i separadament identificar el moviment dels ions i el solvent en la interfície polímer-electròlit. En esta tècnica s'analitza en el domine de la freqüència la resposta de massa davant de xicotetes pertorbacions de voltatge gràcies a l'ocupació de la microbalança de quars en règim dinàmic. Per a este propòsit s'aplica una xicoteta pertorbació sinusoidal superposada a una tensió contínua, entre l'elèctrode de referència i l'elèctrode de treball de la celola. Posteriorment, es pot dibuixar la funció de transferència electrogravimètrica (EGTF), definida esta com la raó (?m/?E) entre l'amplitud dels canvis de massa induïts (?m) i l'amplitud de la pertorbació sinusoïdal aplicada (?E). Esta funció de transferència se dibuixa en un pla complex per a cada una de les freqüències de la senyal de pertorbació. Les distintes espècies iònicas involucrades són identificades en el pla complex per mitjà de bucles característics sempre que els bucles no se superposen. Per mitjà d'esta tesi doctoral es proposa un nou sistema de conversió de freqüència-tensió basat en un doble ajust de freqüència implementat amb un PLL mesclant elements analògics i digitals (AD PLL). Els resultats trobats tant en la caracterització electrònica del dispositiu com en la fase experimental proven la fiabilitat del sistema per als mesuraments realitzats en la tècnica d'Electrogravimetria AC. / Torres Villa, RA. (2007). Instrumental techniques for improving the measurements based on Quartz Crystal Microbalances (Técnicas instrumentales para mejorar las mediciones con microbalanzas de cuarzo) [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/17323 / Palancia