Power supply noise has become a critical issue for low power and high performance circuit design in recent years. The rapid scaling of the CMOS process has pushed the limit further and further in building low-cost and increasingly complex digital VLSI systems. Continued technology scaling has contributed to significant improvements in performance, increases in transistor density, and reductions in power consumption. However, smaller feature sizes, higher operation frequencies, and supply voltage reduction make current and future VLSI systems more vulnerable to power supply noise. Therefore, there is a strong demand for strategies to prevent problems caused by power supply noise. Design challenges exist in different design phases to reduce power supply noise. In terms of physical design, careful power distribution design is required, since it directly determines the quality of power stability and the timing integrity. In addition, power management, such as switching mode of the power gating technique, is another major challenge during the circuit design phase. A bad power gating switching strategy may draw an excessive rush current and slow down other active circuitry. After the circuit is implemented, another critical design challenge is to estimate power supply noise. Designers need to be aware of the voltage drop in order to enhance the power distribution network without wasting unnecessary design resources. However, estimating power supply noise is usually difficult, especially finding the circuit activity which induces the maximum supply noise. Blind search may be very time consuming and not effective. At post-silicon test, detecting power supply noise within a chip is also challenging. The visibility of supply noise is low since there is no trivial method to measure it. However, the supply noise measurement result on silicon is critical to debug and to characterize the chip. This dissertation focuses on novel circuit designs and design methodologies to prevent problems resulted from power supply noise in different design phases. First, a supply noise estimation methodology is developed. This methodology systematically searches the circuit activity inducing the maximum voltage drop. Meanwhile, once the circuit activity is found, it is validated through instruction execution. Therefore, the estimated voltage drop is a realistic estimation close to the real phenomenon. Simulation results show that this technique is able to find the circuit activity more efficiently and effectively compared to random simulation. Second, two on-chip power supply noise detectors are designed to improve the visibility of voltage drop during test phase. The first detector facilitates insertion of numerous detectors when there is a need for additional test points, such as a fine-grained power gating design or a circuit with multiple power domains. It focuses on minimizing the area consumption of the existing detector. This detector significantly reduces the area consumption compared to the conventional approach without losing accuracy due to the area minimization. The major goal of designing the second on-chip detector is to achieve self-calibration under process and temperature variations. Simulation and silicon measurement results demonstrate the capability of self-calibration regardless these variations. Lastly, a robust power gating reactivation technique is designed. This reactivation scheme utilizes the on-chip detector presented in this dissertation to monitor power supply noise in real time. It takes a dynamic approach to control the wakeup sequence according to the ambient voltage level. Simulation results demonstrate the ability to prevent the excessive voltage drop while the ambient active circuitry induces a high voltage drop during the wakeup phase. As a result, the fixed design resource, which is used to prevent the voltage emergency, can potentially be reduced by utilizing the dynamic reactivation scheme. / text

Testing integrated circuits to verify their operating frequency, known as delay testing, is essential to achieve acceptable product quality. The high cost of functional testing has driven the industry to automatically-generated structural tests, applied by low-cost testers taking advantage of design-for-test (DFT) circuitry on the chip. Traditional at-speed functional testing of digital circuits is increasingly challenged by new defect types and the high cost of functional test development. This research addressed the problems of accurate delay testing in DSM circuits by targeting resistive open and short circuits, while taking into account manufacturing process variation, power dissipation and power supply noise. In this work, we developed a class of structural delay tests in which we extended traditional launch-on-capture delay testing to additional launch and capture cycles. We call these Pseudofunctional Tests (PFT). A test pattern is scanned into the circuit, and then multiple functional clock cycles are applied to it with at-speed launch and capture for the last two cycles. The circuit switching activity over an extended period allows the off-chip power supply noise transient to die down prior to the at-speed launch and capture, achieving better timing correlation with the functional mode of operation. In addition, we also proposed advanced compaction methodologies to compact the generated test patterns into a smaller test set in order to reduce the test application time. We modified our CodGen K longest paths per gate automatic test pattern generator to implement PFT pattern generation. Experimental results show that PFT test generation is practical in terms of test generation time.

Power has become an important design closure parameter in today’s ultra low submicron digital designs. The impact of the increase in power is multi-discipline to researchers ranging from power supply design, power converters or voltage regulators design, system, board and package thermal analysis, power grid design and signal integrity analysis to minimizing power itself. This work focuses on challenges arising due to increase in power to power grid design and analysis. Challenges arising due to lower geometries and higher power are very well researched topics and there is still lot of scope to continue work. Traditionally, designs go through average IR drop analysis. Average IR drop analysis is highly dependent on current dissipation estimation. This work proposes a vector less probabilistic toggle estimation which is extension of one of the approaches proposed in literature. We have further used toggles computed using this approach to estimate power of ISCAS89 benchmark circuits. This provides insight into quality of toggles being generated. Power Estimation work is further extended to comprehend with various state of the art methodologies available i.e. spice based power estimation, logic simulation based power estimation, commercially available tool comparisons etc. We finally arrived at optimum flow recommendation which can be used as per design need and schedule. Today’s design complexity – high frequencies, high logic densities and multiple level clock and power gating - has forced design community to look beyond average IR drop. High rate of switching activities induce power supply fluctuations to cells in design which is known as instantaneous IR drop. However, there is no good analysis methodology in place to analyze this phenomenon. Ad hoc decoupling planning and on chip intrinsic decoupling capacitance helps to contain this noise but there is no guarantee. This work also applies average toggle computation approach to compute instantaneous IR drop analysis for designs. Instantaneous IR drop is also known as dynamic IR drop or power supply noise. We are proposing cell characterization methodology for standard cells. This data is used to build power grid model of the design. Finally, the power network is solved to compute instantaneous IR drop. Leakage Power Minimization has forced design teams to do complex power gating – multilevel MTCMOS usage in Power Grid. This puts additonal analysis challenge for Power Grid in terms of ON/OFF sequencing and noise injection due to it. This work explains the state of art here and highlights some of the issues and trade offs using MTCMOS logic. It further suggests a simple approach to quickly access the impact of MTCMOS gates in Power Grid in terms of peak currents and IR drop. Alternatively, the approach suggested also helps in MTCMOS gate optimization. Early leakage optimization overhead can be computed using this approach.

Power supply noise, which is the variation in the supply voltage across the on-die supply terminals of VLSI circuits, is a serious performance degrader in digital circuits and mixed analog-digital circuits. In digital VLSI systems, power supply noise causes timing errors such as delays, jitter, and false switching. In microprocessors, power supply noise reduces the maximum operating frequency (FMAX) of the CPU. In mixed analog-digital circuits, power supply noise manifests as the substrate noise and impairs the performance of the analog portion. The decrease in the available noise margin with the decrease in the feature size of transistors in CMOS systems makes the power supply noise a very serious issue, and demands new methods to reduce the power supply noise in sub-micron CMOS systems. In this thesis, we develop a new method to determine optimal time-delays between the switching of input/output (I/O) data buffers in digital VLSI systems that realizes maximum reduction of the power supply noise. We first discuss methods to characterize the distributed nature of the Power Delivery Network (PDN) in the frequency-domain. We then develop an analytical method to determine the optimal delays using the frequency-domain response of the PDN and the supply current spectrum of the buffer units. We explain the mechanism behind the cancellation of the power supply noise by the introduction of optimal buffer-to-buffer delays. We also develop a numerical method to determine the optimal delays and compare it with the analytical method. We illustrate the reduction in the power supply noise by applying the optimal time-delays determined using our methods to two examples of PDN. Our method has great potential to realize maximum reduction of power supply noise in digital VLSI circuits and substrate noise in mixed analog-digital VLSI circuits. Lower power supply noise translates into lower cost and improved performance of the circuit.

The objective of this dissertation is to derive a set of compact physical models addressing power integrity issues in high performance gigascale integration (GSI) systems and three-dimensional (3-D) systems. The aggressive scaling of CMOS integrated circuits makes the design of power distribution networks a serious challenge. This is because the supply current and clock frequency are increasing, which increases the power supply noise. The scaling of the supply voltage slowed down in recent years, but the logic on the integrated circuit (IC) still becomes more sensitive to any supply voltage change because of the decreasing clock cycle and therefore noise margin. Excessive power supply noise can lead to severe degradation of chip performance and even logic failure. Therefore, power supply noise modeling and power integrity validation are of great significance in GSI systems and 3-D systems. Compact physical models enable quick recognition of the power supply noise without doing dedicated simulations. In this dissertation, accurate and compact physical models for the power supply noise are derived for power hungry blocks, hot spots, 3-D chip stacks, and chip/package co-design. The impacts of noise on transmission line performance are also investigated using compact physical modeling schemes. The models can help designers gain sufficient physical insights into the complicated power delivery system and tradeoff various important chip and package design parameters during the early stages of design. The models are compared with commercial tools and display high accuracy.

Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.