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1 + 1 = ? : En fallstudie om tvålärarsystemets implementering och genomförande.Jakobsson, Linn, Lotz Lee, Alexandra January 2019 (has links)
Denna fallstudie tar sin utgångspunkt i flertalet artiklar där effekter av det så kalladetvålärarsystemet diskuteras. Begreppet tvålärarsystem har sin uppkomst i det amerikanska begreppet co-teaching, som i USA:s klassrum kopplas till en lärare och en specialpedagog. I denna fallstudie har vi valt att förkorta begreppet tvålärarsystem som TLS. Fallstudien grundar sig bland annat på två intervjuer med lärare som arbetar tillsammans i ett lärarpar på en grundskola i en större kommun i Sverige. För att lyckas med TLS är nyckeln att ha en god relation och kommunikation mellan lärarna i lärarparet. Fallstudien visar att svenska skolor och deras socioekonomiska läge är ett argument för att implementera TLS. TLS skapar förutsättningar för en mer individanpassad undervisning, till skillnad från om man arbetar som ensam lärare. Lärarna upplever därmed att de får mer tid till att stötta varje elev och detta gynnar elevernas lärande. TLS skall underlätta inkluderingsarbetet i skolan, det vill säga, elever med olika förutsättningar skall undervisas tillsammans och på så sätt få en mer likvärdig utbildning. Det fallstudiens resultat visar är dock att lärarparen ibland väljer att dela upp klassen i mindre grupper efter kunskapsnivå och genom att göra detta motverkar de inkluderingsarbetet. Följande forskningsfrågor har besvarats: Vilka var argumenten för att införa TLS på skolan?, Vilka är skillnaderna mot hur respektive lärare tidigare arbetat? och slutligen Hur upplever lärare TLS?
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A qualitative hermeneutic phenomenological study exploring lived experiences of re-imprisoned women transitioning to the communityLawton, Donna Blair 05 May 2016 (has links)
Women in the Province of Manitoba are discharged daily from provincial jails back to their communities after an interruption in their lives of anywhere from days to years. Many of these women cycle in and out of jail on a regular basis. This hermeneutic phenomenological study explored the daily lifeworlds of re-imprisoned women during their return to the community. Twelve women (nine Aboriginal, three Caucasian) were interviewed. Analysis of the study themes using van Manen’s existentials: temporality, spatiality, relationality, and corporeality revealed the complex multi-systemic issues that affect women’s lived experiences. The essence of the women’s accounts provides some insight into how the role of intergenerational, personal trauma and accumulated trauma impacted their lived experiences and continues to do so when they re-enter the community. The opportunities and options that women had to make positive life changes were obscured by insidious barriers and challenges impairing their ability to avoid re-imprisonment. / May 2016
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Hardware bidirectional real time motion estimator on a Xilinx Virtex II Pro FPGAIqbal, Rashid January 2006 (has links)
<p>This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. The architecture allows extremely controlled, macro level floor-planning with parameterized block size, image size, placement coordinates and data words length. The FPGA chip is part of the board that was developed at the Institute of Computer & Communication Networking Engineering, Technical University Braunschweig Germany, in collaboration with Grass Valley Germany in the FlexFilm research project. The goal of the project was to develop hardware and programming methodologies for real-time digital film image processing. Motion estimation core uses FlexWAFE reconfigurable architecture where FPGAs are configured using macro components that consist of weakly programmable address generation units and data stream processing units. Bidirectional motion estimation uses two cores of motion estimation engine (MeEngine) forming main data processing unit for backward and forward motion vectors. The building block of the core of motion estimation is an RPM-macro which represents one processing element and performs 10-bit difference, a comparison, and 19-bit accumulation on the input pixel streams. In order to maximize the throughput between elements, the processing element is replicated and precisely placed side-by-side by using four hierarchal levels, where each level is a very compact entity with its own local control and placement methodology. The achieved speed was further improved by regularly inserting pipeline stages in the processing chain.</p>
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Hardware bidirectional real time motion estimator on a Xilinx Virtex II Pro FPGAIqbal, Rashid January 2006 (has links)
This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. The architecture allows extremely controlled, macro level floor-planning with parameterized block size, image size, placement coordinates and data words length. The FPGA chip is part of the board that was developed at the Institute of Computer & Communication Networking Engineering, Technical University Braunschweig Germany, in collaboration with Grass Valley Germany in the FlexFilm research project. The goal of the project was to develop hardware and programming methodologies for real-time digital film image processing. Motion estimation core uses FlexWAFE reconfigurable architecture where FPGAs are configured using macro components that consist of weakly programmable address generation units and data stream processing units. Bidirectional motion estimation uses two cores of motion estimation engine (MeEngine) forming main data processing unit for backward and forward motion vectors. The building block of the core of motion estimation is an RPM-macro which represents one processing element and performs 10-bit difference, a comparison, and 19-bit accumulation on the input pixel streams. In order to maximize the throughput between elements, the processing element is replicated and precisely placed side-by-side by using four hierarchal levels, where each level is a very compact entity with its own local control and placement methodology. The achieved speed was further improved by regularly inserting pipeline stages in the processing chain.
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