La miniaturisation croissante des composants électroniques accroît considérablement la sensibilité des circuits intégrés face aux fautes transitoires de type (SEU) ou (SET). De ce fait, l'analyse de la sensibilité face aux ces fautes transitoires des circuits combinatoires et séquentiels est une tâche essentielle aujourd'hui. Les méthodes analytiques de calcul probabiliste de génération des impulsions SET ou des SEU et de propagation et transformation en erreur, publiées dans la littérateur jusqu'à ce jour, ne sont pas complets car un certain nombre de paramètres ne sont pas pris en compte. Dans cette thèse, nous proposons une méthodologie de simulation de fautes transitoires multi-niveaux qui permettra une évaluation plus rapide et en même temps précise. Cette méthodologie est en fait une collection des méthodes de simulations, une pour chaque niveau d'abstraction (niveau physique, niveau transistor, et niveau portes logiques). Au niveau physique, nous utilisons la simulation physique au niveau composants ou portes logiques élémentaires qui consiste en la caractérisation de chaque type de transistor d'une technologie donnée face aux SET en prenant en compte plusieurs paramètre (l'énergie ou le LET de la particule, l'angle d'incidence et la localisation de l'impact sur le composant, et les dimensions des transistors heurté par la particule). Suite à cette caractérisation, une famille de courbes de courants sera obtenue pour chaque transistor et un domaine de valeurs de l'amplitude et la durée de l'impulsion de courant sera établi. La transformation des impulsions de courants obtenus au niveau physique en impulsions de tension est réalisée à travers des simulations électriques en prenant en compte l'impédance de sortie de chaque porte. Une famille de courbes de tension transitoire sera aussi établie pour chaque porte. Un modèle d'impulsion logique sera défini pour ces impulsions qui sera ensuite utilisé dans des simulations numériques, qui sont beaucoup plus rapides, et qui sont utilisées finalement afin de pouvoir analyser la sensibilité face aux fautes transitoires de type SET et SEU d'un circuit complexe. Les résultats de cette analyse seront utilisés afin de réaliser une cartographie de sensibilité d'un circuit complexe qui nous permet de déterminer les zones les plus sensibles d'un circuit étudié et éventuellement de décider d'un durcissement ponctuel des portes sensibles.

Avec l'accroissement de la complexité des traitements effectués à bord des véhicules spatiaux et l'utilisation de circuits de plus en plus intégrés, le phénomène d'upset devient de plus en plus critique. En effet, ce phénomène se traduit par le basculement intempestif du contenu d'un point mémoire suite à l'impact d'une particule lourde dans des zones sensibles du circuit. Ses conséquences sont parfois fatales et peuvent conduire à la perte voire à la destruction de l'engin sur lequel il a eu lieu. Les réseaux de neurones artificiels constituent une nouvelle approche de traitement de l'information. Ils offrent des solutions compactes et rapides pour une large gamme de problèmes, en particulier ceux ayant des contraintes temps réel tel le cas de la plupart des applications spatiales actuelles. Ceci est davantage vrai avec l'utilisation des émulations et des implantations matérielle. Parmi les propriétés importantes des réseaux de neurones, on peut citer leur tolérance aux fautes qui mesure leur aptitude à exécuter la tâche qui leur est demandée en présence d'informations erronées et de maintenir leur capacité de calcul même si une partie du réseau est endommagée. L'objectif de cette thèse est d'étudier la tolérance aux fautes des réseaux de neurones face aux fautes de type upset et ceci en vue d'étudier la possibilité de leur utilisation, sous forme matérielle, dans un environnement radiatif tel que l'espace, le but étant de choisir parmi des circuits candidats, ceux qui sont acceptés (ou rejetés) pour des applications spatiales. Pour ce faire, plusieurs réseaux et plusieurs circuits ont été testés. Les expériences réalisées étaient de type simulation logicielle d'erreurs, injection matérielle de fautes et tests aux ions lourds. Les résultats obtenus montrent que les réseaux de neurones artificiels sont tolérants aux fautes de type upsets ce qui en fait un bon candidat pour les applications s'exécutant à bord des engins spatiaux.

The object of this research is to develop robust wire-line systems which demonstrate high performance while simultaneously consuming low power. The main focus of this work is the Clock and Data Recovery (CDR) system, which is the primary circuit of any modern wire-line transceiver. Different techniques starting from circuit-level to system-level have been investigated in this work to improve the performance of multi-gigabit CDRs. A 62 GHz bandwidth amplifier has been presented to address the need for a scalable amplifier for CDR needs. A new technique has been proposed to improve the radiation immunity of latches, to reduce the BER in CDRs occurring due to package radiations. An injection-lock based clock recovery method was investigated as an alternative to PLL based CDRs as they can be used for burst-mode wire-line communication. The investigation yielded the vulnerability of the method to jitter (false-locking and high jitter transfer), the attenuation of which is critical to commercial CDRs. A novel false-lock detector system has been proposed and demonstrated for the first time as a robust solution to the issue of false-locking of CDRs due to repetitive patterns. The implementation of the final CDR system required the use of an L-C tank VCO, the components of which are generic for all commercial CDRs. A new systematic layout technique for the VCO has been proposed and demonstrated in this work to substantially improve the layout area and the associated parasitics, approximately by 70 %. This new layout addresses a critical yet often neglected part of VCO design. Furthermore, a new concept has been proposed to optimize static dividers with respect to their power consumption and number of devices.

The high-radiation environment in space can lead to anomalies in normal satellite operation. A major cause of concern to spacecraft-designers is the single event upset (SEU). SEUs can result in deviations from expected component behavior and are capable of causing irreversible damage to hardware. In particular, Field Programmable Gate Arrays (FPGAs) are known to be highly susceptible to SEUs. Radiation-hardened versions of such devices are associated with an increase in power consumption and cost in addition to being technologically inferior when compared to contemporary commercial-off-the-shelf (COTS) parts. This thesis consequently aims at exploring the option of using COTS FPGAs in satellite payloads. A framework is developed, allowing the SEU susceptibility of such a device to be studied. SEU testing is carried out in a software-simulated fault environment using a set of Java classes called JBits. A radiation detector module, to measure the radiation backdrop of the device, is also envisioned as part of the final design implementation.

Radiation effects encountered in space or aviation environments can affect the configuration bits in Field Programmable Gate Arrays (FPGA) causing errors in FPGA output. One method of increasing FPGA reliability in radiation environments includes adding redundant logic to mask errors and allow time for repair. Despite the redundancy added with triple modular redundancy (TMR) and configuration scrubbing there exist some configuration bits that individually affect multiple TMR domains causing errors in FPGA output. A new tool called DeBit is introduced that identifies hardware resources associated with a single bit failure. This tool identifies a novel failure mode involving global routing resources and the failure mode is verified through a series of directed tests on global routing resources. Lastly, a mitigation strategy is proposed and tested on a single error in a triple modular redundancy (TMR) design.

Radiation effects encountered in space or aviation environments can affect the configuration bits in Field Programmable Gate Arrays (FPGA) causing errors in FPGA output. One method of increasing FPGA reliability in radiation environments includes adding redundant logic to mask errors and allow time for repair. Despite the redundancy added with triple modular redundancy (TMR) and configuration scrubbing there exist some configuration bits that individually affect multiple TMR domains causing errors in FPGA output. A new tool called DeBit is introduced that identifies hardware resources associated with a single bit failure. This tool identifies a novel failure mode involving global routing resources and the failure mode is verified through a series of directed tests on global routing resources. Lastly, a mitigation strategy is proposed and tested on a single error in a triple modular redundancy (TMR) design.

Methods for testing commercial off-the-shelf (COTS) digital devices at varying levels of complexity is presented and discussed as well as the results for testing a COTS SRAM, FRAM, and SoC using these methodologies in a pulsed dose rate environment at Little Mountain Test Facility (LMTF) and neutron testing at Los Alamos Neutron Science Center (LANSCE). Investigations at LMTF revealed a dependence in all three devices on the integrated dose of a single pulse of radiation, implying that the duration of radiation plays a significant role in the response. The test infrastructure necessary to dynamically access an FRAM at LMTF and time the access with the pulse of radiation allowed for the discovery of a new FRAM failure mode where an entire word of the FRAM becomes corrupted as well as selecting between two different failure modes based on the timing of the pulse. A novel component-based testing methodology for testing complicated SoCs is presented and used to report on the cross-sections of several components on the Xilinx MPSoC, including its DMA which has not previously been reported.

<p>This thesis proposes a new method to detect routing switch alterations on FPGAs in real-time. By sampling the circuit path at the source and destination, and comparing the samples, it is possible to find out if there has been a routing change in the circuit path. We compare and contrast this probing method with previously established techniques such as Cyclic Redundancy Checks, Built-in-self-tests, Triple Modular Redundancy, Duplication with Comparison, and redesigning the FPGA. The probe method finds the routing error in one clock cycle, using the pre-existing elements on the FPGA, while the FPGA is still operational. This method works on all FPGAs that use the Wilton style switchbox. An automated tool for probing the design circuit is presented in this thesis that applies the probe scheme on a circuit built on the Xilinx Virtex-4 FPGA.</p> / Master of Applied Science (MASc)

Le De regione et moribus Canadensium seu Barbarorum Novæ Franciæ a toujours été présenté comme un texte rédigé par le jésuite Joseph de Jouvency. Pourtant, une étude plus approfondie montre que certains éléments ne peuvent provenir ni d'un religieux, ni du XVIIIe siècle. On aurait plutôt à faire avec un auteur laïc du début du XVIIe siècle, qui a des informations de première main, puisqu'il est lui-même à Québec. Ce qui en fait un document précieux et un témoin privilégié de l’histoire du début de la Nouvelle-France, bien que traduit et retravaillé par des Jésuites. Jouvency, en l'insérant dans les Historiæ Societatis Jesu, l'a en effet censuré et a ajouté quelques passages au texte original. Quelle est l'opinion du véritable auteur, ce Français vivant à Québec, sur les « Barbares de Nouvelle-France » qu'il rencontre? Une étude du texte montre qu'il dépeint à la fois les bonnes et les mauvaises coutumes des tribus autochtones, nous renseignant ainsi sur l'état des indigènes peu après l'arrivée des premiers véritables colons de la Nouvelle-France. Une traduction française accompagne l'analyse du texte. / De regione et moribus Canadensium seu Barbarorum Novæ Franciæ is studied as if it has been written by Jesuit Father Joseph de Jouvency. That being said, a more thorough research indicates that this text does not originate from such a pious man, nor from someone that lived during the eighteenth century. Indeed, the real author behind this text would more likely be a French who is laic and lived in Quebec city during the early seventeenth century. This revelation makes the document unique, despite the Jesuit’s adaptation both in language and content. For instance, Father Jouvency, the editor of the De regione who inserted it in the Historiae Societatis Jesu, censured and added some informations to the original text. It now becomes crucial to investigate the real opinion of the French Canadian author about these ‘‘Savages’’ that he met ? Our study shows that he described both good and bad native Americans customs, unveiling their life just after the arrival of the first French settlers in Quebec city. A French translation of the latin text also accompanies our analysis.

Este trabalho tem como objetivo abordar uma das obras mais importantes do escritor francês Antonin Artaud, Le Théâtre et son double, explorando o universo artaudiano, a partir de conceitos, como a peste e a crueldade. O estudo procura abordar a proposta de Teatro da Crueldade e as críticas feitas por Artaud em relação aos espetáculos apresentados na França na década de 1930. Por meio de uma crítica ao chamado teatro psicológico, Artaud exalta um teatro constituído por diversas linguagens, não restrito à mera reprodução do texto. Sem a pretensão de abordar a extensa obra escrita por Artaud, a dissertação tem como objetivo tratar de aspectos revelantes dos conceitos tratados por Artaud, como a crueldade e a peste, tentando identificar em sua proposta de teatro, o desenvolvimento de conceitos ligados à psicanálise, como a pulsão de morte. Procuramos, ainda, discutir o processo de criação de Artaud, problematizando a figura do Pai em sua escrita e a chamada outra cena do inconsciente que seria aberta pelo teatro da crueldade. / The purpose of this research is to analyse one of the most important works of Antonin Artaud, The Theater and its double (Le Théâtre et son double), exploring his universe from concepts like the pest and cruelty. The study seeks to analyse the proposal of the Theatre of Cruelty and the criticisms made by Artaud in relation to theatrical performances presented in France in the 1930s. By making a critique of the psychological theater, Artaud ideates a theater consisted of different languages, not restricted to the simple reproduction of the text. Without attempting to address the extensive work by Artaud, the dissertation aims to analyse some aspects of important concepts created by Artaud, as the cruelty and the pest, trying to identify in its proposal for the theater, as well as the development of concepts related to psychoanalysis, like the death drive. We also aim to discuss the creation process of Artaud, by analyzing the figure of the Father in his writing and the so called \"other unconscious scene\" that would be opened by the theater of cruelty.