In the present work new methods were developed for preparation of novel nanosized and nanostructured ceramic materials. Ordered mesoporous silica SBA-15 was found to be useful as a hard template for the nanocasting of silicon carbide and allowed the preparation of high temperature stable mesoporous silicon carbide ceramics. Chemical vapor infiltration of SBA-15 with dimethyldichlorosilane at elevated temperatures yields SiC/SBA-15 nanocomposites. The subsequent HF treatment of those composites resulted in silica removal and preparation of mesoporous silicon carbide with surface areas between 410 and 830 m2g-1 and high mesopore volume (up to 0.9 cm3g-1). The pore size (between 3 and 7nm in diameter) and surface area of mesoporous silicon carbide were controlled by adjusting the infiltration conditions (time, atmosphere). The mesoporous silicon carbide prepared via this method showed high structural thermal stability at 1300 oC, exceeding that of the SBA-15 template. However, the ordering on the mesoscopic scale was low. Nevertheless, highly ordered mesoporous silicon carbide materials were obtained via polymer melt infiltration in SBA-15. The low molecular weight polycarbosilane used as a preceramic precursor was converted at 1300 oC to silicon carbide inside the SBA-15, and after subsequent silica removal by HF, a highly ordered mesoporous material was obtained. Ordered mesoporous silicon carbide prepared by the methods reported here, may be an interesting material as a support due to its high temperature stability, chemical inertness, high thermal conductivity and semiconductor properties. In contrast to the nanocasting approach, based on the complete pore filling, also a new in-situ procedure for the preparation of finely dispersed metal and metal oxide particles inside ordered mesoporous silica was developed. A swelling agent (toluene) was used to deliver a hydrophobic platinum precursor into the surfactant micelles before addition of silica source. Such an in-situ method resulted in very high platinum incorporation (80-100%), not achieved for any other in-situ preparation procedures. Additionally, the presence of platinum allowed to decrease the template removal temperatures. Moreover, the method was also extended to other metal or metal oxide/ordered mesoporous silica systems. This may be especially interesting for the preparation of ordered mesoporous materials with low melting points, where typically the structure collapses during the high temperature calcinations process. The in-situ synthesized V2O5/MCM-41 materials were used to prepare VN/MCM-41 composites via nitridation in ammonia at 800oC. This method allowed to prepare highly dispersed, X-ray amorphous vanadium nitride species, with high activity in the propane dehydrogenation. Compared to nitridation of supported vanadium oxide prepared via the ex-situ procedure, in-situ synthesized materials showed similar catalytic activity, in spite of having significantly lower vanadium loading. As an alternative for the preparation of supported nitride materials, a novel preparation procedure of bulk not supported nanocrystalline vanadium nitride with high surface area was presented. Instead of pure oxide powder (which was typically used in the preparation of high surface area vanadium nitride catalysts), a macroporous amine intercalated V2O5 was used as the starting material. The obtained nitride consisted of small crystallites and had a surface area up to 198 m2g-1. Moreover, this foam-derived VN showed significantly improved activity as a catalyst in propane dehydrogenation. This novel preparation method could also be extended to other systems such as ternary VMoxNy nitrides.

No description available.

Abstract: Micro­Raman Spectroscopy Investigation of Hard Coatings Diamond, silicon carbide, and boron nitride have attracted great interest in the last years, due to their excellent material properties. Especially the extreme hardness and the high thermal con­ ductivity of these materials favour them as protective layers. The very large hardness gave these materials, deposited as films on various substrates, their name: hard coatings. In contrast to di­ amond, silicon carbide and boron nitride can be n­ as well as p­doped, making them promising candidates for high speed and high temperature electronic applications. Contrarily to the materials mentioned above, carbon nitride was obtained in crystalline form just very recently. Up to now the deposited films mainly consist of amorphous or nanocrystalline, carbon­rich material. For all these material systems inelastic light scattering (Raman spectroscopy) has been already applied for the material properties investigation. However, these investigations usually were restricted to only one of the various Raman spectroscopy tools, described in this work: Incident laser light energy varia­ tion, temperature variation, utilizing the selection rules, measurements at varying sample positions, two­dimensional mappings and one­dimensional scans in the conventional plane­view and the addi­ tional cross­sectional sample geometry. In contrast to this, this work demonstrates the improvement of the information about the investigated material and/or the sample heterostructure obtained by using the combination of all the above mentioned techniques. In the case of the diamond material system, films deposited on silicon substrates were investigated and an interfacial graphitic layer of 2nm thickness was found by scanning across the interface, which was obscured in the conven­ tional plane­view sample geometry. Similar to this an ultra­thin top layer and buried intermixed regions were identified in the silicon carbide material system utilizing the cross­sectional sample geometry. In addition to this, the temperature and the incident laser light energy dependences for 5 SiC polytypes (3C, 4H, 6H, 15R, and 21R) were measured. A resonance enhancement for the 3C and the 21R polytype was found corresponding to their fundamental bandgaps at 2.46eV and ß2.8eV, respectively. For the other polytypes no resonance enhancement was found, due to their larger fundamental bandgap. In the boron nitride material system the spatial correlation model for Raman lineshape analysis was applied for the first time and the values of the asymmetric broad­ ening and the frequency downshift for decreasing crystal sizes were evaluated. This was measured for single crystals of different size and for films deposited on silicon substrates. The correlation lengths in the ten nanometer region found for the deposited films corroborate the nanocrystalline nature of these films. Additionally incident laser light energy was measured, revealing the 488.0nm (Ar + ) and 482.5nm (Kr + ) laser lines as the optimum laser lines for the boron nitride investigation. Furthermore the dependence of the phonon feature parameters was investigated depending on the incident laser light power. A maximum power of 5­10mW for the micro­Raman spectroscopy setup was found to avoid any laser light induced heating of the investigated material. Two­dimensional mappings of the deposited boron nitride films were performed to improve the information about the material system. In the case of carbon nitride for the first time distinct phonon features were measured in a wide spectral range contrarily to most of the other investigations, which usually show only broad bands.

Thesis (Ph.D.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

Silicon carbide (SiC) has higher breakdown field strength than silicon (Si), which enables thinner and more highly doped drift layers compared to Si. Consequently, the power losses can be reduced compared to Si-based power conversion systems. Moreover, SiC allows the power conversion systems to operate at high temperatures up to 250 oC. With such expectations, SiC is considered as the material of choice for modern power semiconductor devices for high efficiencies, high temperatures, and high power densities. Besides the material benefits, the typeof the power device also plays an important role in determining the system performance. Compared to the SiC metal-oxide semiconductor field-effect transistor (MOSFET) and bipolar junction transistor (BJT), the SiC junction field-effect transistor (JFET) is a very promising power switch, being a voltage-controlled device without oxide reliability issues. Its channel iscontrolled by a p-n junction. However, the present JFETs are not optimized yet with regard to on-state resistance, controllability of threshold voltage, and Miller capacitance. In this thesis, the state-of-the-art SiC JFETs are introduced with buried-grid (BG) technology.The buried grid is formed in the channel through epitaxial growth and etching processes. Through simulation studies, the new concepts of normally-on and -off BG JFETs with 1200 V blocking capability are investigated in terms of static and dynamic characteristics. Additionally, two case studies are performed in order to evaluate total losses on the system level. These investigations can be provided to a power circuit designer for fully exploiting the benefit of power devices. Additionally, they can serve as accurate device models and guidelines considering the switching performance. The BG concept utilized for JFETs has been also used for further development of SiC junctionbarrier Schottky (JBS) diodes. Especially, this design concept gives a great impact on high temperature operation due to efficient shielding of the Schottky interface from high electric fields. By means of simulations, the device structures with implanted and epitaxial p-grid formations, respectively, are compared regarding threshold voltage, blocking voltage, and maximum electric field at the Schottky interface. The results show that the device with an epitaxial grid can be more efficient at high temperatures than that with an implanted grid. To realize this concept, the device with implanted grid was optimized using simulations, fabricated and verified through experiments. The BG JBS diode clearly shows that the leakage current is four orders of magnitude lower than that of a pure Schottky diode at an operation temperature of 175 oC and 2 to 3 orders of magnitude lower than that of commercial JBS diodes. Finally, commercialized vertical trench JFETs are evaluated both in simulations andexperiments, while it is important to determine the limits of the existing JFETs and study their performance in parallel operation. Especially, the influence of uncertain parameters of the devices and the circuit configuration on the switching performance are determined through simulations and experiments. / Kiselkarbid (SiC) har en högre genombrottsfältstyrka än kisel, vilket möjliggör tunnare och mer högdopade driftområden jämfört med kisel. Följaktligen kan förlusterna reduceras jämfört med kiselbaserade omvandlarsystem. Dessutom tillåter SiC drift vid temperatures upp till 250 oC. Dessa utsikter gör att SiC anses vara halvledarmaterialet för moderna effekthalvledarkomponenter för hög verkningsgrad, hög temperature och hög kompakthet. Förutom materialegenskaperna är också komponenttypen avgörande för att bestämma systemets prestanda. Jämfört med SiC MOSFETen och bipolärtransistorn i SiC är SiC JFETen en mycket lovande component, eftersom den är spänningsstyrd och saknar tillförlitlighetsproblem med oxidskikt. Dess kanal styrs an en PNövergång. Emellertid är dagens JFETar inte optimerade med hänseende till on-state resistans, styrbarhet av tröskelspänning och Miller-kapacitans. I denna avhandling introduceras state-of-the-art SiC JFETar med buried-grid (BG) teknologi. Denna åstadkommes genom epitaxi och etsningsprocesser. Medelst simulering undersöks nya concept för normally-on och normally-off BG JFETar med blockspänningen 1200 V. Såvä statiska som dynamiska egenskper undersöks. Dessutom görs två fallstudier vad avser totalförluster på systemnivå. Dessa undersökningar kan vara värdefulla för en konstruktör för att till fullo utnyttja fördelarna av komponenterna. Dessutom kan resultaten från undersökningarna användas som komponentmodeller och anvisningar vad gäller switch-egenskaper. BG konceptet som använts för JFETar har också använts för vidareutveckling av så kallade JBS-dioder. Speciellt ger denna konstruktion stora fördelar vid höga temperature genom en effektiv skärmning av Schottkyövergången mot höga elektriska fält. Genom simuleringar har komponentstrukturer med implanterade och epitaxiella grids jämförst med hänseende till tröskelspänning, genombrottspänning och maximalt elektriskt fält vid Schottky-övergången. Resultaten visar att den epitaxiella varianten kan vara mer effektiv än den implanterade vid höga temperaturer. För att realisera detta concept optimerades en komponent med implanterat grid med hjälp av simuleringar. Denna component tillverkades sedan och verifierades genom experiment. BG JBS-dioden visar tydligt att läckströmmen är fyra storleksordningar lägre än för en ren Schottky-diod vid 175 oC, och två till tre storleksordningar lägre än för kommersiella JBS-dioder. Slutligen utvärderas kommersiella vertical trench-JFETar bade genom simuleringar och experiment, eftersom det är viktigt att bestämma gränserna för existerande JFETar och studera parallelkoppling. Speciellt studeras inverkan av obestämda parametrar och kretsens konfigurering på switchegenskaperna. Arbetet utförs bade genom simuleringar och experiment. / <p>QC 20150915</p>

R??sum?? : L???isolation thermique est essentielle dans de nombreux types de MEMS (micro-syst??mes ??lectro-m??caniques). Elle permet de r??duire la consommation d?????nergie, am??liorer leurs performances, ou encore isoler la zone chaude du reste du dispositif, ce qui est essentiel dans les syst??mes sur puce. Il existe quelques mat??riaux et techniques d???isolation pour les MEMS, mais ils sont limit??s. En effet, soit ils ne proposent pas un niveau d???isolation suffisant, sont trop fragiles, ou imposent des contraintes trop importantes sur la conception du dispositif et sont difficiles ?? int??grer. Une approche int??ressante pour l???isolation, d??montr??e dans la litt??rature, est de fabriquer des pores de taille nanom??trique dans le silicium par gravure ??lectrochimique. En nanostructurant le silicium ainsi, on peut diviser sa conductivit?? thermique par un facteur de 100 ?? 1000, le transformant en isolant thermique. Cette solution est id??ale pour l???int??gration dans les proc??d??s de fabrication existants des MEMS, car on garde le silicium qui est d??j?? utilis?? pour leur fabrication, mais en le nanostructurant localement, on le rend isolant l?? o?? on en a besoin. Par contre sa porosit?? cause des probl??mes : mauvaise r??sistance chimique, structure instable au-del?? de 400??C, et tenue m??canique r??duite. La facilit?? d???int??gration des semiconducteurs poreux est un atout majeur, nous visons donc de r??duire les d??savantages de ces mat??riaux afin de favoriser leur int??gration dans des dispositifs en silicium. Nous avons identifi?? deux approches pour atteindre cet objectif : i) am??liorer le Si poreux ou ii) d??velopper un nouveau mat??riau. La premi??re approche consiste ?? amorphiser le Si poreux en l???irradiant avec des ions ?? haute ??nergie (uranium, 110 MeV). Nous avons montr?? que l???amorphisation, m??me partielle, du Si poreux entra??ne une diminution de sa conductivit?? thermique, sans endommager sa structure poreuse. Cette technique r??duit sa conductivit?? thermique jusqu????? un facteur de trois, et peut ??tre combin??e avec une pr??-oxydation afin d???atteindre une r??duction d???un facteur cinq. Donc cette m??thode permet de r??duire la porosit?? du Si poreux, et d???att??nuer ainsi les probl??mes de fragilit?? m??canique caus??s par la porosit?? ??lev??e, tout en gardant un niveau d???isolation ??gal. La seconde approche est de d??velopper un nouveau mat??riau. Nous avons choisi le SiC poreux : le SiC massif a des propri??t??s physiques sup??rieures ?? celles du Si, et donc ?? priori le SiC poreux devrait conserver cette sup??riorit??. La fabrication du SiC poreux a d??j?? ??t?? d??montr??e dans la litt??rature, mais avec peu d?????tudes d??taill??es du proc??d??. Sa conductivit?? thermique et tenue m??canique n???ont pas ??t?? caract??ris??es, et sa tenue en temp??rature que de fa??on incompl??te. Nous avons men?? une ??tude syst??matique de la porosification du SiC en fonction de la concentration en HF et le courant. Nous avons impl??ment?? un banc de mesure de la conductivit?? thermique par la m??thode ?? 3 om??ga ?? et l???avons utilis?? pour mesurer la conductivit?? thermique du SiC poreux. Nous avons montr?? qu???elle est environ deux ordres de grandeur plus faible que celle du SiC massif. Nous avons aussi montr?? que le SiC poreux est r??sistant ?? tous les produits chimiques typiquement utilis??s en microfabrication sur silicium. D???apr??s nos r??sultats il est stable jusqu????? au moins 1000??C et nous avons obtenu des r??sultats qualitatifs encourageants quant ?? sa tenue m??canique. Nos r??sultats signifient donc que le SiC poreux est compatible avec la microfabrication, et peut ??tre int??gr?? dans les MEMS comme isolant thermique. // Abstract : Thermal insulation is essential in several types of MEMS (micro electro-mechanical systems). It can help reduce power consumption, improve performance, and can also isolate the hot area from the rest of the device, which is essential in a system-on-chip. A few materials and techniques currently exist for thermal insulation in MEMS, but these are limited. Indeed, either they don???t have provide a sufficient level of insulation, are too fragile, or restrict design of the device and are difficult to integrate. A potentially interesting technique for thermal insulation, which has been demonstrated in the literature, is to make nanometer-scale pores in silicon by electrochemical etching. By nanostructuring silicon in this way, its thermal conductivity is reduced by a factor of 100 to 1000, transforming it into a thermal insulator. This solution is ideal for integration in existing MEMS fabrication processes, as it is based on the silicon substrates which are already used for their fabrication. By locally nanostructuring these substrates, silicon is made insulating wherever necessary. However the porosity also causes problems : poor chemical resistance, an unstable structure above 400???C, and reduced mechanical properties. The ease of integration of porous semiconductors is a major advantage, so we aim to reduce the disadvantages of these materials in order to encourage their integration in silicon-based devices. We have pursued two approaches in order to reach this goal : i) improve porous Si, or ii) develop a new material. The first approach uses irradiation with high energy ions (100 MeV uranium) to amorphise porous Si. We have shown that amorphisation, even partial, of porous Si leads to a reduction of its thermal conductivity, without damaging its porous structure. This technique can reduce the thermal conductivity of porous Si by up to a factor of three, and can be combined with a pre-oxidation to achieve a five-fold reduction of thermal conductivity. Therefore, by using this method we can use porous Si layers with lower porosity, thus reducing the problems caused by the fragility of high-porosity layers, whilst keeping an equal level of thermal insulation. The second approach is to develop a new material. We have chosen porous SiC: bulk SiC has exceptional physical properties and is superior to bulk Si, so porous SiC should be superior to porous Si. Fabrication of porous SiC has been demonstrated in the literature, but detailed studies of the process are lacking. Its thermal conductivity and mechanical properties have never been measured and its high-temperature behaviour has only been partially characterised. We have carried out a systematic study of the effects of HF concentration and current on the porosification process. We have implemented a thermal conductivity measurement setup using the ???3 omega??? method and used it to measure the thermal conductivity of porous SiC. We have shown that it is about two orders of magnitude lower than that of bulk SiC. We have also shown that porous SiC is chemically inert in the most commonly used solutions for microfabrication. Our results show that porous SiC is stable up to at least 1000???C and we have obtained encouraging qualitative results regarding its mechanical properties. This means that porous SiC is compatible with microfabrication processes, and can be integrated in MEMS as a thermal insulation material.

R??sum?? : L???isolation thermique est essentielle dans de nombreux types de MEMS (micro-syst??mes ??lectro-m??caniques). Elle permet de r??duire la consommation d?????nergie, am??liorer leurs performances, ou encore isoler la zone chaude du reste du dispositif, ce qui est essentiel dans les syst??mes sur puce. Il existe quelques mat??riaux et techniques d???isolation pour les MEMS, mais ils sont limit??s. En effet, soit ils ne proposent pas un niveau d???isolation suffisant, sont trop fragiles, ou imposent des contraintes trop importantes sur la conception du dispositif et sont difficiles ?? int??grer. Une approche int??ressante pour l???isolation, d??montr??e dans la litt??rature, est de fabriquer des pores de taille nanom??trique dans le silicium par gravure ??lectrochimique. En nanostructurant le silicium ainsi, on peut diviser sa conductivit?? thermique par un facteur de 100 ?? 1000, le transformant en isolant thermique. Cette solution est id??ale pour l???int??gration dans les proc??d??s de fabrication existants des MEMS, car on garde le silicium qui est d??j?? utilis?? pour leur fabrication, mais en le nanostructurant localement, on le rend isolant l?? o?? on en a besoin. Par contre sa porosit?? cause des probl??mes : mauvaise r??sistance chimique, structure instable au-del?? de 400??C, et tenue m??canique r??duite. La facilit?? d???int??gration des semiconducteurs poreux est un atout majeur, nous visons donc de r??duire les d??savantages de ces mat??riaux afin de favoriser leur int??gration dans des dispositifs en silicium. Nous avons identifi?? deux approches pour atteindre cet objectif : i) am??liorer le Si poreux ou ii) d??velopper un nouveau mat??riau. La premi??re approche consiste ?? amorphiser le Si poreux en l???irradiant avec des ions ?? haute ??nergie (uranium, 110 MeV). Nous avons montr?? que l???amorphisation, m??me partielle, du Si poreux entra??ne une diminution de sa conductivit?? thermique, sans endommager sa structure poreuse. Cette technique r??duit sa conductivit?? thermique jusqu????? un facteur de trois, et peut ??tre combin??e avec une pr??-oxydation afin d???atteindre une r??duction d???un facteur cinq. Donc cette m??thode permet de r??duire la porosit?? du Si poreux, et d???att??nuer ainsi les probl??mes de fragilit?? m??canique caus??s par la porosit?? ??lev??e, tout en gardant un niveau d???isolation ??gal. La seconde approche est de d??velopper un nouveau mat??riau. Nous avons choisi le SiC poreux : le SiC massif a des propri??t??s physiques sup??rieures ?? celles du Si, et donc ?? priori le SiC poreux devrait conserver cette sup??riorit??. La fabrication du SiC poreux a d??j?? ??t?? d??montr??e dans la litt??rature, mais avec peu d?????tudes d??taill??es du proc??d??. Sa conductivit?? thermique et tenue m??canique n???ont pas ??t?? caract??ris??es, et sa tenue en temp??rature que de fa??on incompl??te. Nous avons men?? une ??tude syst??matique de la porosification du SiC en fonction de la concentration en HF et le courant. Nous avons impl??ment?? un banc de mesure de la conductivit?? thermique par la m??thode ?? 3 om??ga ?? et l???avons utilis?? pour mesurer la conductivit?? thermique du SiC poreux. Nous avons montr?? qu???elle est environ deux ordres de grandeur plus faible que celle du SiC massif. Nous avons aussi montr?? que le SiC poreux est r??sistant ?? tous les produits chimiques typiquement utilis??s en microfabrication sur silicium. D???apr??s nos r??sultats il est stable jusqu????? au moins 1000??C et nous avons obtenu des r??sultats qualitatifs encourageants quant ?? sa tenue m??canique. Nos r??sultats signifient donc que le SiC poreux est compatible avec la microfabrication, et peut ??tre int??gr?? dans les MEMS comme isolant thermique. // Abstract : Thermal insulation is essential in several types of MEMS (micro electro-mechanical systems). It can help reduce power consumption, improve performance, and can also isolate the hot area from the rest of the device, which is essential in a system-on-chip. A few materials and techniques currently exist for thermal insulation in MEMS, but these are limited. Indeed, either they don???t have provide a sufficient level of insulation, are too fragile, or restrict design of the device and are difficult to integrate. A potentially interesting technique for thermal insulation, which has been demonstrated in the literature, is to make nanometer-scale pores in silicon by electrochemical etching. By nanostructuring silicon in this way, its thermal conductivity is reduced by a factor of 100 to 1000, transforming it into a thermal insulator. This solution is ideal for integration in existing MEMS fabrication processes, as it is based on the silicon substrates which are already used for their fabrication. By locally nanostructuring these substrates, silicon is made insulating wherever necessary. However the porosity also causes problems : poor chemical resistance, an unstable structure above 400???C, and reduced mechanical properties. The ease of integration of porous semiconductors is a major advantage, so we aim to reduce the disadvantages of these materials in order to encourage their integration in silicon-based devices. We have pursued two approaches in order to reach this goal : i) improve porous Si, or ii) develop a new material. The first approach uses irradiation with high energy ions (100 MeV uranium) to amorphise porous Si. We have shown that amorphisation, even partial, of porous Si leads to a reduction of its thermal conductivity, without damaging its porous structure. This technique can reduce the thermal conductivity of porous Si by up to a factor of three, and can be combined with a pre-oxidation to achieve a five-fold reduction of thermal conductivity. Therefore, by using this method we can use porous Si layers with lower porosity, thus reducing the problems caused by the fragility of high-porosity layers, whilst keeping an equal level of thermal insulation. The second approach is to develop a new material. We have chosen porous SiC: bulk SiC has exceptional physical properties and is superior to bulk Si, so porous SiC should be superior to porous Si. Fabrication of porous SiC has been demonstrated in the literature, but detailed studies of the process are lacking. Its thermal conductivity and mechanical properties have never been measured and its high-temperature behaviour has only been partially characterised. We have carried out a systematic study of the effects of HF concentration and current on the porosification process. We have implemented a thermal conductivity measurement setup using the ???3 omega??? method and used it to measure the thermal conductivity of porous SiC. We have shown that it is about two orders of magnitude lower than that of bulk SiC. We have also shown that porous SiC is chemically inert in the most commonly used solutions for microfabrication. Our results show that porous SiC is stable up to at least 1000???C and we have obtained encouraging qualitative results regarding its mechanical properties. This means that porous SiC is compatible with microfabrication processes, and can be integrated in MEMS as a thermal insulation material.

The two-dimensional phase of carbon known as graphene is actively being pursued as a primary material in future electronic devices. The goals of this thesis are to investigate the growth and electronic properties of epitaxial graphene on SiC, with a particular focus on nanostructured graphene. The first part of this thesis examines the kinetics of graphene growth on SiC(0001) and SiC(0001 ̅) by high-temperature sublimation of the substrate using a custom-built, ultra-high vacuum induction furnace. A first-principles kinetic theory of silicon sublimation and mass-transfer is developed to describe the functional dependence of the graphene growth rate on the furnace temperature and pressure. This theory can be used to calibrate other graphene growth furnaces which employ confinement controlled sublimation. The final chapter in this thesis involves a careful study of self-organized epitaxial graphene nanoribbons (GNRs) on SiC(0001). Scanning tunneling microscopy of the sidewall GNRs confirms that these self-organized nanostructures are susceptible to overgrowth onto nearby SiC terraces. Atomic-scale imaging of the overgrown sidewall GNRs detected local strained regions in the nanoribbon crystal lattice, with strain coefficients as high as 15%. Scanning tunneling spectroscopy (STS) of these strained regions demonstrate that the graphene electronic local density of states is strongly affected by distortions in the crystal lattice. Room temperature STS in regions with a large strain gradient found local energy gaps as high as 400 meV. Controllable, strain-induced quantum states in epitaxial graphene on SiC could be utilized in new electronic devices. / Per request of the author and the advisor, and with the approval of the graduate office, the Acknowledgements page was replaced with an errata.

In this thesis work several manufacturing methods for graphene is discussed followed by an indepth study of graphene grown by a high temperature sublimation method (sublimation of siliconcarbide). The graphene surfaces studied have been grown by Graphensic AB, both graphenegrown on the Si-face and the C-face of the silicon carbide were studied. Six graphene samplesgrown 4H-SiC substrates were examined for homogeneity and surface morphology as well assome surface roughness parameters using Atomic Force Microscopy (AFM). The graphene wasstudied to get a better understanding of the surfaces and the growth mechanisms to improvemanufacturing parameters while also being informative for graphene sample customers. Anadditional graphene sample grown on 6H-SiC epitaxial layer was also studied to get a betterunderstanding of the sublimation mechanism. If graphene could be manufactured in a cheaprepeatable way the applications are endless and a new era of technology could emerge muchlike the silicon era that began several decades ago. In this thesis work the results are presentedas topography images as well as tables and histograms in the results section. The growth onthe Si-face is found to be well ordered when compared to the C-face which shows signs of alargely complex growth. The graphene on the Si-face lies on top of silicon carbide steps like acarpet with a buer layer interface against the silicon carbide. On the C-face this buer layeris not present but the graphene is deformed by buckling which is suspected to originate fromdierences in thermal properties between the graphene and the C-face. The in uence of AFMsettings for characterization of graphene while using intermittent mode have been evaluated andrecommendations are given. Finally a method for evaluating the homogeneity of the graphenelm is proposed but is in need of further verication.

Graphene, a single sheet of carbon atoms sp2-bonded in a honeycomb lattice, is a possible all-carbon successor to silicon electronics. Ballistic conduction at room temperature and a linear dispersion relation that causes carriers to behave as massless Dirac fermions are features that make graphene promising for high-speed, low-power devices. The critical advantage of epitaxial graphene (EG) grown on SiC is its compatibility with standard lithographic procedures. Surface X-ray diffraction (SXRD) and scanning tunneling microscopy (STM) results are presented on the domain structure, interface composition and stacking character of graphene grown on both polar faces of semi-insulating 4H-SiC. The data reveal intriguing differences between graphene grown on these two faces. Substrate roughening is more pronounced and graphene domain sizes are significantly smaller on the SiC (0001) Si-face. Specular X-ray reflectivity measurements show that both faces have a carbon rich, extended interface that is tightly bound to the first graphene layer, leading to a buffering effect that shields the first graphene layer from the bulk SiC, as predicted by ab initio calculations. In-plane X-ray crystal truncation rod analysis indicates that rotated graphene layers are interleaved in C-face graphene films and corresponding superstructures are observed in STM topographs. These rotational stacking faults in multilayer C-face graphene preserve the linear dispersion found in single layer graphene, making EG electronics possible even for a multilayer material.