Les résultats de différentes expériences du CNES (Centre National d’Études Spatiales) embarquées sur satellites montrent que des composants SRAM et SDRAM subissent des erreurs atypiques, qui se caractérisent par une fraction d’emplacements mémoire présentant des erreurs récurrentes. Ces erreurs non-catégorisées représentent la quasi-totalité des erreurs détectées sur ces mémoires. Une revue interne du CNES a déterminé que ces erreurs étaient dues aux radiations présentes dans l’environnement spatial (protons, électrons, ions lourds). Cette thèse s’attache à reproduire ces erreurs atypiques au sol en utilisant des moyens d’irradiation et des accélérateurs de particules, à les caractériser ainsi qu’à expliquer le mécanisme physique menant à l’apparition de ces cellules endommagées. Le mécanisme physique que nous proposons est cohérent avec les données obtenues sous faisceau de particules et soutenu par nos simulations de type TCAD. / CNES’s onboard experiment results on several satellites have demonstrated that on SRAM and SDRAM memories, a fraction of words suffers from unknown errors that increase the afflicted words’ rate of error by orders of magnitude compared to other words. CNES’s experts found that these errors were due to the space radiation environment (proton, electrons, heavy ions).The main goals of this Ph.D. thesis are to successfully recreate such errors at ground level using irradiation facilities and particle accelerators, to investigate their behavior and finally, to submit a physical mechanism for memory cell degradation under irradiation, both coherent with experimental data and data obtained from TCAD simulations.

Cette thèse s'intéresse en premier lieu à l'évaluation des effets fonctionnels des erreurs survenant dans la mémoire SRAM de configuration de certains FPGAs. La famille Virtex II Pro de Xilinx est utilisée comme premier cas pratique d'expérimentation. Des expérimentations sous faisceau laser nous ont permis d'avoir une bonne vue d'ensemble sur les motifs d'erreurs réalistes qui sont obtenus par des sources de perturbations réelles. Une méthodologie adaptée d'injection de fautes a donc été définie pour permettre une meilleure évaluation, en phase de conception, de la robustesse d'un circuit implanté sur ce type de technologie. Cette méthodologie est basée sur de la reconfiguration dynamique. Le même type d'approche a ensuite été évalué sur plusieurs cibles technologiques, ce qui a nécessité le développement de plusieurs environnements d'injection de fautes. L'étude a pour la première fois inclus la famille AT40K de ATMEL, qui permet un type de reconfiguration unique et efficace. Le second type de contribution concerne l'augmentation à faible coût de la robustesse de circuits implantés sur des plateformes FPGA SRAM. Nous proposons une approche de protection sélective exploitant les ressources du FPGA inutilisées par l'application. L'approche a été automatisée sur plusieurs cibles technologiques (Xilinx, Altera) et l'efficacité est analysée en utilisant les méthodes d'injection de fautes précédemment développées. / This thesis focuses primarily on the evaluation of the functional effects of errors occurring in the SRAM configuration memory of some FPGAs. Xilinx Virtex II Pro family is used as a first case study. Experiments under laser beam allowed us to have a good overview of realistic error patterns, related to real disturbance sources. A suited fault injection methodology has thus been defined to improve design-time robustness evaluations of a circuit implemented on this type of technology. This methodology is based on runtime reconfiguration. The approach has then been evaluated on several technological targets, requiring the development of several fault injection environments. The study included for the first time the ATMEL AT40K family, with a unique and efficient reconfiguration mode. The second type of contribution is focused on the improvement at low cost of the robustness of designs implemented on SRAM-based FPGA platforms. We propose a selective protection approach exploiting resources unused by the application. The approach has been automated on several technological targets (Xilinx, Altera) and the efficiency has been analyzed by taking advantage of the fault injection techniques previously developed.

La miniaturisation des transistors vers ses ultimes limites physiques a exacerbé les effets négatifs qui sont liées à la granularité de la matière. Plusieurs nouvelles sources de variabilités affectent les transistors qui, bien qu'identiquement dessinés, montrent des caractéristiques électriques qui sont variables entre eux et entre différents moments de leur utilisation. Les circuits de mémoire SRAM, qui sont conçues avec des règles de dessin parmi le plus agressives et contiennent un nombre de transistors très élevé, sont menacés en particulier par ce phéomène de variabilité qui représente le plus grand obstacle non seulement pour la réduction de la surface d'un point mémoire SRAM, mais aussi pour la réduction de son tension d'alimentation. L'optimisation des circuits SRAM est devenue une tache cruciale afin de répondre à la fois aux demandes d'augmentation de densité et de la réduction de la consommation, donc une méthodologie statistique permettant de modéliser an amont l'impact de la variabilité à travers des simulations SPICE est devenue un besoin obligatoire. Les travaux de recherches présentés se concentrent sur le développement des nouvelles méthodologies pour la simulation des points mémoires sous l'impact de la variabilité, dans le but d'accomplir une modélisation précise de la tension d'alimentation minimale d'un SRAM quelques soit les conditions d'opérations. La variabilité dynamique liée au bruit RTS qui cause le changement des caractéristiques électrique des transistors au cours de leurs opérations est également étudiée avec un effort particulier de modélisation. Ce travail a donné lieu à de nombreuses publications internationales et à un brevet. Aujourd'hui cette méthodologie est retenue par STMicroelectronics et est utilisé dans la phase d'optimisation des plans mémoires SRAM. / The downscaling of device geometry towards its physical limits exacerbates the impact of the inevitable atomistic phenomena tied to matter granularity. In this context, many different variability sources raise and affect the electrical characteristics of the manufactured devices. The variability-aware design methodology has therefore become a popular research topic in the field of digital circuit design, since the increased number of transistors in the modern integrated circuits had led to a large statistical variability affecting dramatically circuit functionality. Static Random Access Memory (SRAM) circuits which are manufactured with the most aggressive design rules in a given technology node and contain billions of transistor, are severely impacted by the process variability which stands as the main obstacle for the further reduction of the bitcell area and of its minimum operating voltage. The reduction of the latter is a very important parameter for Low-Power design, which is one of the most popular research fields of our era. The optimization of SRAM bitcell design therefore has become a crucial task to guarantee the good functionality of the design at an industrial manufacturing level, in the same time answering to the high density and low power demands. However, the long time required by each new technology node process development means a long waiting time before obtaining silicon results, which is in cruel contrast with the fact that the design optimization has to be started as early as possible. An efficient SPICE characterization methodology for the minimum operating voltage of SRAM circuits is therefore a mandatory requirement for design optimization. This research work concentrates on the development of the new simulation methodologies for the modeling of the process variability in ultra-deep-submicron SRAMs, with the ultimate goal of a significantly accurate modeling of the minimum operating voltage Vmin. A particular interest is also carried on the time-dependent sub-class of the process variability, which appears as a change in the electrical characteristics of a given transistor during its operation and during its life-time. This research work has led to many publications and one patent application. The majority of findings are retained by STMicroelectronics SRAM development team for a further use in their design optimization flow.

This paper outlines design considerations and implementation details of full swing and of partial swing SRAM arrays. Comparisons between the two methods based on performance, power, and noise rejection are then presented. Finally, a decision matrix will be provided that selects the better topology based on varying design constraints. / text

Ce travail contribue à établir une méthode de test permettant de déterminer l'impact des radiations naturelles sur le fonctionnement de circuits intégrés de type FPGA SRAM-Based. L'étude des erreurs potentielles liées aux événements singuliers ou multiples ayant lieu dans la mémoire de configuration sera faite à l'aide d'expériences d'injection de fautes réalisées avec un équipement laser. Il s'appuie sur une présentation du contexte scientifique ainsi qu'une description de l'architecture complexe des FPGA SRAM-Based et des moyens de tests usuels. Des expériences d'injection de fautes à l'aide d'un laser sont menées sur plusieurs familles de composants afin de réaliser des tests statiques de la mémoire de configuration et de trouver les liens avec le fonctionnement de l'application. Elles révèlent ainsi l'organisation et la sensibilité des cellules SRAM de configuration. Des tests dynamiques en accélérateur de protons permettent de définir des critères de criticité des bits de configuration en fonction de leur impact sur l'application. Un outil de prédiction du taux d'erreur critique a été développé et validé à partir de cette classification.

<p>In this thesis, a Static Random Access Memory generator has been designed and implemented. The tool can generate memories of different sizes. The number of words that can be stored can be chosen among powers of 2 and the number of bits per word can be up to 48. </p><p>The focus of the thesis was to find an adequate structure for the generated memories depending on the size, and develop a memory generator that implements the structures, which has been thoroughly done. The single circuits used in the generated memories can be substituted with better circuits as well as adapted to other processes. </p><p>All circuits apart from a block decoder circuit have been developed. The memory generator was not supposed to automatically produce a complete layout, and some manual interventions on the memories generated by the tool are necessary. The tool requires to be developed further to minimise this manual intervention on the generated memories. The complete memories generated have not been tested because of their complexity, but tests on circuits as well as many parts of the memories have been carried out. </p><p>During the thesis work, a large amount of tasks had to be carried out and a lot of issues had to be dealt with, which has been a problem. The tool used for the implementation has powerful features for both analog and digital electronic design, but has stability problems with large designs, which has been a big obstacle in this work.</p>

With the increment of mobile, biomedical and space applications, digital systems with low-power consumption are required. As a main part in digital systems, low-power memories are especially desired. Reducing the power supply voltages to sub-threshold region is one of the effective approaches for ultra low-power applications. However, the reduced Static Noise Margin (SNM) of Static Random Access Memory (SRAM) imposes great challenges to the subthreshold SRAM design. The conventional 6-transistor SRAM cell does not function properly at sub-threshold supply voltage range because it has no enough noise margin for reliable operation. In order to achieve ultra low-power at sub-threshold operation, previous research work has demonstrated that the read and write decoupled scheme is a good solution to the reduced SNM problem. A Dual Interlocked Storage Cell (DICE) based SRAM cell was proposed to eliminate the drawback of conventional DICE cell during read operation. This cell can mitigate the singleevent effects, improve the stability and also maintain the low-power characteristic of subthreshold SRAM, In order to make the proposed SRAM cell work under different power supply voltages from 0.3 V to 0.6 V, an improved replica sense scheme was applied to produce a reference control signal, with which the optimal read time could be achieved. In this thesis, a 2K~8 bits SRAM test chip was designed, simulated and fabricated in 90nm CMOS technology provided by ST Microelectronics. Simulation results suggest that the operating frequency at VDD = 0.3 V is up to 4.7 MHz with power dissipation 6.0 ÊW, while it is 45.5 MHz at VDD = 0.6 V dissipating 140 ÊW. However, the area occupied by a single cell is larger than that by conventional SRAM due to additional transistors used. The main contribution of this thesis project is that we proposed a new design that could simultaneously solve the ultra low-power and radiation-tolerance problem in large capacity memory design.

This thesis explores means of mitigating the effects of silicon variation on SRAM by means of circuit techniques. This thesis also explores novel read and write techniques for MRAM that support a non-destructive read operation and power-saving write operations in the face of device and silicon variation. First, this thesis proposes the use of a cross-coupled bit line BL biasing scheme that retains an SRAM's fast access speed while reducing the read-access failures in the presence of Vt variation, without excessively increasing the SRAM cell size. It is shown, by extensive Monte-Carlo simulations using 22-nm predictive CMOS models, that the proposed scheme reduces the cell area by 6.5% compared to the conventional BL biasing schemes also analyzed. Second, this thesis proposes a 10T SRAM cell that supports lower voltage operation, achieves lower static power dissipation, and is similar in area to the 6T SRAM cell when the 3-sigma variation of Vt exceeds 40% of nominal Vt. The 10T cell achieves improved write functionality, in comparison to the 6T cell, by preemptively turning off the cell's power supply to the side of the cell that is being pulled low, while not disturbing any unselected cells. Write access time is not affected, as the positive-feedback required to quickly regenerate CMOS voltage levels remains intact. Finally, this thesis proposes a negative-resistance read scheme and write scheme for spin-torque-transfer (STT) MRAM. A negative resistance shunting an STT-MRAM cell guarantees a non-destructive read operation, and saves power during write operations compared with a conventional scheme. Measurements confirm an 7ns non-destructive read access time without the use of a typical sense amplifier and an average write power savings of 10.5% for a 16Kb STT-MRAM fabricated in 0.13um CMOS using a CoFeB/MgO/CoFeB MTJ.

This thesis explores means of mitigating the effects of silicon variation on SRAM by means of circuit techniques. This thesis also explores novel read and write techniques for MRAM that support a non-destructive read operation and power-saving write operations in the face of device and silicon variation. First, this thesis proposes the use of a cross-coupled bit line BL biasing scheme that retains an SRAM's fast access speed while reducing the read-access failures in the presence of Vt variation, without excessively increasing the SRAM cell size. It is shown, by extensive Monte-Carlo simulations using 22-nm predictive CMOS models, that the proposed scheme reduces the cell area by 6.5% compared to the conventional BL biasing schemes also analyzed. Second, this thesis proposes a 10T SRAM cell that supports lower voltage operation, achieves lower static power dissipation, and is similar in area to the 6T SRAM cell when the 3-sigma variation of Vt exceeds 40% of nominal Vt. The 10T cell achieves improved write functionality, in comparison to the 6T cell, by preemptively turning off the cell's power supply to the side of the cell that is being pulled low, while not disturbing any unselected cells. Write access time is not affected, as the positive-feedback required to quickly regenerate CMOS voltage levels remains intact. Finally, this thesis proposes a negative-resistance read scheme and write scheme for spin-torque-transfer (STT) MRAM. A negative resistance shunting an STT-MRAM cell guarantees a non-destructive read operation, and saves power during write operations compared with a conventional scheme. Measurements confirm an 7ns non-destructive read access time without the use of a typical sense amplifier and an average write power savings of 10.5% for a 16Kb STT-MRAM fabricated in 0.13um CMOS using a CoFeB/MgO/CoFeB MTJ.

In this thesis, a Static Random Access Memory generator has been designed and implemented. The tool can generate memories of different sizes. The number of words that can be stored can be chosen among powers of 2 and the number of bits per word can be up to 48. The focus of the thesis was to find an adequate structure for the generated memories depending on the size, and develop a memory generator that implements the structures, which has been thoroughly done. The single circuits used in the generated memories can be substituted with better circuits as well as adapted to other processes. All circuits apart from a block decoder circuit have been developed. The memory generator was not supposed to automatically produce a complete layout, and some manual interventions on the memories generated by the tool are necessary. The tool requires to be developed further to minimise this manual intervention on the generated memories. The complete memories generated have not been tested because of their complexity, but tests on circuits as well as many parts of the memories have been carried out. During the thesis work, a large amount of tasks had to be carried out and a lot of issues had to be dealt with, which has been a problem. The tool used for the implementation has powerful features for both analog and digital electronic design, but has stability problems with large designs, which has been a big obstacle in this work.