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Arbetet undersöker skillnader i prestanda mellan SOLID och mer hårdkodade algoritmer, i form av respektive beteendeträd och en enum-switch tillståndsmaskin. Testerna utförs i spelmotorn Unity genom en isolerad testmiljö där exekveringstiden mäts mellan i scenarion. Algoritmerna har implementerats så att de kan köra olika beteenden, dessa testas i olika scenarion för att få fram resultaten. Exekveringstid mäts genom profiler-verktyget i Unity som sedan analyseras och jämförs för att se hur mycket tid det tar att exekvera och om det finns skillnader mellan dem. Resultaten tyder på att den hårdkodade algoritmen presterade bättre än den som följde SOLID-principer, dock inte så markant att det utesluter användningen av den mer flexibla koden.

Nous proposons dans cette thèse les approches de test pour la composition de services web. Nous nous intéressons aux test unitaire et d’intégration d’une orchestration de services web. L’aspect de vérification d’exécution en-ligne est aussi consideré. Nous définissons une plateforme de test unitaire pour l’orchestration de services web qui compose une architecture de test, une relation de conformité et deux approches de test basés sur le modèle de machine à l’états finis étendues temporisés: l’approche offline où les activités de test comme la génération de cas de test temporisé, l’exécution de test et l’assignement de verdict sont appliquées en séquentielle tandis que ces activités sont appliquées en parallèle dans l’approche online. Pour le test d’intégration d’une orchestration, nous combinons deux approches: active et passive.Au debut, l’approche active est utilisée pour activer une nouvelle session d’orchestration par l’envoi d’un message de requête SOAP. Après, tous les messages d’entré et de sortie de l’orchestration sont collectés et analysés par l’approche passive.Pour l’aspect de vérification d’exécution en-ligne, nous nous intéressons à la vérification d’une trace qui respecte un ensemble des constraintes, noté règles, ou pas. Nous avons proposé extendre le langage Nomad en définissant des constraintes sur chaque action atomique et un ensemble de corrélation de données entre les actions pour définir des règles pour le service web. Ce langage nous permet de définir des règles avec le temps futur et passé, et d’utiliser des opérations NOT, AND, OR pour combiner quelque conditions dans le contexte de la règle. Ensuite, nous proposons un algorithme pour vérifier l’exactitude d’une séquence des messages en parallèle avec le moteur de collecte de trace. / In this thesis, we propose the testing approaches for web service composition. We focus on unit, integrated testing of an orchestration of web services and also the runtime verification aspect. We defined an unit testing framework for an orchestration that is composed of a test architecture, a conformance relation and two proposed testing approaches based on Timed Extended Finite State Machine (TEFSM) model: offline which test activities as timed test case generation, test execution and verdict assignment are applied in sequential, and online which test activities are applied in parallel. For integrated testing of an orchestration, we combines of two approaches: active and passive. Firstly, active approach is used to start a new session of the orchestration by sending a SOAP request. Then all communicating messages among services are collected and analyzed by a passive approach. On the runtime verification aspect, we are interested in the correctness of an execution trace with a set of defined constraints, called rules. We have proposed to extend the Nomad language, by defining the constraints on each atomic action (fixed conditions) and a set of data correlations between the actions to define the rules for web services. This language allows us to define a rule with future and past time, and to use the operations: NOT, AND, OR to combines some conditions into a context of the rule. Afterwards, we proposed an algorithm to check correctness of a message sequence in parallel with the trace collection engine. Specifically, this algorithm verifies message by message without storing them.

Dans la première partie de ce mémoire, nous étudions le modèle des protocoles de population, introduit dans\cite{DBLP:conf/podc/BeauquierBCK10}. Ce modèle permet de représenter les grands réseaux de capteurs (ou agents) mobiles anonymes dotés de faibles ressources. Les contraintes de ce modèle sont si sévères que la plupart des problèmes classiques d'algorithmique répartie, tels que la collecte de données, le consensus ou l'élection d'un leader, sont difficiles à analyser, sinon impossibles à résoudre.Nous commençons notre étude par le problème de collecte de données. Celui-ci consiste principalement à transférer des valeurs réparties dans la population d'agents mobiles vers une station de base en un minimum de temps (temps de convergence). En utilisant un hypothèse d'équité, dite hypothèse de temps couvertures et introduite dans \cite{DBLP:conf/podc/BeauquierBCK10}, nous calculons des bornes optimales sur le temps de convergences de différents protocoles concrets. Ensuite, nous étudions le problème du consensus et d'élection de leader. Il a été montré que ces problèmes sont impossibles à résoudre dans le modèle original des protocoles de population. Pour contourner cette impossibilité, il est possible d'adjoindre au modèle certaines hypothèses sous la forme d'oracles. Nous proposons ensuite divers oracles permettant de résoudre le problème du consensus et d'élection de leader dans divers environnements, et nous étudions leurs puissances relatives. Ce faisant, nous développons un cadre formel permettant de représenter toutes les variétés d'oracles introduites, ainsi que leur possibles relations.Dans la seconde partie de ce mémoire, nous étudions le problème de la réplication de machine à états finis dans le modèle (classique) de communications asynchrones à passage de message. L'algorithme Paxos, introduit dans \cite{lamportPartTimeParliament,lamport01paxos} est une solution (partielle) bien connue au problème de la réplication capable de tolérer des pannes crash. Notre contribution, dans cette partie,consiste à améliorer Paxos afin qu'il puisse également tolérer des défaillances transitoires. Ce faisant, nous définissons la notions de machine répliquée pratiquement autostable. / In the first part of this thesis, we focus on a recent model, calledpopulation protocols, which describes large networksof tiny wireless mobile anonymous agents with very limited resources.The harsh constraints of the original model makes most of theclassical problems of distributed algorithmics, such as datacollection, consensus and leader election, either difficult to analyzeor impossible to solve.We first study the data collection problem, which mainly consists intransferring some values to a base station. By using a fairnessassumption, known as cover times, we compute tight bounds on theconvergence time of concrete protocols. Next, we focus on theproblems of consensus and leader election. It is shown that theseproblems are impossible in the original model. To circumvent theseissues, we augment the original model with oracles, and study theirrelative power. We develop by the way a formal framework generalenough to encompass various sorts of oracles, as well as theirrelations.In the second part of the thesis, we study the problem ofstate-machine replication in the more classical model of asynchronousmessage-passing communication. The Paxos algorithm is a famous(partial) solution to the state-machine replication problem whichtolerates crash failures. Our contribution is the enhancement of Paxosin order to tolerate transient faults as well. Doing so, we define thenotion of practically self-stabilizing replicated state-machine.

A Arquitetura Orientada a Serviços (SOA) é um estilo arquitetural formado por um conjunto de restrições que visa promover a escalabilidade e a flexibilidade de um sistema, provendo suas funcionalidades como serviços. Nos últimos anos, um estilo alternativo foi proposto e amplamente adotado, que projeta as funcionalidades de um sistema como recursos. Este estilo arquitetural orientado a recursos é chamado de REST. O teste de serviços web em geral apresenta vários desafios devido a sua natureza distribuída, canal de comunicação pouco confiável, baixo acoplamento e a falta de uma interface de usuário. O teste de serviços RESTful (serviços que utilizam o REST) compartilham estes mesmos desafios e ainda necessitam que suas restrições sejam obedecidas. Estes desafios demandam testes mais sistemáticos e formais. Neste contexto, o teste baseado em modelos (TBM) se apresenta como um processo viável para abordar essas necessidades. O modelo que representa o sistema deve ser simples e ao mesmo tempo preciso para que sejam gerados casos de teste com qualidade. Com base nesse contexto, este projeto de mestrado propõe uma abordagem baseada em modelos para testar serviços RESTful. O modelo comportamental adotado foi a máquina de estados de protocolos UML, capaz de formalizar a interface do serviço enquanto esconde o seu funcionamento interno. Uma ferramenta foi desenvolvida para gerar automaticamente os casos de teste usando critérios de cobertura de estados e transições para percorrer o modelo / Service Oriented Architecture (SOA) is an architectural style consisting of a set of restrictions aimed at promoting the scalability and flexibility of a system, providing its functionalities as services. In recent years, an alternative style was proposed and widely adopted, which designs the system\'s functionalities as resources. This resource oriented architectural style is called REST. In general, the test of web services has several challenges due to its distributed nature, unreliable communication channel, low coupling and the lack of a user interface. Testing RESTful web services (services that use REST) share these same challenges and also need to obey the REST constraints. These challenges require a more systematic and formal testing approach. In this context, model based testing presents itself as a viable process for addressing those needs. The model that represents the system should be simple and precise enough to generate quality test cases. Based on this context, this work proposes a model based approach to test RESTful web services. The behavioral model used was the UML protocol state machine, which is capable to provide a formalization of the service interface, while hiding its internal behaviour. A tool was developed to automatically generate test cases using the state and transition coverage criteria to traverse the model

La sophistication grandissante des dispositifs intelligents ultra-portatifs, tels que les smartphones ou les tablettes,crée un besoin d'amélioration des performances des organes de conversion de puissance.La tendance des technologies d'acheminement de puissance évolue progressivement vers une fréquence plus élevée, une meilleure densité d'intégration et une plus grande flexibilité dans les schémas d'asservissement. La modulation dynamique de tension est utilisée dans les circuits intégrés de gestion de puissances(DVS PMICs)des transmetteurs RF alors que la modulation DVFS est utilisée dans les PMICs dédiées au CPUs et GPUs. Des DCDC flexibles et fonctionnant à haute fréquence constituent aujourd'hui la solution principale en conjonction avec des régulateurs à faible marge de tension (LDO).L'évolution vers des solutions à base de HFDCDC de faibles dimensions pose un défi sérieux en matière de 1)stabilité des boucles d'asservissement,2)de complexité des architectures de contrôle imbriquant des machines d'état asynchrones pour gérer une large dynamique de puissance de sortie et 3)de portabilité de la solutions d'une technologie à une autre.Les solutions les plus courantes atteignent aujourd'hui une gamme de 2 à 6 Mhz de fréquence de découpage grâce à l'usage de contrôleurs à hystérésis qui souffrent de la difficulté à contenir la fréquence de découpage lors des variations de la tension ou du courant en charge.Nous avons voulu dans ce travail étendre l'usage des méthodes de conception et de modélisation conventionnelles comme le modèle petit signal moyen, dans une perspective de simplification et de création de modèles paramétriques. L'objectif étant de rendre la technique de compensation flexible et robuste aux variations de procédés de fabrication ou bien aux signaux parasités inhérents à la commutation de puissance.Certes, le modèle moyen petit signal, au demeurant bien traité dans la littérature, réponds amplement à la problématique de compensation des DCDCs notamment quand la stabilité s'appuie sur le zéro naturel à haute fréquence inhérent à la résistance série ESR de la capacité de sortie, mais les HFDCDC actuels utilisent des capacités MLCC ayant une très faible ESR et font appel à des techniques de compensation paramétriques imbriquant le schéma de compensation dans la génération même du rapport cyclique. La littérature existante sur le fonctionnement de la machine d'état, se contente d'une description simpliste de convertisseurs PWM/PFM mais ne donne que très peu d'éléments sur la gestion des opérations synchrones/asynchrones alternant PWM,PFM,écrêtage de courant, démarrage ou détection de défaillance. Dans ce travail, notre études est axée sur les deux aspects suivants:1)La modélisation paramétrique et la compensation de la boucle d'asservissement de HFDCDC et 2)la portabilité de la conception de la machine d'états du contrôleur notamment lorsqu'elle intègre des transitions complexes entre les modes.Dans la première section, nous avons développé un modèle petit signal moyen d'un convertisseur Buck asservi en mode courant-tension et nous l'avons analysé pour faire apparaitre les contributions proportionnelle, intégrale et dérivé dans la boucle. Nous avons démontré la possibilité d'utiliser le retour en courant pour assurer l'amortissement nécessaire et la stabilité de la boucle pour une large dynamique de variations des conditions de charge.Dans la seconde section, nous avons développé une architecture de machine d'états sophistiquée basé sur la méthode d'Huffman avec un effort substantiel d'abstraction que nous a permis de la concevoir en description RTL pour une gestion fiable du fonctionnement asynchrone et temps réel.Notre contribution théorique a fait l'objet d'une réalisation d'un PMIC de test comportant deux convertisseurs Buck cadencés à 12MHz en technologie BiCMOS 0.5um/0.18um. Les performances clefs obtenues sont:une surtension de 50mV pendant 2us suite à l'application d'un échelon de courant de 300mA. / The continuous sophistication of smart handheld devices such as smartphones and tablets creates an incremental need for improving the performances of the power conversion devices. The trend in power delivery migrates progressively to higher frequency, higher density of integration and flexibility of the control scheme. Dynamic Voltage Scaling Power Management ICs (DVS PMIC) are now systematically used for powering RF Transmitters and DVFS PMICS using Voltage and Frequency scaling are used for CPUs and GPUs. Flexible High frequency (HF) DC/DC converters in conjunction with low dropout LDOs constitute the main solution largely employed for such purposes. The migration toward high frequency/small size DCDC solutions creates serious challenges which are: 1) the stability of the feedback loop across a wide range of loading voltage and current conditions 2) The complexity of the control and often-non-synchronous state machine managing ultra large dynamics and bridging low power and high power operating modes, 3) The portability of the proposed solution across technology processes.The main stream solutions have so far reached the range of 2 to 6 MHz operation by employing systematically sliding mode or hysteretic converters that suffer from their variable operating frequency which creates EMI interferences and lead to integration problems relative to on-chip cross-talk between converters.In this work we aim at extend the use of traditional design and modeling techniques of power converters especially the average modeling technique by putting a particular care on the simplification of the theory and adjunction of flexible compensation techniques that don't require external components and that are less sensitive to process spread, or to high frequency substrate and supply noise conditions.The Small Signal Average Models, widely treated in the existing literature, might address most needs for system modeling and external compensation snubber design, especially when aiming on the high frequency natural zero of the output capacitor. However, HFDCDC converters today use small size MLCC capacitors with a very low ESR which require using alternative techniques mixing the compensation scheme with the duty cycle generation itself. The literature often provides a simplistic state machine description such as PWM/PFM operations but doesn't cover combined architectures of synchronous / non synchronous mode operations such as PWM, PFM, Current Limit, Boundary Clamp, Start, Transitional and finally Fault or Protection modes.In our work, we have focused our study on two main axes: 1) The parametric modeling and the loop compensation of HFDCDC and 2) the scalability of the control state machine and mode inter-operation. In the first part, we provided a detailed small signal averaged model of the “voltage and current mode buck converter” and we depicted it to emphasize and optimize the contributions of the Proportional, Integral and Derivative feedback loops. We demonstrated the ability to use the current feedback to damp and stabilize the converter with a wide variety of loading conditions (resistive or capacitive). In the second part, we provided architecture of the mode control state machine with different modes like the PWM, PFM, soft-start, current limit,… .The technique we have used is inspired by Huffman machine with a significant effort to make it abstract and scalable. The state machine is implemented using RTL coding based on a generic and scalable approach.The theoretical effort has been implemented inside a real PMIC test-chip carrying two 12MHz buck converters, each employing a voltage and current mode feedback loop. The chip has been realized in a 0.5um / 0.18um BiCMOS technology and tested through a dedicate Silicon validation platform able to test the analog, digital and power sections. The key performance obtained is a 50mV load transient undershoot / overshoot during 2us following a load step of 300mA (slope 0.3A/ns).

Esta dissertação investiga a aplicação dos algoritmos evolucionários inspirados na computação quântica na síntese de circuitos sequenciais. Os sistemas digitais sequenciais representam uma classe de circuitos que é capaz de executar operações em uma determinada sequência. Nos circuitos sequenciais, os valores dos sinais de saída dependem não só dos valores dos sinais de entrada como também do estado atual do sistema. Os requisitos cada vez mais exigentes quanto à funcionalidade e ao desempenho dos sistemas digitais exigem projetos cada vez mais eficientes. O projeto destes circuitos, quando executado de forma manual, se tornou demorado e, com isso, a importância das ferramentas para a síntese automática de circuitos cresceu rapidamente. Estas ferramentas conhecidas como ECAD (Electronic Computer-Aided Design) são programas de computador normalmente baseados em heurísticas. Recentemente, os algoritmos evolucionários também começaram a ser utilizados como base para as ferramentas ECAD. Estas aplicações são referenciadas na literatura como eletrônica evolucionária. Os algoritmos mais comumente utilizados na eletrônica evolucionária são os algoritmos genéticos e a programação genética. Este trabalho apresenta um estudo da aplicação dos algoritmos evolucionários inspirados na computação quântica como uma ferramenta para a síntese automática de circuitos sequenciais. Esta classe de algoritmos utiliza os princípios da computação quântica para melhorar o desempenho dos algoritmos evolucionários. Tradicionalmente, o projeto dos circuitos sequenciais é dividido em cinco etapas principais: (i) Especificação da máquina de estados; (ii) Redução de estados; (iii) Atribuição de estados; (iv) Síntese da lógica de controle e (v) Implementação da máquina de estados. O Algoritmo Evolucionário Inspirado na Computação Quântica (AEICQ) proposto neste trabalho é utilizado na etapa de atribuição de estados. A escolha de uma atribuição de estados ótima é tratada na literatura como um problema ainda sem solução. A atribuição de estados escolhida para uma determinada máquina de estados tem um impacto direto na complexidade da sua lógica de controle. Os resultados mostram que as atribuições de estados obtidas pelo AEICQ de fato conduzem à implementação de circuitos de menor complexidade quando comparados com os circuitos gerados a partir de atribuições obtidas por outros métodos. O AEICQ e utilizado também na etapa de síntese da lógica de controle das máquinas de estados. Os circuitos evoluídos pelo AEICQ são otimizados segundo a área ocupada e o atraso de propagação. Estes circuitos são compatíveis com os circuitos obtidos por outros métodos e em alguns casos até mesmo superior em termos de área e de desempenho, sugerindo que existe um potencial de aplicação desta classe de algoritmos no projeto de circuitos eletrônicos. / This thesis investigates the application of quantum inspired evolutionary algorithms in the synthesis of sequential circuits. Sequential digital systems represent a class of circuit that is able to execute operations in a particular sequence. In sequential circuits, the values of output signals not only depend on the values of input signals but also on the current state of the system. The increasingly high requirements regarding the functionality and performance of digital systems demand more efficient designs. The design of these circuits, when implemented manually, became slow and thus the importance of tools for automatic synthesis of circuits grew rapidly. These tools known as ECAD (Electronic Computer-Aided Design) are computer programs usually based on heuristics. Recently, evolutionary algorithms also began to be used as a basis in ECAD tools developing. These applications are referenced in literature as evolutionary electronics. The algorithms most commonly used in evolutionary electronics are genetic algorithms and genetic programming. This work presents a study of the application of quantum inspired evolutionary algorithms as a tool for automatic synthesis of sequential circuits. This class of algorithms uses the principles of quantum computing to improve the performance of evolutionary algorithms. Traditionally, the design of sequential circuits is divided into five main steps: (i) State machine specification; (ii) Reduction of states; (iii) State assignment; (iv) Control logic synthesis and (v) Implementation of the state machine. The proposed algorithm AEICQ is used in the state assignment design step. The choice of an optimal state assignment is treated in the literature as an issue still unresolved. The state assignment chosen for a particular state machine has a direct impact on the complexity of its control logic. The results show that the state assignment obtained by AEICQ in fact leads to the implementation of circuits of less complexity when compared with the ones generated from assignments obtained by other methods. The AEICQ is also used in the control logic synthesis of the state machine. The circuits evolved by AEICQ are optimized according to the area occupied and the propagation delay. These circuits are compatible with the circuits obtained by other methods and in some cases even higher in terms of area and performance, suggesting that there is a potential for application of this class of algorithms in the design of electronic circuits.

Les systèmes intégrés sont souvent des systèmes hétérogènes avec des contraintes fortes de consommation électrique. Ils embarquent aujourd'hui des actionneurs, des capteurs et des unités pour le traitement du signal. Afin de limiter l'énergie consommée, ils peuvent tirer profit des techniques évènementielles que sont l'échantillonnage non uniforme et l'électronique asynchrone. En effet, elles permettent de réduire drastiquement la quantité de données échantillonnées pour de nombreuses classes de signaux et de diminuer l'activité. Pour aider les concepteurs à développer rapidement des plateformes exploitant ces deux techniques évènementielles, nous avons élaboré un flot de conception nommé ALPS. Il propose un environnement permettant de déterminer et de simuler au niveau algorithmique le schéma d'échantillonnage et les traitements associés afin de sélectionner les plus efficients en fonction de l'application ciblée. ALPS génère directement le convertisseur analogique/numérique à partir des paramètres d'échantillonnage choisis. L'élaboration de la partie de traitement s'appuie quant à elle sur un outil de synthèse de haut niveau synchrone et une méthode de désynchronisation exploitant des protocoles asynchrones spécifiques, capables d'optimiser la surface et la consommation du circuit. Enfin, des simulations au niveau porteslogiques permettent d'analyser et de valider l'énergie consommée avant de poursuivre par un flot classique de placement et routage. Les évaluations conduites montrent une réduction d'un facteur 3 à 8 de la consommation des circuits automatiquement générés. Le flot ALPS permet à un concepteur non-spécialiste de se concentrer sur l'optimisation de l'échantillonnage et de l'algorithme en fonction de l'application et de potentiellement réduire d'un ou plusieurs ordres de grandeur la consommation du circuit. / Integrated systems are mainly heterogeneous systems with strong powerconsumption constraints. They embed actuators, sensors and signalprocessing units. To limit the energy consumption, they can exploitevent-based techniques, namely non-uniform sampling and asynchronouscircuits. Indeed, they allow cutting drastically the amount of sampleddata for many types of signals and reducing the system activity. To helpdesigners in quickly developing platforms that exploit those event-basedtechniques, we elaborated a design framework called ALPS. It proposes anenvironment to determine and simulate at algorithmic level the samplingscheme and the associated processing in order to select the mostefficient ones depending on the targetted application. ALPS generatesdirectly the analog-to-digital converter based on the chosen samplingparameters. The elaboration of the processing unit uses a synchronoushigh-level synthesis tool and a desynchronization method that exploitsspecific asynchronous protocols to optimize the circuit area and powerconsumption. Finally, gate-level simulations allow analyzing andvalidating the energy consumption before continuing with a standardplacement and routing flow. The conducted evaluations show a reductionfactor of 3 to 8 of the consumption of the automatically generatedcirctuis. The flow ALPS allow non-specialists to concentrate on theoptimization of the sampling and the processing in function of theirapplication and to reduice the circuit power consumptions by one toseveral orders of magnitude.

Esta dissertação investiga a aplicação dos algoritmos evolucionários inspirados na computação quântica na síntese de circuitos sequenciais. Os sistemas digitais sequenciais representam uma classe de circuitos que é capaz de executar operações em uma determinada sequência. Nos circuitos sequenciais, os valores dos sinais de saída dependem não só dos valores dos sinais de entrada como também do estado atual do sistema. Os requisitos cada vez mais exigentes quanto à funcionalidade e ao desempenho dos sistemas digitais exigem projetos cada vez mais eficientes. O projeto destes circuitos, quando executado de forma manual, se tornou demorado e, com isso, a importância das ferramentas para a síntese automática de circuitos cresceu rapidamente. Estas ferramentas conhecidas como ECAD (Electronic Computer-Aided Design) são programas de computador normalmente baseados em heurísticas. Recentemente, os algoritmos evolucionários também começaram a ser utilizados como base para as ferramentas ECAD. Estas aplicações são referenciadas na literatura como eletrônica evolucionária. Os algoritmos mais comumente utilizados na eletrônica evolucionária são os algoritmos genéticos e a programação genética. Este trabalho apresenta um estudo da aplicação dos algoritmos evolucionários inspirados na computação quântica como uma ferramenta para a síntese automática de circuitos sequenciais. Esta classe de algoritmos utiliza os princípios da computação quântica para melhorar o desempenho dos algoritmos evolucionários. Tradicionalmente, o projeto dos circuitos sequenciais é dividido em cinco etapas principais: (i) Especificação da máquina de estados; (ii) Redução de estados; (iii) Atribuição de estados; (iv) Síntese da lógica de controle e (v) Implementação da máquina de estados. O Algoritmo Evolucionário Inspirado na Computação Quântica (AEICQ) proposto neste trabalho é utilizado na etapa de atribuição de estados. A escolha de uma atribuição de estados ótima é tratada na literatura como um problema ainda sem solução. A atribuição de estados escolhida para uma determinada máquina de estados tem um impacto direto na complexidade da sua lógica de controle. Os resultados mostram que as atribuições de estados obtidas pelo AEICQ de fato conduzem à implementação de circuitos de menor complexidade quando comparados com os circuitos gerados a partir de atribuições obtidas por outros métodos. O AEICQ e utilizado também na etapa de síntese da lógica de controle das máquinas de estados. Os circuitos evoluídos pelo AEICQ são otimizados segundo a área ocupada e o atraso de propagação. Estes circuitos são compatíveis com os circuitos obtidos por outros métodos e em alguns casos até mesmo superior em termos de área e de desempenho, sugerindo que existe um potencial de aplicação desta classe de algoritmos no projeto de circuitos eletrônicos. / This thesis investigates the application of quantum inspired evolutionary algorithms in the synthesis of sequential circuits. Sequential digital systems represent a class of circuit that is able to execute operations in a particular sequence. In sequential circuits, the values of output signals not only depend on the values of input signals but also on the current state of the system. The increasingly high requirements regarding the functionality and performance of digital systems demand more efficient designs. The design of these circuits, when implemented manually, became slow and thus the importance of tools for automatic synthesis of circuits grew rapidly. These tools known as ECAD (Electronic Computer-Aided Design) are computer programs usually based on heuristics. Recently, evolutionary algorithms also began to be used as a basis in ECAD tools developing. These applications are referenced in literature as evolutionary electronics. The algorithms most commonly used in evolutionary electronics are genetic algorithms and genetic programming. This work presents a study of the application of quantum inspired evolutionary algorithms as a tool for automatic synthesis of sequential circuits. This class of algorithms uses the principles of quantum computing to improve the performance of evolutionary algorithms. Traditionally, the design of sequential circuits is divided into five main steps: (i) State machine specification; (ii) Reduction of states; (iii) State assignment; (iv) Control logic synthesis and (v) Implementation of the state machine. The proposed algorithm AEICQ is used in the state assignment design step. The choice of an optimal state assignment is treated in the literature as an issue still unresolved. The state assignment chosen for a particular state machine has a direct impact on the complexity of its control logic. The results show that the state assignment obtained by AEICQ in fact leads to the implementation of circuits of less complexity when compared with the ones generated from assignments obtained by other methods. The AEICQ is also used in the control logic synthesis of the state machine. The circuits evolved by AEICQ are optimized according to the area occupied and the propagation delay. These circuits are compatible with the circuits obtained by other methods and in some cases even higher in terms of area and performance, suggesting that there is a potential for application of this class of algorithms in the design of electronic circuits.

Les entités physiques prises en compte par les applications dites M2M dans les télécoms sont aujourd’hui de plus en plus hétérogènes. Le défi adressé par ce travail est donc l’intégration, et la configuration automatiques de toutes ces différentes variétés d’entités physiques d’une façon homogène dans les systèmes M2M, en généralisant les approches de configuration automatique déjà connues et utilisées pour les objets communicants numériques. Cette thèse présente un cadre théorique général et des mécanismes de base pour l’identification de modèles de telles entités physiques dans les systèmes d’information embarqués répartis, en englobant dans une même approche les équipements et les sous-ensembles de l’espace, faisant se rejoindre les points de vue ”internet des objets” et ”environnement interactif” dans une nouvelle vision unifiée de l’intelligence ambiante. Ce travail, motivé initialement par les applications à la gestion d’énergie domestique, cherche à intégrer au réseau local de la maison des entités physiques qui ont un impact énergétique mais ne sont dotés d’aucune connexion réseau, ce qui correspond à une extension qualitative du périmètre de l’Internet des Objets. Cette intégration se fait de manière tout à fait similaire à ce qui est fait classiquement pour des équipements numériques état de l’art, c’est-à-dire par des mécanismes de découverte et configuration spontanés. Ces mécanismes comportent les étapes suivantes : détection de la présence d’une entité physique par analyse de la coïncidence d’évènements significatifs reçus de capteurs ; sélection d’un premier modèle générique représentatif de l’entité physique détectée depuis une ontologie de référence en analysant des données reçues les capteurs ; création d’un composant logiciel représentant l’entité physique détectée, à partir du modèle sélectionné, et associant les capteurs et actionneurs utiles ; supervision et contrôle de l’entité cible par l’intermédiaire de ce composant logiciel ; mise à jour incrémentale du modèle de l’entité identifiée par analyse des données issues des capteurs associés. Ce travail est parti d’applications dans l’environnement de la maison, pour lesquelles il a été validé et mis en œuvre. Mais notre approche a vocation à être généralisée et étendue à des environnements comme les bâtiments ou la ville, en offrant suivant le même principe une infrastructure partagée pour toutes les applications M2M dans ces environnements / The physical entities which are taken into account by Machine to Machine (M2M) telecom applications are more and more heterogeneous. The challenge addressed by our research is the automatic integration and configuration of all these types of physical entities in M2M systems, with a homogeneous solution that generalizes self-configuration approaches used for networked digital devices. This thesis presents a general theoretical framework and basic mechanisms for the identification and configuration of such physical entity models in distributed embedded information systems. Our approach deals jointly with equipment and space entities encompassing the ”Internet of Things” (IoT) and ”interactive environment” viewpoints in a renewed interpretation of ambient intelligence. This work has been motivated initially by home energy management applications, trying to integrate into the Home Area Network all home entities that play a role in energy management, but do not have a networked interface of their own. This corresponds to a qualitative extension of the perimeter of the Home Area Network. This integration is achieved in a way similar to what is done for state of the art digital devices, through a spontaneous discovery and configuration mechanism, with the following stages: detection of the presence of a physical entity by analyzing the coincidence of significant events detected by sensors; selection of the first generic model corresponding to the detected physical entity from a reference ontology, on the basis of received sensors data; creation of a software component representing the detected physical entity, based on the selected model, associated with relevant sensors and actuators; provision of application interface for monitoring and control of the target entity through this intermediate software component; iterative update of the identified entity model on the basis of data from associated sensors. The proposed approach has been validated and implemented in home environments, but it is intended to be generalized and expanded to environments such as buildings or cities, offering a similarly shared infrastructure for all M2M applications in these environments