Ce travail présente la mise en œuvre du test par faisceau laser TPA pour l’étude de la sensibilité au phénomène SEB dans les diodes schottky en carbure de silicium. Le contexte de l’étude est décrit par un état de l’art du SEB sur les MOSFETs et Diodes en Silicium et en carbure de silicium. Une étude technologique et structurelle des composants en SiC a permis de dégager les avantages du SiC par rapport au Si conventionnel et a permis d’analyser les dégâts causés par le faisceau TPA. L’utilisation du montage expérimental sur la plateforme ATLAS dédié spécifiquement au test de matériaux à grand gap a permis de mettre en place une méthodologie de test sur des diodes schottky en SiC. L’efficacité de cette méthodologie est prouvée par l’obtention de résultats expérimentaux très originaux. La susceptibilité au SEB induit par la technique laser TPA a été démontrée. Les mesures SOA ont permis d’évaluer la robustesse des diodes schottky SiC face aux événements singuliers. Une modélisation analytique a été menée afin de comprendre la cause du mécanisme du SEB et la localisation des défauts induits par le faisceau TPA. / This work presents the implementation of the TPA laser beam testing to study the SEB phenomenon in silicon carbide Schottky diodes. The context of the study is described by a state of the art of SEB on Si and SiC MOSFETs and Diodes. Technological and structural study of SiC components has identified the benefits of SiC compared to conventional Si and permits to analyze the damage caused by the TPA beam. Using the experimental setup of the ATLAS platform dedicated specifically to test large gap materials has set up a test methodology on SiC Schottky diodes. The effectiveness of this methodology is demonstrated by obtaining original experimental results. Susceptibility to SEB induced by TPA laser technique has been demonstrated. SOA measurements were used to assess the robustness of SiC Schottky diodes to single event effects.An analytical modeling was conducted to understand the cause of the SEB mechanism and the location of defects induced by the TPA beam.

The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. As the device dimensions approach the fundamental limits, novel double/trigate device architecture such as FinFET is needed to guarantee the ultimate downscaling. Furthermore, Schottky barrier source/drain technology presents a promising solution to reducing the parasitic source/drain resistance in the FinFET. The ultimate goal of this thesis is to integrate Schottky barrier source/drain in FinFETs, with an emphasis on process development and integration towards competitive devices. First, a robust sidewall transfer lithography (STL) technology is developed for mass fabrication of Si-nanowires in a controllable manner. A scalable self-aligned silicide (SALICIDE) process for Pt-silicides is also developed. Directly accessible and uniform NWs of Ni- and Pt-silicides are routinely fabricated by combining STL and SALICIDE. The silicide NWs are characterized by resistivity values comparable to those of their thin–film counterparts. Second, a systematic experimental study is performed for dopant segregation (DS) at the PtSi/Si and NiSi/Si interfaces in order to modulate the effective SBHs needed for competitive FinFETs. Two complementary schemes SIDS (silicidation induced dopant segregation) and SADS (silicide as diffusion source) are compared, and both yield substantial SBH modifications for both polarities of Schottky diodes (i.e. φbn and φbp). Third, Schottky barrier source/drain MOSFETs are fabricated in UTB-SOI. With PtSi that is usually used as the Schottky barrier source/drain for p-channel SB-MOSFETs, DS with appropriate dopants leads to excellent performance for both types of SBMOSFETs. However, a large variation in position of the PtSi/Si interface with reference to the gate edge (i.e., underlap) along the gate width is evidenced by TEM. Finally, integration of PtSi NWs in FinFETs is carried out by combining the STL technology, the Pt-SALICIDE process and the DS technology, all developed during the course of this thesis work. The performance of the p-channel FinFETs is improved by DS with B, confirming the SB-FinFET concept despite device performance fluctuations mostly likely due to the presence of the PtSi-to-gate underlap. / QC 20100923

In dieser Arbeit wurden die Strom-Spannungs- und Kapazitäts-Spannungs-Kennlinien von Ag/n-GaAs(100) Schottky-Dioden untersucht, wobei die Kennlinien durch organische Zwischenschichten verschiedener Dicke modifiziert werden. Dazu wird der organische Halbleiter 3,4,9,10- Perylentetracarboxyldianhydrid (PTCDA) verwendet. Die PTCDA-Schichten werden mittels Organischer Molekularstrahldeposition (OMBD) hergestellt. Die Charakterisierung der Ag/PTCDA/GaAs-Dioden erfolgte sowohl in situ als auch ex situ.

The field of hybrid electronics of molecules and traditional semiconductors is deemed to be a realistic route towards possible use of molecular electronics. Such hybrid electronics finds its potential technological applications in nuclear detectors, near-infrared detectors, organic thin film transistors and gas sensors. Specifically Metal / organic / n-Silicon structures in this regard are mostly reported to have two regimes of charge transport at lower and higher applied voltages in such two terminal devices. The fact is mostly attributed to the change in conduction mechanism while moving from lower to higher applied voltages. These reports describe interactions between the semiconductors and molecules in terms of both transport and electrostatics but finding the exact potential distribution between the two components still require numerical calculations. The challenge in this regard is to give the exact relations and the transport models, towards practical quantification of charge transport properties of metal / organic / inorganic semiconductor devices. Some of the most exiting questions in this regard are; whether the existing models are sufficient to describe the device performances of the hybrid devices or some new models are needed? What type of charge carriers are responsible for conduction at lower and higher applied voltages? What is the source of such charge carriers in the sandwiched organic layer between the metal and inorganic semiconductors? How the transition applied voltage for the change in conduction mechanism is determined? What is the role of dopants in the organic layer semiconductors? What are the possible explanations for observed temperature effects in such devices? In present work the charge transport properties of metal / metal-phthalocyanine / n-Si structures with low (ND = 4×1014 cm-3), medium (ND = 1×1016 cm-3) and high (ND = 2×1019 cm-3) doped n-Si as injecting electrode and the effect of air exposure of the vacuum evaporated metal-phthalocyanine film in these structures is investigated. The results obtained through temperature dependent electrical characterizations of the structures suggest that in terms of dominant conduction mechanism in these devices Schottky-type conduction mechanism dominates the charge transport in low-bias region of these devices up to 0.8 V, 0.302 V and 0.15 V in case of low, medium and high doped n-Silicon devices. For higher voltages, in each case of devices, the space-charge-limited conduction, controlled by exponential trap distribution, is found to dominate the charge transport properties of the devices. The interface density of states at the CuPc / n-Si interface of the devices are found to be lower in case of lower work function difference at the CuPc / n-Si interface of the devices. The results also suggest that the work function difference at the CuPc / n-Si interface of these devices causes charge transfer at the interface and these phenomena results in formation of interface dipole. The width of the Schottky depletion region at the CuPc / n-Si interface of these devices is found to be higher with higher work function difference at the interface. The investigation of charge transport properties of Al / ZnPc / medium n-Si and Au / ZnPc / medium n-Si devices suggest that the Schottky depletion region formed at the ZnPc / n-Si interface of these devices determines the charge transport in the low-bias region of both the devices. Therefore, the Schottky-type (injection limited) and the space-charge-limited (bulk limited) conduction are observed in the low and the high bias regions of these devices, respectively. The determined width of the Schottky depletion region at the ZnPc / n-Si interface of these devices is found to be similar for both the devices, therefore, the higher work function difference at the metal / ZnPc interface of the devices has no influence on the Schottky depletion region formed at the ZnPc / n-Si interface of the devices. The similar diode ideality factor, barrier height and the width of the Schottky depletion region, determined for both of these devices, demonstrates that these device characteristics originate from ZnPc / n-Si interface of these devices. Therefore, the work function difference at the metal / ZnPc interface of these devices has no noticeable influence on the device properties originating from ZnPc / n-Si interface in these devices. The investigation of charge transport properties of Al / CuPc / low n-Si devices with and without air exposure of the CuPc film, before depositing metal contact demonstrate that Schottky-type conduction mechanism dominates the charge transport in these devices up to bias of 0.45 V in case devices with the air exposure, and up to 0.8 V in case devices without the air exposure. This decrease in the threshold voltage, for the change in conduction mechanism in the devices, is attributed to wider Schottky depletion width determined at the CuPc / n-Si interface of the devices without the air exposure of CuPc film. For higher voltage the space-charge-limited conduction controlled by exponential trap distribution, is found to dominate the charge transport properties of the devices without the air exposure of CuPc, and in case of devices with the air exposure of CuPc film, the SCLC is controlled by single dominating trap level probably introduced by oxygen impurities.

Silicon carbide (SiC) has higher breakdown field strength than silicon (Si), which enables thinner and more highly doped drift layers compared to Si. Consequently, the power losses can be reduced compared to Si-based power conversion systems. Moreover, SiC allows the power conversion systems to operate at high temperatures up to 250 oC. With such expectations, SiC is considered as the material of choice for modern power semiconductor devices for high efficiencies, high temperatures, and high power densities. Besides the material benefits, the typeof the power device also plays an important role in determining the system performance. Compared to the SiC metal-oxide semiconductor field-effect transistor (MOSFET) and bipolar junction transistor (BJT), the SiC junction field-effect transistor (JFET) is a very promising power switch, being a voltage-controlled device without oxide reliability issues. Its channel iscontrolled by a p-n junction. However, the present JFETs are not optimized yet with regard to on-state resistance, controllability of threshold voltage, and Miller capacitance. In this thesis, the state-of-the-art SiC JFETs are introduced with buried-grid (BG) technology.The buried grid is formed in the channel through epitaxial growth and etching processes. Through simulation studies, the new concepts of normally-on and -off BG JFETs with 1200 V blocking capability are investigated in terms of static and dynamic characteristics. Additionally, two case studies are performed in order to evaluate total losses on the system level. These investigations can be provided to a power circuit designer for fully exploiting the benefit of power devices. Additionally, they can serve as accurate device models and guidelines considering the switching performance. The BG concept utilized for JFETs has been also used for further development of SiC junctionbarrier Schottky (JBS) diodes. Especially, this design concept gives a great impact on high temperature operation due to efficient shielding of the Schottky interface from high electric fields. By means of simulations, the device structures with implanted and epitaxial p-grid formations, respectively, are compared regarding threshold voltage, blocking voltage, and maximum electric field at the Schottky interface. The results show that the device with an epitaxial grid can be more efficient at high temperatures than that with an implanted grid. To realize this concept, the device with implanted grid was optimized using simulations, fabricated and verified through experiments. The BG JBS diode clearly shows that the leakage current is four orders of magnitude lower than that of a pure Schottky diode at an operation temperature of 175 oC and 2 to 3 orders of magnitude lower than that of commercial JBS diodes. Finally, commercialized vertical trench JFETs are evaluated both in simulations andexperiments, while it is important to determine the limits of the existing JFETs and study their performance in parallel operation. Especially, the influence of uncertain parameters of the devices and the circuit configuration on the switching performance are determined through simulations and experiments. / Kiselkarbid (SiC) har en högre genombrottsfältstyrka än kisel, vilket möjliggör tunnare och mer högdopade driftområden jämfört med kisel. Följaktligen kan förlusterna reduceras jämfört med kiselbaserade omvandlarsystem. Dessutom tillåter SiC drift vid temperatures upp till 250 oC. Dessa utsikter gör att SiC anses vara halvledarmaterialet för moderna effekthalvledarkomponenter för hög verkningsgrad, hög temperature och hög kompakthet. Förutom materialegenskaperna är också komponenttypen avgörande för att bestämma systemets prestanda. Jämfört med SiC MOSFETen och bipolärtransistorn i SiC är SiC JFETen en mycket lovande component, eftersom den är spänningsstyrd och saknar tillförlitlighetsproblem med oxidskikt. Dess kanal styrs an en PNövergång. Emellertid är dagens JFETar inte optimerade med hänseende till on-state resistans, styrbarhet av tröskelspänning och Miller-kapacitans. I denna avhandling introduceras state-of-the-art SiC JFETar med buried-grid (BG) teknologi. Denna åstadkommes genom epitaxi och etsningsprocesser. Medelst simulering undersöks nya concept för normally-on och normally-off BG JFETar med blockspänningen 1200 V. Såvä statiska som dynamiska egenskper undersöks. Dessutom görs två fallstudier vad avser totalförluster på systemnivå. Dessa undersökningar kan vara värdefulla för en konstruktör för att till fullo utnyttja fördelarna av komponenterna. Dessutom kan resultaten från undersökningarna användas som komponentmodeller och anvisningar vad gäller switch-egenskaper. BG konceptet som använts för JFETar har också använts för vidareutveckling av så kallade JBS-dioder. Speciellt ger denna konstruktion stora fördelar vid höga temperature genom en effektiv skärmning av Schottkyövergången mot höga elektriska fält. Genom simuleringar har komponentstrukturer med implanterade och epitaxiella grids jämförst med hänseende till tröskelspänning, genombrottspänning och maximalt elektriskt fält vid Schottky-övergången. Resultaten visar att den epitaxiella varianten kan vara mer effektiv än den implanterade vid höga temperaturer. För att realisera detta concept optimerades en komponent med implanterat grid med hjälp av simuleringar. Denna component tillverkades sedan och verifierades genom experiment. BG JBS-dioden visar tydligt att läckströmmen är fyra storleksordningar lägre än för en ren Schottky-diod vid 175 oC, och två till tre storleksordningar lägre än för kommersiella JBS-dioder. Slutligen utvärderas kommersiella vertical trench-JFETar bade genom simuleringar och experiment, eftersom det är viktigt att bestämma gränserna för existerande JFETar och studera parallelkoppling. Speciellt studeras inverkan av obestämda parametrar och kretsens konfigurering på switchegenskaperna. Arbetet utförs bade genom simuleringar och experiment. / <p>QC 20150915</p>

Le sujet de thèse abordé dans ce mémoire s'inscrit dans la thématique du LE²P sur l'autonomie énergétique des réseaux de capteurs. Ce travail est axé sur la partie réception et redressement du transfert de l'énergie sans fil pour l'apport d'énergie à des capteurs nomades. Ce procédé n'est pas nouveau et prend son origine dans les années 1950. Les connaissances dans l'appréhension de ce processus sont nombreuses pour certains guides d'onde tels que le microruban. Mais la nécessité de perçages dans ces structures de guide d'onde peut être contraignante et causer des disparités dans une chaîne de construction. Ceci a motivé les travaux présentés dans ce mémoire qui utilise une technologie de guide d'onde coplanaire (CPW) peu exploitée. Ainsi, la conception d'un tel dispositif passe par la maîtrise d'un point de vue conceptuel et expérimental de cette technologie. La démarche consiste à utiliser ce guide d'onde coplanaire en minimisant les effets négatifs que peut engendrer ce dernier, pour s'abroger du besoin de perçage et faciliter la réalisation des dispositifs de redressement en limitant le nombre d'interactions humaines. / The thesis subject dealt in this report lies in the LE²P framework on the energy sustainability of wireless sensor network. This work is dedicated to the reception and rectifying part of wireless power transfer to give energy sustainability to nodes in a sensor network. This process is not new and originate from the years 1950. The behavior of this process is since well-known in several waveguide such technology as microstrip. But the need of drill in those waveguide circuit may be inconvenient and lead to discrepancy from one circuit to another. This was the motivational keystone to the work address in this report which uses coplanar waveguide (CPW) over microstrip. The conception of such devices goes through a good conceptual and experimental understanding of the waveguide technology. The approach in this document consists of using coplanar waveguide while minimizing its drawbacks, in order to avoid drilling in the substrate and ease the realization of the rectifying part by limiting the human interaction.

La diode Schottky SiC est un composant qui peut potentiellement remplacer la diode PiN Si dans les applications de puissance. Effectivement, la tenue en tension élevée, la faible résistivité, ainsi que l’indépendance de la température du courant de recouvrement rendent cette diode idéale pour les convertis- seurs de puissance DC/DC. Cependant, face à l’abondance des composants Si sur le marché, la diode Schottky rencontre une certaine réticence. Malgré les nombreuses démonstrations de systèmes électroniques de puissance réalisés, la fiabilité de cette technologie n’arrive pas à convaincre. Cette étude porte sur la caractérisation en régime statique sur une large gamme de températures et l’évaluation de la fiabilité en surcharge des diodes Schottky et JBS SiC-4H. La caractérisation en température a permis de proposer des modèles de la carac- téristique directe et inverse sur une gamme étendue de températures. Les tests en surcharge ont permis de comparer la fiabilité de diodes expérimentales et commerciales à fin de montrer la maturité de cette technologie. / The SiC Schottky diode can potentially replace the PiN diode in power appli- cations. As a matter of fact, high blocking voltage, low resistivity as well as temperature independence of the reverse recovery current make this diode ideal for DC/DC power converters. Nevertheless, Schottky diodes meet some reluc- tance before the abundance of PiN Si diodes. Despite the numerous demons- trations of power electronics systems, there are still some reliability aspects to improve. This study focuses on static characteristic in a large temperature range and reliability assessment of repetitive surge test of Schottky and JBS diodes. The measurements of forward and reverse characteristics yielded new models in a wide temperature range. Repetitive surge tests enabled us to com- pare the reliability of experimental and commercial diodes in order to prove the maturity of this technology.

The field of hybrid electronics of molecules and traditional semiconductors is deemed to be a realistic route towards possible use of molecular electronics. Such hybrid electronics finds its potential technological applications in nuclear detectors, near-infrared detectors, organic thin film transistors and gas sensors. Specifically Metal / organic / n-Silicon structures in this regard are mostly reported to have two regimes of charge transport at lower and higher applied voltages in such two terminal devices. The fact is mostly attributed to the change in conduction mechanism while moving from lower to higher applied voltages. These reports describe interactions between the semiconductors and molecules in terms of both transport and electrostatics but finding the exact potential distribution between the two components still require numerical calculations. The challenge in this regard is to give the exact relations and the transport models, towards practical quantification of charge transport properties of metal / organic / inorganic semiconductor devices. Some of the most exiting questions in this regard are; whether the existing models are sufficient to describe the device performances of the hybrid devices or some new models are needed? What type of charge carriers are responsible for conduction at lower and higher applied voltages? What is the source of such charge carriers in the sandwiched organic layer between the metal and inorganic semiconductors? How the transition applied voltage for the change in conduction mechanism is determined? What is the role of dopants in the organic layer semiconductors? What are the possible explanations for observed temperature effects in such devices? In present work the charge transport properties of metal / metal-phthalocyanine / n-Si structures with low (ND = 4×1014 cm-3), medium (ND = 1×1016 cm-3) and high (ND = 2×1019 cm-3) doped n-Si as injecting electrode and the effect of air exposure of the vacuum evaporated metal-phthalocyanine film in these structures is investigated. The results obtained through temperature dependent electrical characterizations of the structures suggest that in terms of dominant conduction mechanism in these devices Schottky-type conduction mechanism dominates the charge transport in low-bias region of these devices up to 0.8 V, 0.302 V and 0.15 V in case of low, medium and high doped n-Silicon devices. For higher voltages, in each case of devices, the space-charge-limited conduction, controlled by exponential trap distribution, is found to dominate the charge transport properties of the devices. The interface density of states at the CuPc / n-Si interface of the devices are found to be lower in case of lower work function difference at the CuPc / n-Si interface of the devices. The results also suggest that the work function difference at the CuPc / n-Si interface of these devices causes charge transfer at the interface and these phenomena results in formation of interface dipole. The width of the Schottky depletion region at the CuPc / n-Si interface of these devices is found to be higher with higher work function difference at the interface. The investigation of charge transport properties of Al / ZnPc / medium n-Si and Au / ZnPc / medium n-Si devices suggest that the Schottky depletion region formed at the ZnPc / n-Si interface of these devices determines the charge transport in the low-bias region of both the devices. Therefore, the Schottky-type (injection limited) and the space-charge-limited (bulk limited) conduction are observed in the low and the high bias regions of these devices, respectively. The determined width of the Schottky depletion region at the ZnPc / n-Si interface of these devices is found to be similar for both the devices, therefore, the higher work function difference at the metal / ZnPc interface of the devices has no influence on the Schottky depletion region formed at the ZnPc / n-Si interface of the devices. The similar diode ideality factor, barrier height and the width of the Schottky depletion region, determined for both of these devices, demonstrates that these device characteristics originate from ZnPc / n-Si interface of these devices. Therefore, the work function difference at the metal / ZnPc interface of these devices has no noticeable influence on the device properties originating from ZnPc / n-Si interface in these devices. The investigation of charge transport properties of Al / CuPc / low n-Si devices with and without air exposure of the CuPc film, before depositing metal contact demonstrate that Schottky-type conduction mechanism dominates the charge transport in these devices up to bias of 0.45 V in case devices with the air exposure, and up to 0.8 V in case devices without the air exposure. This decrease in the threshold voltage, for the change in conduction mechanism in the devices, is attributed to wider Schottky depletion width determined at the CuPc / n-Si interface of the devices without the air exposure of CuPc film. For higher voltage the space-charge-limited conduction controlled by exponential trap distribution, is found to dominate the charge transport properties of the devices without the air exposure of CuPc, and in case of devices with the air exposure of CuPc film, the SCLC is controlled by single dominating trap level probably introduced by oxygen impurities.:1 INTRODUCTION 3 1.1 Organic / Inorganic Semiconductor Interfaces 5 1.2 Organic / Metal Interfaces 6 1.3 Organic Material / Semiconductor Interfaces 6 1.4 Interface Dipoles at Organic / Inorganic Interfaces 7 1.5 Objectives of the Study 9 1.6 Research Methodology 10 1.7 References 12 2 BASIC CONCEPTS OF ORGANIC ELECTRONICS 16 2.1 Localized and Delocalized Orbital in Organic Semiconductors 16 2.2 Operating principle of some basic organic / inorganic devices 19 2.3 Electronic Structure of an Organic Solid 20 2.4 Validity Limits of band model and the tunneling model 21 2.5 Dark Electric Conduction 23 2.6 Injection of Carriers from Electrodes 24 2.7 References 26 3 MATERIALS AND DEVICE FABRICATION 27 3.1 Assembly of the hybrid organic / inorganic structures 27 3.2 The Vacuum Systems for Device Fabrication 27 3.3 The n-Si substrates 29 3.4 The Organic semiconductors; CuPc and ZnPc 30 3.5 Sample Fabrication Procedures 32 3.5.1 Experimental Details of Samples Prepared at PCRET labs 32 3.5.2 Experimental details of samples Prepared at TU Chemnitz labs 33 3.6 References 34 4 METHODS FOR DATA ANALYSIS 35 4.1 The Dominant Conduction Mechanisms in the Devices 35 4.1.1 Schottky-type Conduction 35 4.1.1.1 The Standard Characterization Technique 38 4.1.1.2 The R. J. Bennett Technique 39 4.1.1.3 The Cheung and Cheung Technique 42 4.1.1.4 The H. Norde Technique 42 4.1.2 Space Charge Limited Conduction (SCLC) 43 4.1.3 The MIM Models to Determine Dominant Conduction Mechanism 44 4.2 Interface State Energy Distribution 46 4.3 References 48 5 CHARGE TRANSPORT PROPERTIES OF Al / CuPc / n-Si DEVICES IN DARK 50 5.1 Charge Transport Properties of Al / CuPc / low-doped n-Si Devices 51 5.1.1 Interface State Energy Distribution 65 5.2 Charge Transport Properties of Al / CuPc / medium-doped n-Si Devices 67 5.3 Charge Transport Properties of Al / CuPc / High-doped n-Si Devices 75 5.3.1 Charge Transport Properties of Al / CuPc / High-doped n-Si Devices as Metal-Insulator-Metal Structures 82 5.4 Summary 85 5.5 Final Remarks 87 5.6 References 88 6 INFLUENCE OF TOP METAL CONTACT ON CHARGE TRANSPORT PROPERTIES META / ZnPc / n-Si DEVICES IN DARK 89 6.1 Charge Transport Properties of Metal / ZnPc / Medium-doped n-Si Devices 89 6.2 Interface State Energy Distribution 99 6.3 Summary 100 6.4 Final Remarks 101 6.5 References 103 7 INFLUENCE AIR EXPOSURE ON THE CHARGE TRANSPORT PROPERTIES OF Al / CuPc / n-Si DEVICES 104 7.1 Charge Transport Properties of Al / CuPc / low n-Si Devices With (or) without air exposure of CuPc film 104 7.2 Summary 115 7.3 Final Remarks 116 7.4 References 117 8 CONCLUSIONS 118 8.1 Scope of Future Work 120 Index of Figures 121 Curriculum Vitae and List of Publications 125

With the introduction of Internet of Things (IoT) technology in several sectors, wireless, reliable, and energy-saving communication in distributed sensor networks are more important than ever. Thereby, wake-up technologies are becoming increasingly important as they significantly contribute to reducing the energy consumption of wireless sensor nodes. In an indoor environment, the use of wireless sensors, in general, is more challenging due to signal fading and reflections and needs, therefore, to be critically investigated. This paper discusses the performance analysis of wakeup receiver (WuRx) architectures based on two low frequency (LF) amplifier approaches with regard to sensitivity, power consumption, and package error rate (PER). Factors that affect systems were compared and analyzed by analytical modeling, simulation results, and experimental studies with both architectures. The developedWuRx operates in the 868MHz band using on-off-keying (OOK) signals while supporting address detection to wake up only the targeted network node. By using an indoor setup, the signal strength and PER of received signal strength indicator (RSSI) in different rooms and distances were determined to build a wireless sensor network. The results show a wake-up packets (WuPts) detection probability of about 90% for an interior distance of up to 34 m.

No description available.