In this thesis, we will investigate the degradation of the Low-Temperature-Polycrystalline-Silicon TFTs(LTPS TFTS) under the electrical stress. The devices are offer by Chi Mei Optoelectronics. The two mechanisms of the electrical stress are AC and DC stress. On the AC stress, there are some phenomena which cannot be completely explained by typical NBTI mechanism in the experiment. In addition to NBTI, we suggest that the self-heating effect might be involved, because the self-heating effect could rise channel temperature and cause the dissociation of the Si-H bonds at the poly-Si/SiO2 interface due to the Joule heating. We also compare pulse to give on the degradation difference of different place. On the DC stress, we show the stress drain voltage dependence of on-current and threshold voltage degradation, in which the stress gate voltage was fixed at -15V and stress time was 2154 s. The electric measurements of forward and reverse modes were employed to analyze the experimental data. The anomalous negative bias temperature instability degradation of poly-Si TFTs was investigated.

We have carried out a theoretical and an experimental study of thermal effects arising in bulk high-Tc superconductors. The theoretical study has allowed us to predict the self-heating behaviour. We have calculated the temperature evolution. We have shown the existence of a forbidden temperature window, and we have determined the analytical expression of a threshold field (Htr2) separating the « middle» and the «high» dissipation state . From a numerical modelling of a short cylinder, we have determined the time and spatial dependance of dissipated power and temperature within the sample. We have shown that the temperature rise is the highest along the corner location where the dissipated power is maximum. We have designed and constructed a susceptometer for characterizing large bulk superconductors (f →32 mm). The susceptometer allows a small temperature gradient (< 0.1K) to be achieved in the presence of large heating rates. It allows large AC and DC fields to be applied simultaneously, and was upgraded to measure simultaneously local temperatures and magnetic inductions. We have determined the heat transfer occuring in the susceptometer chamber. Magneto-thermal measurements with this system can be carried out with a high sensitivity and are found to be in very good agreement with the theoretical predictions. This work underlines the importance of the cooling conditions that can affect the distribution of the magneto-thermal properties within the superconductor.

In this paper, we propose a novel thin film MOSFET with source/drain tie and discontinuously block oxide layers. Improving process is very important, when the gate length of SOI MOSFET is reduced. To overcome the misalignment problem, we use self-aligned technology to fabricate this device. In addition, the device has discontinuously block oxide layers; they can improve short channel effects, reduce the parasitic capacitance, and decrease the leakage current cause by P-N junction between source/drain and body regions. They also supply two pass ways to eliminate carriers and heat which generated by impact ionization resulting in suppression of floating-body effect and self-heating effect. In addition, these two pass ways can be seen as the parallel equivalent resistance results in a reduced series resistance and an increased drain saturation current. According to the ISE TCAD 10.0 simulation results, the discontinuously block oxide layers can not only improve the short channel effects, but also eliminate the floating-body effect and diminish the self-heating effect because of the pass ways.

Non traduit / The introduction of nanometer technologies, has allowed the semiconductor industry to create nanoscale devices in combination with gigascale complexity. However, new technologies bring with them new challenges. In the era of large systems embedded in a single System-On-Chip and fabricated in continuously shrinking technologies, it is important to test and ensure fault-free operation of the whole system. The cost involved in semiconductor test has been steadily growing and testing techniques for integrated circuits are today facing many exciting and complex challenges. Although important advances have been made, existing test solutions are still unable to exhaustively cover all types of defects in advanced technology nodes. Consequently, innovative solutions are required to cope with new failure mechanisms under the constraints of higher density and complexity, cost and time to market pressure, product quality level and usage of low cost test equipment.The work of this thesis is focused on the development of silicon test and characterization methodologies that aid in the accurate detection and resolution of issues that may arise due to variability, manufacturing defects, wear-out or interference. A wide spectrum of these challenges has been addressed from a test perspective to ensure that the availability of effective test solutions does not become a bottleneck in the path towards further scaling. Additionally the advances and innovations introduced in the myriad domains of electronic design, reliability management, manufacturing process improvements etc. that call for the development of advanced, modular and agile test methodologies have been effectively covered within the scope of this work.This thesis presents the significant contributions made for enabling resolution of state of the art industrial test challenges via the design and implementation of novel test strategies (targeting the 28nm FDSOI technology node) for:•Detection & diagnosis of timing faults in standard cells.•Analysis of Setup and Hold margins within silicon.•Verification & reliability analysis of innovative test structures.•Analysis of on-chip self heating.•Enabling characterization and performance evaluation of high speed digital IPs.

Devido às dimensões cada vez mais reduzidas dos transistores e a utilização de novos materiais com baixa condutividade térmica, o desempenho de transistores avançados é afetado pelo autoaquecimento. Dispositivos sob os efeitos de autoaquecimento sofrem um aumento da sua temperatura, fazendo com que a mobilidade seja reduzida, além de comprometer a confiabilidade e gerar atrasos de sinal, trazendo impactos na eficiência de circuitos analógicos, bem como afetando o desempenho de circuitos digitais. Apesar da relevância do fenômeno, muitos estudos não o levam em consideração devido à dificuldade de sua verificação, uma vez que os métodos utilizados para transistores avançados requerem estruturas ou equipamentos especiais, que são raramente disponíveis. Dessa forma, três novas técnicas são desenvolvidas neste trabalho com o objetivo de viabilizar o estudo do efeito utilizando estruturas convencionais e medidas em corrente contínua: (i) a condutância de saída média; (ii) o método da assinatura na eficiência do transistor; (iii) a estimativa da resistência térmica utilizando somente medidas em corrente contínua. Os dois primeiros métodos são focados em uma análise qualitativa do autoaquecimento, permitindo uma verificação preliminar eficiente da presença e relevância do efeito, enquanto o terceiro método permite a extração da resistência térmica a partir do inverso da eficiência do transistor utilizando um processo iterativo, consequentemente possibilitando a obtenção do aumento da temperatura do canal devido ao autoaquecimento, com boa precisão e maior simplicidade em relação aos métodos disponíveis na literatura (com erro máximo menor que 6% para transistores de múltiplas portas em relação ao método de medidas pulsadas). Com essas técnicas, são feitas comparações da elevação de temperatura do canal entre transistores de múltiplas portas (também chamados de FinFET ou transistores 3D) e transistores de silício sobre isolante com camada de silício e óxido enterrado extremamente finos (SOI UTBB), usando simulações tridimensionais para obter condições similares de potência. Em dispositivos com menores comprimentos de canal, os FinFETs apresentaram temperaturas cerca de 60 K acima dos UTBBs. / Due to the reduction of devices\' dimensions and the use of new materials with low thermal conductivity, self-heating affects the performances of advanced transistors. Devices under self-heating effects suffer an increase of their temperature, causing mobility reduction, besides compromising reliability and generating signal delays, bringing impacts to the efficiency of analog circuits, and affecting the performance of digital circuits. Despite the relevance of the phenomenon, many studies do not consider it, given the difficulty to assess it, since the methods used for advanced transistors require special structures or equipment, which are rarely available. Hence, three new techniques are developed in this work, with the objective of permitting the study of the effect utilizing conventional structures and direct current measurements: (i) the mean output conductance method; (ii) the signature in the transistor efficiency method; (iii) the thermal resistance estimative using only direct current measurements. The first two methods are focused on a qualitative analysis of the self-heating, allowing an efficient preliminary verification of the presence and relevance of the effect, while the last allows the extraction of the thermal resistance from the inverse of the transistor efficiency through an iterative process, consequently making it possible to obtain the temperature rise in the channel due to the self-heating with a good precision and greater simplicity when compared to other methods available in the literature (with maximum error smaller than 6% for multiple gate transistors when compared to the pulsed method). With these techniques, comparisons between multiple gate transistors (also known as FinFET or 3D transistors) and silicon-on-oxide with ultra-thin body and buried oxide (SOI UTBB) are performed, utilizing three-dimensional simulations to obtain similar power conditions. In devices with smaller channel length, FinFETs presented temperatures approximately 60 K above the UTBBs.

Devido às dimensões cada vez mais reduzidas dos transistores e a utilização de novos materiais com baixa condutividade térmica, o desempenho de transistores avançados é afetado pelo autoaquecimento. Dispositivos sob os efeitos de autoaquecimento sofrem um aumento da sua temperatura, fazendo com que a mobilidade seja reduzida, além de comprometer a confiabilidade e gerar atrasos de sinal, trazendo impactos na eficiência de circuitos analógicos, bem como afetando o desempenho de circuitos digitais. Apesar da relevância do fenômeno, muitos estudos não o levam em consideração devido à dificuldade de sua verificação, uma vez que os métodos utilizados para transistores avançados requerem estruturas ou equipamentos especiais, que são raramente disponíveis. Dessa forma, três novas técnicas são desenvolvidas neste trabalho com o objetivo de viabilizar o estudo do efeito utilizando estruturas convencionais e medidas em corrente contínua: (i) a condutância de saída média; (ii) o método da assinatura na eficiência do transistor; (iii) a estimativa da resistência térmica utilizando somente medidas em corrente contínua. Os dois primeiros métodos são focados em uma análise qualitativa do autoaquecimento, permitindo uma verificação preliminar eficiente da presença e relevância do efeito, enquanto o terceiro método permite a extração da resistência térmica a partir do inverso da eficiência do transistor utilizando um processo iterativo, consequentemente possibilitando a obtenção do aumento da temperatura do canal devido ao autoaquecimento, com boa precisão e maior simplicidade em relação aos métodos disponíveis na literatura (com erro máximo menor que 6% para transistores de múltiplas portas em relação ao método de medidas pulsadas). Com essas técnicas, são feitas comparações da elevação de temperatura do canal entre transistores de múltiplas portas (também chamados de FinFET ou transistores 3D) e transistores de silício sobre isolante com camada de silício e óxido enterrado extremamente finos (SOI UTBB), usando simulações tridimensionais para obter condições similares de potência. Em dispositivos com menores comprimentos de canal, os FinFETs apresentaram temperaturas cerca de 60 K acima dos UTBBs. / Due to the reduction of devices\' dimensions and the use of new materials with low thermal conductivity, self-heating affects the performances of advanced transistors. Devices under self-heating effects suffer an increase of their temperature, causing mobility reduction, besides compromising reliability and generating signal delays, bringing impacts to the efficiency of analog circuits, and affecting the performance of digital circuits. Despite the relevance of the phenomenon, many studies do not consider it, given the difficulty to assess it, since the methods used for advanced transistors require special structures or equipment, which are rarely available. Hence, three new techniques are developed in this work, with the objective of permitting the study of the effect utilizing conventional structures and direct current measurements: (i) the mean output conductance method; (ii) the signature in the transistor efficiency method; (iii) the thermal resistance estimative using only direct current measurements. The first two methods are focused on a qualitative analysis of the self-heating, allowing an efficient preliminary verification of the presence and relevance of the effect, while the last allows the extraction of the thermal resistance from the inverse of the transistor efficiency through an iterative process, consequently making it possible to obtain the temperature rise in the channel due to the self-heating with a good precision and greater simplicity when compared to other methods available in the literature (with maximum error smaller than 6% for multiple gate transistors when compared to the pulsed method). With these techniques, comparisons between multiple gate transistors (also known as FinFET or 3D transistors) and silicon-on-oxide with ultra-thin body and buried oxide (SOI UTBB) are performed, utilizing three-dimensional simulations to obtain similar power conditions. In devices with smaller channel length, FinFETs presented temperatures approximately 60 K above the UTBBs.

This work investigates the influence of gate-induced floating body effect (GIFBE) on negative bias temperature instability (NBTI) in partial depleted silicon-on-insulator p-type metal-oxide-semiconductor field effect transistors (PD-SOI p-MOSFETs). The results indicate GIFBE causes a reduction in the electrical oxide field, leading to an underestimate of NBTI degradation. This can be attributed to the electrons tunneling from the process-induced partial n+ poly gate, and at higher voltages is dominated by the proposed anode electron injection (AEI) model. Moreover, when introducing the mechanical strain to PD-SOI p-MOSFETs result in decreasing the NBTI degradation for BC and FB devices, because increase of effective mass of hole and barrier height to decrease the probability of reaction of NBTI. The degradation of NBTI on FB device less than BC device because of strain-induced band gap narrowing to substrate and p+ poly gate, resulting in the rising of rate of impact ionization in AEI model to increase the accumulation of electrons on body. After that, giving the drain voltage in NBTI stress, the threshold voltage, Vth, shift decreases as drain voltage (VD) rising within the stress condition of VD= -1V. This phenomenon can be attributed to the shorter effective reaction time of hole and Si-H bonds after applying drain voltage during NBTI stress. However, beyond the condition at VD= -1V, the Vth shift rises as the drain voltage increasing. This behavior is resulted from the self-heating effect induced by the higher stress VD to increase the degradation of NBTI.

In this thesis, a bottom gate TFT with smart body tie device is realized, For a PDSOI devices, which usually uses large layout areas of body ties, and it has self-heating effect resulting from the buried oxide between the silicon film and substrate, which has a lower thermal conductivity. In order to suppress the short channel effect and reduce leakage current, we dug out in advance the PN junction to formed the ultra thin film body, besides, in order to reduce Miller's capacitance effect we formed enough thickness of spacer at both sides of the bottom gate and let the source and the drain region do not too closer nearly. According to the simulation results of ISE TCAD, the TFT with smart body tie device can alleviate self-heating effect and can achieve kink-free at output characteristic curve due to hot carriers by impact ionization and enhance the breakdown voltage of the device. Although the drive current of the TFT device lower than conventional TFT due to the parasitic resistance in the body region, the output characteristic curve is smooth in the saturation zone; the device suppress the short channel effect and improve the performance of the device due to most areas of PN junction are dug out.

In this thesis, we present a new Poly - Si TFT process method to overcome Self - heating effect and Floating body effect. The main drawback of a conventional Poly - Si TFT is the existence of self - heating effect and floating body effect. The self - heating effect leads to drain current reduced and the floating body effect leads to premature device breakdown and kink effects. Here, we utilize all kinds of different isolation technologies to form non - continuing buried layer. Between the non - continuing buried layer there are pass ways, which contact the active region and the substrate directly. Because of conventional LOCOS isolation technology has longer bird¡¦s beak, the familiar method of SILO and PBL isolation technologies are used to reduce bird¡¦s beak. Also, we use STI isolation technology to build up non - continuing buried layer, which can control the width of pass way more easily. It is proved from the measurement that the pass way can slow down the self - heating effect and the floating body effect successfully.

This paper investigates the device behavior of a novel pseudo tri-gate ultrathin channel vertical MOSFET with source/drain tie (S/D tie), the PTG-SDT VMOS. The S/D tie (SDT) of this novel device circumvents short channel effect (SCEs). A double- surround-gate (the mid-gate and the spacer gate) is also presented to investigate the effect of S/D tie. According to the 2D simulation, three kinds of pseudo vertical MOSFETs are now proposed. The first one is to investigate the device characteristics of the new PTG-SDT VMOS. Our proposed structure also mitigates self-heating effect (SHEs), thereby enhancing the drain drive current and the thermal stability. Owing to its ultrathin channel (Tsi = 10 nm), the PTG-SDT VMOS has a very low subthreshold swing of 60 mV/dec, for channel lengths from 90 nm down to 40 nm. It is also found to control drain-induced barrier lowing (DIBL) and to have an excellent Gm of 4.5 mS/£gm at the channel length 40 nm. The second one, we proposed the ultrathin channel pseudo tri-gate vertical MOSFET with natural source/drain tie (NSDT), the big source/drain tie (BSDT), the SDT and the without source/drain tie (WSDT) VMOS. The PTG VMOS of this novel structure circumvents short channel effects (SCEs). A new natural S/D tie (N-SDT) is also presented to investigate of the PTG VMOS. According to 2D simulation, the PTG-NSDT also show the excellent thermal dissipated such as the lattice temperature in the drain-on-top configuration and drain-on-bottom configuration were improved 47% and 66% respectively, thereby enhancing the ON-state and OFF-state current ratio. In addition, the dependence of GIDL current on body bias and temperature is characterized and discussed when the source and drain interchanged. Although the PTG VMOS keep the double-surround-gate and S/D tie structure, the design flow is more simplify even increase the drain drive current and immunity the SHEs.