SRAM-Based FPGAs provide valuable computation resources and reconfigurability; however, FPGA designs can fail during operation due to ionizing radiation. As an SRAM-based device, these FPGAs store operation-critical information in configuration RAM, or CRAM. Testing, through radiation tests, can be performed to prove the effectiveness of SEU mitigation techniques by comparing the SEU sensitivity of an FPGA design with and without the mitigation techniques applied. However, radiation testing is expensive and time-consuming. Another method for SEU sensitivity testing is through fault injection. This work describes a low-cost fault injection platform for evaluating the SEU sensitivity of an SRAM-based FPGA design by emulating faults in the device CRAM through partial reconfiguration. This fault injection platform, called the TURTLE, is designed to gather statistically significant amounts of fault injection data to test and validate SEU mitigation techniques for SRAM-based FPGAs. Across multiple fault injection campaigns, the TURTLE platform was used to inject more than 600 million faults to test SEU mitigation techniques, estimate design SEU sensitivity, and validate radiation test data through fault injection.

With the relentless shrinking of the minimum feature size of VLSI Integrated Circuits (ICs), reduction in operating voltages and increase in operating frequencies, VLSI circuits are becoming more vulnerable to radiation strikes. As a result, this problem is now important not only for space and military electronics but also for consumer ICs. Thus, the design of radiation-hardened circuits has received significant attention in recent times. This thesis addresses the radiation hardening issue for VLSI ICs. In particular, circuit techniques are presented to protect against Single Event Transients (SETs). Radiation hardening has long been an area of research for memories for space and military ICs. In a memory, the stored state can ip as a result of a radiation strike. Such bit reversals in case of memories are known as Single Event Upsets (SEUs). With the feature sizes of VLSI ICs becoming smaller, radiation-induced glitches have become a source of concern in combinational circuits also. In combinational circuits, if a glitch due to a radiation event occurs at the time the circuit outputs are being sampled, it could lead to the propagation of a faulty value. The current or voltage glitches on the nodes of a combinational circuit are known as SETs. When an SET occurring on a node of a logic network is propagated through the gates of the network and is captured by a latch as a logic error, it is transformed to an SEU. The approach presented in this thesis makes use of Code Word State Preserving (CWSP) elements at each ip-op of the design, along with additional logic to trigger a recomputation in case a SET induced error is detected. The combinational part of the design is left unaltered. The CWSP element provides 100% SET protection for glitch widths up to min{(Dmin-D1)/2, (Dmax-D2)/2}, where Dmin and Dmax are the minimum and maximum circuit delay respectively. D1 and D2 are extra delays associated with the proposed SET protection circuit. The CWSP circuit has two inputs - the flip flop output signal and the same signal delayed by a quantity 6. In case an SET error is detected at the end of a clock period i, then the computation is repeated in clock period i+1, using the correct output value, which was captured by the CWSP element in the ith clock period. Unlike previous approaches, the CWSP element is i) in a secondary computational path and ii) the CWSP logic is designed to minimally impact the critical delay path of the design. It was found through SPICE simulations that the delay penalty of the proposed approach (averaged over several designs) is less than 1%. Thus, the proposed technique is applicable for high-speed designs, where the additional delay associated with the SET protection must be kept at a minimum.

The high resolution silicon Pixel detector is critical in event vertex reconstruction and in particle track reconstruction in the ATLAS detector. During the pixel data taking operation, some modules (Silicon Pixel sensor +Front End Chip+ Module Control Chip (MCC)) go to an auto-disable state, where the Modules don't send the data for storage. Modules become operational again after reconfiguration. The source of the problem is not fully understood. One possible source of the problem is traced to the occurrence of single event upset (SEU) in the MCC. Such a module goes to either a Timeout or Busy state. This report is the study of different types and rates of errors occurring in the Pixel data taking operation. Also, the study includes the error rate dependency on Pixel detector geometry.

The Versal Adaptive Compute Acceleration Platform (Versal ACAP) is a system-on-chip (SoC) developed by AMD Xilinx. To help protect the programmable logic from soft errors, the configuration needs to be constantly checked and repaired through a process called scrubbing. This thesis provides a methodology for scrubbing the configuration over JTAG. The scrubber uses two platform device image (PDI) files, one to read the configuration and one to send corrected frames. The methodology is characterized to determine the time it takes to completely scrub the configuration. The designed scrubber was able to scrub the VM1802 in 11.5 seconds, or 41.6 Mbits/second, when the JTAG interface was operated at 50MHz.

This work presents on-orbit experiments conducted to validate SEU mitigation and detection techniques on FPGA devices and to measure SEU rates in FPGAs and SDRAM. These experiments were designed for the Cibola Flight Experiment Satellite (CFESat), which is an operational technology pathfinder satellite built around 9 Xilinx Virtex FPGAs and developed at Los Alamos National Laboratory. The on-orbit validation experiments described in this work have operated for over four thousand FPGA device days and have validated a variety of SEU mitigation and detection techniques including triple modular redundancy, duplication with compare, reduced precision redundancy, and SDRAM and FPGA block memory scrubbing. Regional SEU rates and the change in CFE's SEU rate over time show the measurable, expected effects of the South Atlantic Anomaly and the cycle of solar activity on CFE's SEU rates. The results of the on-orbit experiments developed for this work demonstrate that FPGA devices can be used to provide reliable, high-performance processing to space applications when proper SEU mitigation strategies are applied to the designs implemented on the FPGAs.

No fault found (NFF) errors, i.e. errors which origin has not been established, irregularly occur in electronic devices. The actual cause of such errors varies but one, possibly more prominent, source for these soft errors is atmospheric radiation. The overarching aim of this thesis is to demonstrate: 1) the importance of keeping the atmospheric radiation environment in mind when designing robust airborne systems, 2) how to take this environment into consideration when applying mitigation techniques which may drastically reduce the risk of SEEs (Single Event Effects) which can cause NFF errors. To achieve these goals, Part 1 of this thesis describes how cosmic rays affect electronics (i.e. what kind of errors may be induced), which types of devices are susceptible to radiation, and why this subject is of extra importance for airborne systems. In addition, soft error mitigation techniques, which may be applied at different design levels to reduce the soft error rate (SER) or the impact of soft errors, are also presented. The aim is further corroborated by Part 2. Five subsystems of a modern aircraft are studied and real examples of failures potentially induced by atmospheric radiation are presented. For each of the five systems, all errors that have been reported for these (in the past few years) have been studied, and the number of errors found to be potentially induced by cosmic radiation has been listed and compared to number of expected soft errors based on calculations and previous experimental tests.

Technology scaling of CMOS devices has made the integrated circuits vulnerable to single event radiation effects. Scaling of CMOS Static RAM (SRAM) has led to denser packing architectures by reducing the size and spacing of diffusion nodes. However, this trend has led to the increase in charge collection and sharing effects between devices during an ion strike, making the circuit even more vulnerable to a specific single event effect called the single event multiple-node upset (SEMU). In nanometer technologies, SEMU can easily disrupt the data stored in the memory and can be more hazardous than a single event single-node upset. During the last decade, most of the research efforts were mainly focused on improving the single event single-node upset tolerance of SRAM cells by using novel circuit techniques, but recent studies relating to angular radiation sensitivity has revealed the importance of SEMU and Multi Bit Upset (MBU) tolerance for SRAM cells. The research focuses on improving SEMU tolerance of CMOS SRAM cells by using novel circuit and layout level techniques. A novel SRAM cell circuit & layout technique is proposed to improve the SEMU tolerance of 6T SRAM cells with decreasing feature size, making it an ideal candidate for future technologies. The layout is based on strategically positioning diffusion nodes in such a way as to provide charge cancellation among nodes during SEMU radiation strikes, instead of charge build-up. The new design & layout technique can improve the SEMU tolerance levels by up to 20 times without sacrificing on area overhead and hence is suitable for high density SRAM designs in commercial applications. Finally, laser testing of SRAM based configuration memory of a Xilinx Virtex-5 FPGA is performed to analyze the behavior of SRAM based systems towards radiation strikes.

Inaug. Diss. - Leipzig. / Includes bibliographical references.

The purpose of this study was to determine the level of self-directed learning readiness among undergraduate students at Saudi Electronic University in Saudi Arabia. This study also investigated whether there were relationships between the level of self-directed learning readiness and selected demographic variables such as gender, college, and age in the sample of undergraduate students in Saudi Arabia. This research utilized a quantitative design. The Self-directed Learning Readiness Scale (SDLRS), which was developed by Guglielmino, was utilized to measure the level of self-directed learning readiness among undergraduate students at Saudi Electronic University on the Riyadh campus. A total of 203 undergraduate students completed the SDLRS questionnaire. Results were that the mean score of SDLRS among undergraduate students at Saudi Electronic University in Riyadh campus included 64 (32.52%) were students with below average 58-201 scores; 71 (34.98%) students with average 202-226 scores; and 68 (33.50%) were students with above average 227-290 scores. age. However, there was a significant difference between the colleges. The results of the Tukey post-hoc test indicated that significant differences existed between the Sciences and Theoretical Studies College students and the Administration and Finance College and Computation and Information College students. The Sciences and Theoretical Studies College scored significantly lower than the other two colleges.

Les DRAMs sont des mémoires fréquemment utilisées dans les systèmes aéronautiques et spatiaux. Leur tenue aux radiations doit être connue pour satisfaire les exigences de fiabilité des applications critiques. Ces évaluations sont traditionnellement faites en accélérateur de particules. Cependant, les composants se complexifient avec l'intégration technologique. De nouveaux effets apparaissent, impliquant l'augmentation des temps et des coûts de test. Il existe une solution complémentaire, le laser impulsionnel, qui déclenche des effets similaires aux particules. Grâce à ces deux moyens de test, il s'est agi d'étudier les principaux modes de défaillance des DRAMs liés aux radiations : les SEUs (Single Event Upset) dans les plans mémoire, et les SEFIs (Single Event Functional Interrupt) dans les circuits périphériques. L'influence des motifs de test sur les sensibilités SEUs et SEFIs selon la technologie utilisée a ainsi été démontrée. L'étude a de plus identifié l'origine des SEFIs les plus fréquents. En outre, des techniques de test laser ont été développées pour quantifier les surfaces sensibles des différents effets. De ces travaux a pu être dégagée une nouvelle méthodologie de test destinée à l'industrie. Son objectif est d'optimiser l'efficacité et le coût des caractérisations, grâce à l'utilisation de l'outil laser de façon complémentaire aux accélérateurs de particules. Enfin, une nouvelle solution de tolérance aux fautes est proposée : basée sur la propriété des cellules DRAMs d'être immune aux radiations lorsqu'elles sont déchargées, cette technique permet la correction de tous les bits d'un mot logique. / DRAMs are frequently used in space and aeronautic systems. Their sensitivity to cosmic radiations have to be known in order to satisfy reliability requirements for critical applications. These evaluations are traditionally done with particle accelerators. However, devices become more complex with technology integration. Therefore new effects appear, inducing longer and more expensive tests. There is a complementary solution: the pulsed laser, which trigger similar effects as particles. Thanks to these two test tools, main DRAM radiation failure modes were studied: SEUs (Single Event Upset) in memory blocks, and SEFIs (Single Event Functional Interrupt) in peripheral circuits. This work demonstrates the influence of test patterns on SEU and SEFI sensitivities depending on technology used. In addition, this study identifies the origin of the most frequent type of SEFIs. Moreover, laser techniques were developed to quantify sensitive surfaces of the different effects. This work led to a new test methodology for industry, in order to optimize test cost and efficiency using both pulsed laser beams and particle accelerators. Finally, a new fault tolerant technique is proposed: based on DRAM cell radiation immunity when discharged, this technique allows to correct all bits of a logic word.