The world of wireless communications is under constant change. Radio standards evolve and new standards emerge. More and more functionality is put into wireless terminals. E.g. mobile phones need to handle both second and third generation mobile telephony as well as Bluetooth, and will soon also support wireless LAN functionality, reception of digital audio and video broadcasting, etc. These developments have lead to an increased interest in software defined radio (SDR), i.e. radio devices that can be reconfigured via software. SDR would provide benefits such as low cost for multi-mode devices, reuse of the same hardware in different products, and increased product life time via software updates. One essential part of any software defined radio is a programmable baseband processor that is flexible enough to handle different types of modulation, different channel coding schemes, and different trade-offs between data rate and mobility. So far, programmable baseband solutions have mostly been used in high end systems such as mobile telephony base stations since the cost and power consumption have been considered too high for handheld terminals. In this work a new low power and low silicon area programmable baseband processor architecture aimed for multi-mode terminals is presented. The architecture is based on a customized DSP core and a number of hardware accelerators connected via a configurable network. The architecture offers a good tradeoff between flexibility and performance through an optimized instruction set, efficient hardware acceleration of carefully selected functions, low memory cost, and low control overhead. One main contribution of this work is a study of important issues in programmable baseband processing such as software-hardware partitioning, instruction level acceleration, low power design, and memory issues. Further contributions are a unique optimized instruction set architecture, a unique architecture for efficient integration of hardware accelerators in the processor, and mapping of complete baseband applications to the presented architecture. The architecture has been proven in a manufactured demonstrator chip for wireless LAN applications. Wireless LAN firmware has been developed and run on the chip at full speed. Silicon area and measured power consumption have proven to be similar to that of a non-programmable ASIC solution.

With the development of powerful computational resources such as Digital Signal Processors and Field Programmable Gate Arrays, It has become possible to utilize many radio functions via software. This is the main concept of an up-and-coming technology of Software Defined Radio. In the Thesis, a number of platforms for implementation of Software Defined Radio has been evaluated. Platform that proved to be most suitable for the project was Ettus’ USRP N210. Using the platform, implementation of 802.15.4 Zigbee’s physical layer was done, where experiments whose outputs can later be used to compare performance with respect to "hardware radios" were performed. / Med utvecklingen av enheter med kraftfulla beräkningsegenskaper som “Digital Signal Processors” och “Field Programmable Gate Arrays” har det blivit möjligt att implementera flera radiofunktioner i mjukvara. Det är huvudkonceptet i den uppåtgående teknologin mjukvaru definierad radio.I det här examensarbetet har ett flertal plattformar för mjukvaru definierad radioutvärderats. Plattformen som visade sig vara mest lämplig för projektet var Ettus USRP N210. En implementation av IEEE 802.15.4 Zigbees fysiska lager har realiserats till plattformen. Experiment, vars utdata senare kan användas för att jämföra prestanda mellan mjukvaru definierad radio och hårdvaru baserad radio, har även utförts. / TESLA - Time-critical and Safe wireLess Automation communication / GAUSS - Guaranteed Automation communication Under Severe disturbanceS

The objective of this thesis is to design and implement a rapid, reconfigurable and portable reader for wirelessly interrogating inductively coupled passive sensors. While the current method of impedance analyzer is sensitive and an accurate, the instruments used are bulky and slow, substantially hampering in-field testing and interrogation of sensors. Current methods cannot provide a quantifiable measure on minimum necessary read-speeds and instrument accuracy desirable for rapid sensing applications. This work summarizes the design and hardware implementation of two reader methods that address the aforementioned requirements. Both reader methods are based on a reflectometer approach: Swept-frequency Reflectometer Reader and Switched-frequency Interrogation Technique (SWIFT). The first method is a much faster alternative to in-lab and in-field testing for structural health monitoring, and is intended as an immediate replacement for the impedance analyzer method. Switched-frequency Interrogation is specifically designed to satisfy the need for rapid and accurate reading, potentially for in-motion sensing applications. This method provides a way of empirically relating minimum necessary read-time required for desired read-ranges. It also facilitates quantification of uncertainty in measurements, which is very critical in determining instrument accuracy in-field. The system design and implementation of both methods are described in detail and experimental results are presented to benchmark the performance of the readers. Issues of instrument reliability and practical limitations are also discussed, with potential solutions. Both methods are intended as universal techniques for wirelessly interrogating coupled passive sensors, not limited to their current form of implementation. / text

It is often required in communication and navigation systems to be able to receive signals from multiple stations simultaneously. A common practice to do this is to use multiple hardware resources; a different set of resources for each station. In this thesis, a Coherent Amplitude Modulated (AM) receiver system was developed based on Software Defined Radio (SDR) technology enabling reception of multiple signals using hardware resources needed only for one station. The receiver system architecture employs Time Division Multiplexing (TDM) to share the single hardware resource among multiple streams of data. The architecture is designed so that it can be minimally modified to support any number of stations. The Verilog Hardware Description Language (HDL) was used to capture the receiver system architecture and design. The design and architecture are initially validated using HDL post-synthesis and post-implementation simulation. In addition, the receiver system architecture and design were implemented to a Xilinx Field Programmable Gate Array (FPGA) technology prototyping board for experimental testing and final validation.

Radio Frequency IDentification (RFID) is a contactless, automatic identification wireless technology primarily used for identifying and tracking of objects, goods and humans. RFID is not only limited to identification and tracking applications. This proliferating wireless technology has been deployed in numerous securities sensitive applications e.g. access control, e-passports, contactless payments, driver license, transport ticking and health cards. RFID inherits all the security and privacy problems that are related to wireless technology and in addition to those that are specific to RFID systems. The security and privacy protection schemes proposed in literature for wireless devices are mostly secured through symmetric/asymmetric keys encryption/decryption and hash functions. The security of all these cryptographic algorithms depends on computationally complex problems that are hard to compute using available resources. However, these algorithms require cryptographic operations on RFID tags which contradict the low cost demand of RFID tags. Due to limited number of logic gates in tags, i.e., 5K-10K, these methods are not practical. Much research effort has done in attempt to solve consumer's privacy and security problem. Solutions that prevent clandestine inventory are mostly application layer techniques. To solve this problem, a new RFID physical layer scheme has been proposed namely Direct Sequence Backscatter Encryption (DSB Enc). The proposed scheme uses level generator to produce different levels before transmitting the signal to the tag. The tag response to the signal sent by the reader using backscatter communications on the same signal which looks random to the eavesdropper. Therefore eavesdropper cannot extract the information from reader to tag and tag to reader communication using passive eavesdropping. As reader knows the different generated levels added to the carrier signal, it can remove the levels and retrieve the tag's messages. We proposed a lightweight, low-cost and practically secure physical layer security to the RFID system, for a supply chain processing application, without increasing the computational power and tag's cost. The proposed scheme was validated by simulations on GNU Radio and experimentation using SDR and a WISP tag. Our implementation and experimental results validate that DSB Enc is secure against passive eavesdropping, replay and relay attacks. It provides better results in the presence of AWGN channel.

Η παρούσα διπλωματική εργασία αφορά στην πειραματική αξιολόγηση του μηχανισμού ανάκτησης ρυθμού συμβόλου για ψηφιακούς δέκτες τεχνολογίας SDR που λαμβάνουν δεδομένα μέσω δορυφόρου. Η ορολογία SDR/SR (Software Defined Radio/Software Radio) χρησιμοποιείται για να χαρακτηρίσει τους πομποδέκτες που μπορούν να καθορίζουν σημαντικές παραμέτρους τους και βασικές αρχές της λειτουργίας τους μέσω αναβάθμισης ή ενημέρωσης του λογισμικού τους. Ο μηχανισμός ανάκτησης του ρυθμού συμβόλου (Symbol Timing Recovery, STR) αναπτύχθηκε στα πλαίσια της διδακτορικής διατριβής του διδάκτορος Παναγιώτη Σαββόπουλου. Η παρούσα εργασία μελετά τη σύγκλιση του βρόχου υπό συνθήκες παραμένοντος σφάλματος συχνότητας καθώς επίσης και τον προσδιορισμό του λόγου σήματος προς θόρυβο στην έξοδο του βρόχου κάνοντας χρήση ενός νέου μεγέθους, metric, το οποίο έχει εισαχθεί στα πλαίσια της προαναφερθείσας διδακτορικής διατριβής, υπό συνθήκες λευκού Gaussian θορύβου. Το μέγεθος αυτό είναι σε θέση να δώσει αξιόπιστα αποτελέσματα στις ενδιάμεσες υπομονάδες του δέκτη υπό συνθήκες παραμένοντος σφάλματος συχνότητας. Στην παρούσα εργασία μελετώνται οι QPSK, 8PSK, 16-APSK και 32-APSK διαμορφώσεις διότι αυτές οι διαμορφώσεις χρησιμοποιούνται από το πρότυπο DVB-S2. / The purpose of this project is the experimental evaluation of a mechanism for the symbol timing recovery which is used in digital Software Defined Radio receivers. SDR/SR (Software Defined Radio/Software Radio) technology is used to characterise the transmitters and the receivers which are able to determine important parameters and basic primciples for their function through upgrade or briefing of their software. The symbol timing recovery mechanism (STR) was developped in terms of the doctora of dr Panagiotis Savopoylos. The precent project examines the loop’s convergence when there is frequency error as well as the signal to noise ratio in the output of STR with the use of a new size, metric, which was also developped in terms of the doctora which was mentioned before, when there is white Gaussian noise. The metric is able to give reliable results in the intermediate stages of the receiver when there is frequency error. In the precent project are examined the QPSK, 8PSK,16-APSK, 32-APSK modulations because these modulations are used in DVB-S2 standard.

A measurement equipment with the purpose of measuring the radiation pattern of antennas in the frequency interval 30-300 MHz was constructed. To perform the necessary measurements the equipment needs to be mounted on a UAV, a necessity that demands a low weight from the measurement equipment. These kinds of measurements are today done with equipment that is mounted on helicopters, making the equipment smaller and fitting it on an UAV will save cost for the persons or companies that need to utilize this service. To ensure that the system is easy to use for anyone who wants to characterize an antenna efforts were made to make the software application user friendly. The system visualizes measurement results in 2D diagrams that are simple to analyze. Since the equipment has size restrictions the computer in the system needs to be small and light. The single board computer used has computational limitations and therefore the digital signal processing must be carefully designed to both be fast and generate good measurement data. To verify the performance of the system tests and theoretical simulations where performed and compared. The tests were performed both in an echo free antenna chamber and in realistic outdoor environments with an UAV. The finished system performed well and the measurement results showed clear similarities with the theoretical simulations. The outdoor environment clearly influences the shape of an antennas radiation pattern and the need to characterize antennas in a realistic environment became clear.

In todays fast evolving mobile communications the requirements of higher datarates are continuously increasing, pushing operators to upgrade the backhaul to support these speeds. A cost eective way of doing this is by using microwave links between base stations, but as the requirements of data rates increase, the capacity of the microwave links must be increased. This thesis was part of a funded research project with the objective of developing the next generation high speed microwave links for the E-band. In the research project there was a need for a testing system that was able to generate a series of test signals with selectable QAM modulations and adjustable properties to be able to measure and evaluate hardware within the research project. The developed system was designed in a digital domain using an FPGA platform from Altera, and had the ability of selecting several types of modulations and changing the properties of the output signals as requested. By using simulation in several steps and measurements of the complete system the functionality was verified and the system was delivered to the research project successfully. The developed system can be used to test several dierent modulators in other projects as well and is easily extended to provide further properties.

Satellite communication system designers are continuously struggling to improve the channel capacity. A critical challenge results from the limited power available aboard the satellite.Because of this constraint, the onboard power amplifier must work with a small power supply which limits its maximum output power. To ensure a sufficient Signal-to-Noise power Ratio (SNR) on the receiver side, the power amplifier must work close to its saturation point. This is power efficient but unfortunately adds non-linear distortions to the communication channel. The latters are very penalizing for high order modulations.In the literature, several equalization algorithms have been proposed to cope with the resulting non-linear communication channel. The most popular solution consists in using baseband Volterra series in order to build non-linear equalization filters. On the other hand, the Recurrent Neural Networks (RNNs), which come from the artificial neural network field, are also interesting candidates to generate such non-linear filters. But they are difficult to implement in practice due to the high complexity of their training. To simplify this task, the Echo State Network (ESN) paradigm has been proposed. It has the advantage of offering performances similar to classical RNNs but with a reduced complexity.The purpose of this work is, first, to compare this solution to the state-of-the-art baseband Volterra filters. We show that the classical ESN is able to reach the same performances, evaluated in terms of Bit Error Rate (BER), and has similar complexity. Secondly, we propose a new design for the ESN which achieves a strong reduction in complexity while conserving a similar BER.To compensate for the channel, the literature proposes to adapt the coefficients of these equalizers with the help of a training sequence in order to recover the transmitted constellation points. We show that, in such a case, the usual symbol detection criterion, based on Euclidean distances, is no longer optimal. For this reason, we first propose a new detection criterion which meets the Maximum Likelihood (ML) criterion. Secondly, we propose a modification of the equalizers training reference points in order to improve their performances and make the detection based on Euclidean distances optimal again. This last solution can offer a significant reduction of the BER without increasing the equalization and detection complexity. Only the new training reference points must be evaluated.In this work, we also explore the field of analog equalizers as different papers showed that the ESN is an interesting candidate for this purpose. It is a promising approach to reduce the equalizer complexity as the digital implementation is very challenging and power-hungry, in particular for high bandwidth communications. We numerically demonstrate that a dedicated analog optoelectronic implementation of the ESN can reach the state-of-the-art performance of digital equalizers. In addition, we show that it can reduce the required resolution of the Analog-to-Digital Converters (ADCs).Finally, a hardware demonstration of the digital solutions is proposed. For this purpose, we build a physical layer test bench which depicts a non-linear communication between two radios. We show that if we drive the transmitter power amplifier close to its saturation point, we can improve the communication range if the non-linear distortions are compensated for at the receiver. The transmitter and the receiver are implemented with Software Defined Radios (SDRs). / Doctorat en Sciences de l'ingénieur et technologie / info:eu-repo/semantics/nonPublished

L'internet des objets vise à connecter des milliards d'objets physiques ainsi qu'à les rendre accessibles depuis le monde numérique que représente l'internet d'aujourd'hui. Pour ce faire, l'accès à ces objets sera majoritairement réalisé sans fil et sans utiliser d'infrastructures prédéfinies ou de normes spécifiques. Une telle technologie nécessite de définir et d'implémenter des nœuds radio intelligents capables de s'adapter à différents protocoles physiques de communication. Nos travaux de recherches ont consisté à définir un flot de conception pour ces nœuds intelligents partant de leur modélisation à haut niveau jusqu'à leur implémentation sur des cibles de types FPGA. Ce flot vise à améliorer la programmabilité des formes d'ondes par l'utilisation de spécification de haut niveau exécutables et synthétisables, il repose sur la synthèse de haut niveau (HLS pour High Level Synthesis) pour le prototypage rapide des briques de base ainsi que sur le modèle de calcul de types flot de données des formes d'ondes radio. Le point d'entrée du flot consiste en un langage à usage spécifique (DSL pour Domain Specific Language) qui permet de modéliser à haut niveau une forme d'onde tout en insérant des contraintes d'implémentation pour des architectures reconfigurables telles que les FPGA. Il est associé à un compilateur qui permet de générer du code synthétisable ainsi que des scripts de synthèse. La forme d'onde finale est composée d'un chemin de données et d'une entité de contrôle implémentée sous forme d'une machine d'état hiérarchique. / The Internet of Things (IoT) aims at connecting billions of communicating devices through an internet-like network. To this aim, the access to these things is expected to be performed via wireless technologies without using any predefined infrastructures or standards. This technology requires defining and implementing smart nodes capable to adapt to different radio communication protocols. In this thesis, we have defined a design methodology/flow, for such smart nodes, starting from their high-level specification down to their implementation in FPGA fabrics. This flow aims at improving the programmability of the waveforms by leveraging some high-level specifications. Thus, it relies on the High-Level Synthesis (HLS) for rapid prototyping of the waveforms functional blocks as well as the dataflow model of computation. Its entry point is Domain-Specific Language which enables modeling a waveform while inserting some implementation constraints for reconfigurable architectures such as the FPGAs. The flow is featured with a compiler which purpose is to produce some synthesis scripts and generate some RTL source code. The final waveform consists of a datapath and a control unit implemented as a Hierarchical Finite State Machine (HFSM).