The SRAM memory generator in this thesis is divided into four parts: row decoder, storage cell, column decoder, and sense amplifier & write controller. The row decoder is designed using pass-transistors logic with better area and regularity compared with conventional NAND based decoders. Two different column decoders, tree structure and NOR based predecoder, are provided in current version. Although only SRAM is implemented in this thesis, the memory generator platform is complete with all the necessary models required in the embedded design. In the future, other memories, such as cache, shift register, FIFO, stacks, ROM, register files, and content addressable memory, can be integrated in this memory generator platform.

Memory wall is becoming a more and more serious bottleneck of the processing speed of microprocessors. The mismatch between CPUs and memories has been increasing since three decades ago. SRAM was introduced as the bridge between the main memory and the CPU. SRAM is designed to be on the same die with CPU and stores temporary data and instructions that are to be processed by the CPU. Thus, the performance of SRAMs has a direct impact on the performance of CPUs. With the application of mass amount data to be processed nowadays, there is a great need for high-performance CPUs. Three dimensional CPUs and CPUs that are specifically designed for machine learning are gaining popularity. The objective of this work is to design high-performance SRAM for these two emerging applications. Firstly, a novel delay cell based on dummy TSV is proposed to replace traditional delay cells for better timing control. Secondly, a unique SRAM with novel architecture is custom designed for a high-performance machine learning processor. Post-layout simulation shows that the SRAM works well with the processing core and its design is optimized to work well with machine learning processors based on convolutional neural networks. A prototype of the SRAM is also tapped out to further verify our design.

京都大学 / 新制・課程博士 / 博士(情報学) / 甲第24746号 / 情博第834号 / 新制||情||140(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 佐藤 高史, 教授 橋本 昌宜, 教授 新津 葵一 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

Physically unclonable functions are increasingly used as security primitives for device identification and anti-counterfeiting. However, PUFs are associated with noise and bias which in turn affects its property of reliability and predictability. The noise is corrected using fuzzy extractors, but the helper data generated during the process may cause leakage in min-entropy due to the bias observed in the response. This thesis offers two optimization techniques for PUF based protocols. The first part talks about the construction of a secure enrollment solution for PUFs on a low-end resource-constrained device using a microcontroller and a secure networked architecture. The second part deals with the combined optimization of min-entropy and error-rate using symbol clustering techniques to improve the reliability of SRAM PUFs. The results indicate an increase in min-entropy without much effect on the error rate but at the expense of PUF size. / Master of Science

The overall energy consumption of portable devices has been projected to triple over the next decade, growing to match the total power generated by the European Union and Canada by 2025. The rise of the internet-of-things (IoT) and ubiquitous and embedded computing has resulted in an exponential increase in such devices, wherein projections estimate that 50 billion smart devices will be connected and online by 2020. In order to alleviate the associated stresses placed on power generation and distribution networks, a holistic approach must be taken to conserve energy usage in electronic devices from the component to the circuit level. An effective approach to reduce power dissipation has been a continual reduction in operating voltage, thereby quadratically down-scaling active power dissipation. However, as state-of-the-art silicon (Si) complimentary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) enter sub-threshold operation in the ultra-low supply voltage regime, their drive current is noticeable degraded. Therefore, new energy-efficient MOSFETs and circuit architectures must be introduced. In this work, tunnel FETs (TFETs), which operate leveraging quantum mechanical tunneling, are investigated. A comprehensive investigation detailing electronic materials, to novel TFET device designs, to memory and logic digital circuits based upon those TFETs is provided in this work. Combined, these advances offer a computing platform that could save considerable energy and reduce power consumption in next-generation, ultra-low voltage applications. / Ph. D. / The overall energy consumption of portable devices has been projected to triple over the next decade, growing to match the total power generated by the European Union and Canada by 2025. The rise of the internet-of-things (IoT) and ubiquitous and embedded computing has resulted in an exponential increase in such devices, wherein projections estimate that 50 billion “smart” devices will be connected and “online” by 2020. In order to alleviate the associated stresses placed on power generation and distribution networks, a holistic approach must be taken to conserve energy usage in electronic devices from the component to the circuit level. An effective approach to reduce power dissipation has been a continual reduction in operating voltage, thereby quadratically down-scaling active power dissipation. However, as state-of-the-art silicon (Si) complimentary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) enter sub-threshold operation in the ultra-low supply voltage regime, their drive current is noticeable degraded. Therefore, new energy-efficient MOSFETs and circuit architectures must be introduced. In this work, tunnel FETs (TFETs), which operate leveraging quantum mechanical tunneling, are investigated. A comprehensive investigation detailing electronic materials, to novel TFET device designs, to memory and logic digital circuits based upon those TFETs is provided in this work. Combined, these advances offer a computing platform that could save considerable energy and reduce power consumption in next-generation, ultra-low voltage applications.

With a view to reduce the number of components in a Static Random Access Memory (SRAM) cell, the feasibility of use of Lambda Bipolar Transistor (LBT)in the bistable element of the cell has been explored under the present study. The LBT under consideration here comprises of an enhancement mode MOSFET integrated with a parasitic bipolar transistor so as to perform as a negative resistance device. LBTs for the study have been fabricated and analysed. The devices have been shown to function at much lower voltage and current levels than those reported earlier/ and thus have been shown to be suitable for lower power applications. The issues of agreements and discrepancies of the experimental results with the original DC model of the device have been highlighted and discussed. The factors contributing to the drain current of the MOSFET in the LBT have been identified. It has also been shown that in the real case of an LBT in operation, the MOSFET in it does not function as a discrete device for the same conditions of voltages and current levels as in an LBT. As per the present study, it is assessed to be influenced by the presence of the BJT in operation and this effect is felt more at the lower current levels of operation. With a separate and tailored p-well implantation the possibility of fabrication of LBTs with a CMOS technology is established. Along with a couple of polysilicon resistors, the LBTs have been successfully made to perform in the common-collector configuration as the bistable storage element of SRAM cell (as proposed in the literature). The bistable element with the LBT in common-emitter mode also has been visualised and practically achieved with the fabricated devices. The WRITE transients for either case have been simulated for various levels of WRITE voltages and their time of hold.The speed of Writing achieved are found comparable with that of the standard SRAMs. The advantages and disadvantages of using the LBT in either mode have been highlighted and discussed. The power consumption of the bistable element with the LBT in either mode is however shown to be the same. A different approach of READING has been proposed to overcome the factors known to increase the cycle time. On the whole, under the present study, the proposal of using LBTs in the bistable storage element of the SRAM cell has been shown to be feasible. Such SRAM circuits can find possible applications in the fields where smaller circuit area is the major concern.

The PhD thesis focuses on the always-on low power SRAM memories (essentially low dynamic power) in thin CMOS technology node CMOS 32nm and beyond. It reviews the state of the art of the eSRAM and describes different techniques to reduce the static and dynamic power consumption with respect the variability issue. Main techniques of power reduction are reviewed with their contributions and their limitations. It presents also a discussion about a statistical variability modeling and the variability effects on the yield. An original low power architecture based on 5T-Portless bit-cell is presented, with current mode read/write operations, as an ideal candidate for the always-on SRAM memories. A test chip implementation in CMOS 32nm of the 5T-Porless is designed and a comparison with an existing 6T SRAM memory is presented based on simulation. Some test chip functionality results and power consumption are performed. Finally the conclusion highlights the major contributions of the study and discusses the various simplification assumptions to see possible limitations. It is concluded affirmatively about industrial interest of the 5T-Portless SRAM for always-on embedded applications. Perspectives concern the analytical modeling for statistical behavior of SRAM as the Monte-Carlo approach is no more practicable. The migration of the 5T-Portless SRAM may be already considered in advanced nodes.

Monolithic Active Pixel Sensors (MAPS) are good candidates to be used in High Energy Physics (HEP) experiments for charged particle detection. In the HEP applications, MAPS chips are placed very close to the interaction point and are directly exposed to harsh environmental radiation. This thesis focuses on the study and improvement of the MAPS radiation hardness. The main radiation effects and the research progress of MAPS are studied firstly. During the study, the SRAM IP cores built in MAPS are found limiting the radiation hardness of the whole MAPS chips. Consequently, in order to improve the radiation hardness of MAPS, three radiation hard memories are designed and evaluated for the HEP experiments. In order to replace the SRAM IP cores, a radiation hard SRAM is developed on a very limited area. For smaller feature size processes, in which the single event upset (SEU) effects get significant, a radiation hard SRAM with enhanced SEU tolerance is implemented by an error detection and correction algorithm and a bit-interleaving storage. In order to obtain higher radiation tolerance and higher circuitry density, a dual-port memory with an original 2-transistor cell is developed and evaluated for future MAPS chips. Finally, the radiation hardness of the MAPS chips using new available processes is studied, and the future works are prospected.

Les capteurs monolithiques actifs à pixels (Monolithic Active Pixel Sensors, MAPS) sont de bons candidats pour être utilisés dans des expériences en Physique des Hautes Énergies (PHE) pour la détection des particules chargées. Dans les applications en PHE, des puces MAPS sont placées dans le voisinage immédiat du point d’interaction et sont directement exposées au rayonnement intense de leur environnement. Dans cette thèse, nous avons étudié et amélioré la résistance aux radiations des MAPS. Les effets principaux de l’irradiation et le progrès de la recherche sur les MAPS sont étudiés tout d'abord. Nous avons constaté que les cœurs des SRAM IP incorporées dans la puce MAPS limitent sensiblement la tolérance aux radiations de la puce MAPS entière. Aussi, pour améliorer la radiorésistance des MAPS, trois mémoires radiorésistantes sont conçues et évaluées pour les expériences en PHE. Pour remplacer les cœurs des IP SRAM, une SRAM radiorésistante est développée sur une petite surface. Pour les procédés de plus petit taille de grille des transistors, dans lequel les effets SEU (Single Event Upset) deviennent significatifs, une SRAM radiorésistante avec une tolérance SEU accrue est réalisée à l’aide d’un algorithme de détection et de correction d'erreurs (Error Detection And Correction, EDAC) et un stockage entrelacé des bits. Afin d'obtenir une tolérance aux rayonnements et une densité de micro-circuits plus élevées, une mémoire à double accès avec une cellule à 2 transistors originale est développée et évaluée pour des puces MAPS futures. Enfin, la radiorésistance des puces MAPS avec des nouveaux procédés disponibles est étudiée, et les travaux futurs sont proposés. / Monolithic Active Pixel Sensors (MAPS) are good candidates to be used in High Energy Physics (HEP) experiments for charged particle detection. In the HEP applications, MAPS chips are placed very close to the interaction point and are directly exposed to harsh environmental radiation. This thesis focuses on the study and improvement of the MAPS radiation hardness. The main radiation effects and the research progress of MAPS are studied firstly. During the study, the SRAM IP cores built in MAPS are found limiting the radiation hardness of the whole MAPS chips. Consequently, in order to improve the radiation hardness of MAPS, three radiation hard memories are designed and evaluated for the HEP experiments. In order to replace the SRAM IP cores, a radiation hard SRAM is developed on a very limited area. For smaller feature size processes, in which the single event upset (SEU) effects get significant, a radiation hard SRAM with enhanced SEU tolerance is implemented by an error detection and correction algorithm and a bit-interleaving storage. In order to obtain higher radiation tolerance and higher circuitry density, a dual-port memory with an original 2-transistor cell is developed and evaluated for future MAPS chips. Finally, the radiation hardness of the MAPS chips using new available processes is studied, and the future works are prospected.

Pour adresser les nœuds technologiques avancés dans le cadre de la lithographie électronique, une nouvelle stratégie de correction des effets de proximité a été imaginée pour prendre le relai de la technique standard de modulation de dose. Dans ces travaux de thèse, les effets de proximité ont été analysés sur les outils e-beam de dernière génération au sein du LETI. Les limites de la modulation de dose ont aussi été évaluées. Parallèlement, une approche plus fondamentale, basée sur la simulation, a permis de mieux comprendre l'impact des différentes étapes du procédé de lithographie sur les motifs réalisés. Une nouvelle stratégie de correction avancée, appelée exposition multiple, a ensuite été mise au point. Celle-ci fait intervenir des motifs spécifiques appelés eRIF (electron Resolution lmprovement Features) dont l'exposition, couplée à celle des motifs initiaux permet de mieux contrôler la répartition de la dose injectée dans la résine. On parle alors d'expositions multiples. Au cours de ces travaux le positionnement des eRIF, ainsi que leurs dimensions ont fait l'objet d'une étude approfondie. L'élaboration d'algorithmes d'optimisation et la réalisation d'expérimentations en salle blanche ont permis d'optimiser ces paramètres et de mettre en évidence les gains apportés par les eRIF. Par rapport à la modulation de dose, des améliorations significatives ont pu être démontrées sur de véritables circuits intégrés. Grâce à l'exposition multiple, la résolution ultime des outils de lithographie e-beam a été repoussée de 2 nœuds technologiques pour les niveaux les plus critiques d'un circuit. Les règles de dessin retenues pour réaliser les eRIF ont ensuite été intégrées dans des modèles de corrections. via le logiciel de préparation de données INSCALE d'ASELTA NANOGRAPHICS pour assurer une correction automatisée des circuits. / In electron beam lithography, a new proximity affects correction strategy has been imagined to push the resolution capabilities beyond the limitations of the standard dose modulation. In this work, the proximity affects inherent to e-beam lithography have been studied on the newest e-beam tools available at LETI. First, the limits of the standard dose modulation correction have been evaluated. The influences of each step of the lithographic process have also been analyzed from a theoretical point a view. A simulation approach was built and used to determine the impact of each of these steps on the patterned features. Then, a new writing strategy has been fully developed. It involves sub resolution features known as eRIF (electron Resolution Improvement features) which provide a finer control of the dose profile into the resist. Since the eRIF are exposed a top the nominal features, this new writing strategy is called multiple pass exposure. In this work, the position, the dose and the design of the eRIF have been studied and optimized to get the best of this new strategy. To do so, experiments were led in a clean room environment, and minimization algorithms have been developed. It has been demonstrated that the eRIF provide a significant gain compared to the standard dose modulation. Improvements have been observed even on the most critical levels of the Integrated circuits. By using the multiple pass exposure with optimized eRIF, the resolution capabilities of the e-beam tool have been reduced by 2 technological nodes. The design rules that have been determined to use the eRIF the most efficient way were finally implemented in INSCALE, the new data preparation software developed by ASELTA NANOGRAPHICS. This way, multiple pass exposure can be used in an automated mode to correct full layouts.