About 50 million people worldwide suffer from epilepsy and one third of them have seizures that are refractory to medication. In the past few decades, deep brain stimulation (DBS) has been explored by researchers and physicians as a promising way to control and treat epileptic seizures. To make the DBS therapy more efficient and effective, the feedback loop for titrating therapy is required. It means the implantable DBS devices should be smart enough to sense the brain signals and then adjust the stimulation parameters adaptively. This research proposes a signal-sensing channel configurable to various neural applications, which is a vital part for a future closed-loop epileptic seizure stimulation system. This doctoral study has two main contributions, 1) a micropower low-noise neural front-end circuit, and 2) a low-power configurable neural recording system for both neural action-potential (AP) and fast-ripple (FR) signals. The neural front end consists of a preamplifier followed by a bandpass filter (BPF). This design focuses on improving the noise-power efficiency of the preamplifier and the power/pole merit of the BPF at ultra-low power consumption. In measurement, the preamplifier exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of bandwidth (BW), 5.86-μVrms input-referred noise in AP mode, while showing 39.4-dB DC gain, 0.36 Hz to 1.3 kHz of BW, 3.07-μVrms noise in FR mode. The preamplifier achieves noise efficiency factor (NEF) of 2.93 and 3.09 for AP and FR modes, respectively. The preamplifier power consumption is 2.4 μW from 2.8 V for both modes. The 6th-order follow-the-leader feedback elliptic BPF passes FR signals and provides -110 dB/decade attenuation to out-of-band interferers. It consumes 2.1 μW from 2.8 V (or 0.35 μW/pole) and is one of the most power-efficient high-order active filters reported to date. The complete front-end circuit achieves a mid-band gain of 38.5 dB, a BW from 250 to 486 Hz, and a total input-referred noise of 2.48 μVrms while consuming 4.5 μW from the 2.8 V power supply. The front-end NEF achieved is 7.6. The power efficiency of the complete front-end is 0.75 μW/pole. The chip is implemented in a standard 0.6-μm CMOS process with a die area of 0.45 mm^2. The neural recording system incorporates the front-end circuit and a sigma-delta analog-to-digital converter (ADC). The ADC has scalable BW and power consumption for digitizing both AP and FR signals captured by the front end. Various design techniques are applied to the improvement of power and area efficiency for the ADC. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588-μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6-μm CMOS process. The die size is 11.25 mm^2. The proposed circuits can be extended to a multi-channel system, with the ADC shared by all channels, as the sensing part of a future closed-loop DBS system for the treatment of intractable epilepsy.

For low and medium power applications, conventional two-level inverters are widely used in industrial applications including electric vehicle drives, traction drives, distributed generation, power management and grid connected renewable energy systems. To filter out the harmonic currents from the load, passive line filters are used. These filters are designed to pass the fundamental phase current and suppress higher harmonic currents, making the filters bulky. To get a nearly sinusoidal current waveform, these two level inverters are switched at high frequency to shift the harmonic components in the phase current to high frequencies to reduce size and cost of the filter. But higher switching frequencies have some drawbacks like large dV /dt stresses on the motor terminals and switching devices, leading to electro-magnetic interference (EMI) problems and higher switching losses. For full DC bus utilization to enhance the power output from the two level inverter, the inverter has to operate in overmodulation region up to the six-step operation. Considerable fifth and seventh order (6n ± 1, n = odd) harmonics are produced when the inverter operates in overmodulation region. These include some low order harmonics like fifth and seventh, which are currently suppressed by using bulky passive line filters. Different high frequency modulation schemes are uniquely used in overmodulation region to suppress these harmonics. Another well accepted method of harmonic suppression is the selective harmonic elimination (SHE) techniques. SHE introduces notches at specific angles in a fundamental period of the inverter pole voltage to eliminate a particular harmonic component from the pole voltage. But, SHE involves extensive offline computation and requirement for higher memory for implementation of huge lookup tables. dodecagonal voltage space vectors have been reported in literature. Dodecagonal voltage space vector structures inherently eliminate fifth and seventh order (6n ± 1, n = odd) harmonics from the phase voltage. However, these require multiple isolated and unequal DC supplies (like VDC and 0.366VDC ). Generating DC voltage supplies at particular ratio to the main DC supply, requires additional circuitry. This increases the size of the converter and four quadrant back to back operation is not possible for the converter. To overcome the problems mentioned above, a novel switched capacitive filtering technique is proposed in this work for low and medium power drives applications. The filtering is done by an inverter fed by capacitor. A novel method to ensure zero power contribution by an inverter is shown, enabling the inverter to be fed by a capacitor. Thus, the capacitor fed inverter is shown to operate as a switched capacitive filter, which generates harmonic voltages that gets eliminated from the phase voltage of conventional two level inverters. With the proposed switched capacitive filtering technique, the following benefits are achieved. • Fifth and seventh order (6n ± 1, n = odd) harmonics are eliminated from the phase voltage, for the full modulation range of the two level inverters even while operating in overmodulation region and six-step mode. Thus, bulky passive line filters are avoided. • Since, the capacitive filter does not contribute any active power to the load, single DC supply operation is possible. Hence, four quadrant back to back operations is possible with the proposed filtering technique. • Dodecagonal voltage space vector structures are realized using single DC supply for the first time. • Modulation techniques for different power circuit topologies have been proposed which inherently controls the capacitor voltage at specific voltage levels for the full modulation range of the inverter including six-step operation. Hence, no additional pre-charging circuitry is required. • High frequency switching is shifted to the capacitive filter which is at a low voltage compared to the DC supply fed power contributing inverter. Thus, the main inverter need not be switched at high switching frequency for harmonic suppression. This reduces the switching loss as compared to conventional inverters, to achieve harmonic suppression of comparable order. • Reduced voltage stress on the switches of the switched capacitive filter. Hence, low voltage devices can be used to implement the switched capacitive filter, reducing the cost and size drastically as compared to conventional passive line filters. The proposed switched capacitive filtering scheme has been realized for open-end winding induction motor drive and three phase star connected three terminal induction motor drive where conventional two level inverter is used as the power contributing inverter. Additionally, extension of the capacitive filtering scheme to multilevel inverter fed drives is also shown, where the main power contributing inverter is a three level flying capacitor (FC) inverter. The power circuit implementations are briefly described as following. (i) In open-end winding three phase induction motors, the two terminals of each of the three phase windings are accessed. The main DC bus connected two level inverter feeds power from one end of the motor terminals. A capacitor fed two level inverter eliminates the fifth and seventh order harmonics from the other end for the full modulation range including overmodulation and six-step operation of DC bus fed inverter. The voltage space vectors from both the inverters connected at opposite ends of the motor forms dodecagonal voltage space vectors. An uniform pulse width modulation (PWM), for the full modulation range is proposed which switches from the dodecagonal voltage space vectors while inherently maintaining the capacitor voltage at 0.289VDC . (ii) In conventional star connection of three phase induction motors, all three terminals of the three phase windings are shorted from one end, leaving access to just three terminals. Such three terminal induction motor fed to conventional two level inverter is commonly used in many drives applications. Capacitor fed H-bridges are cascaded to such two-level inverters, to eliminate the fifth and seventh order harmonics from the phase voltage for the full modulation range including overmodulation and six-step operation of DC fed inverter. The voltage space vectors from capacitor fed H-bridges get added to the voltage space vectors from the two level inverter to form dodecagonal voltage space vectors. A PWM technique for the full modulation range is proposed to switch from the dodecagonal voltage space vector while inherently maintaining the three H-bridge connected capacitor voltages at 0.1445VDC . (iii) Advantages of dodecagonal space vector switching and multilevel inverters are achieved with a single DC supply. A DC supply fed three level flying capacitor (FC) inverter feeds active power to one end of the induction motor winding terminals and H-bridge connected capacitors eliminate fifth and seventh order harmonics from the other end of the motor winding terminals. The voltage space vectors from the three level FC inverter and the H-bridge inverter forms a three level dodecagonal voltage space vectors with symmetric triangular sectors. A PWM technique is developed to switch the three level dodecagonal space vectors and simultaneously control the H-bridge connected capacitors at 0.1445VDC . The fifth and seventh order harmonics are eliminated for the full modulation range of the three level FC inverter, including the extreme six-step operation. Additionally, the proposed inverter has also been shown to operate for rotor field oriented vector control of the open-end winding induction motor drive. For all the power circuit implementation of the switched capacitive filter, an increase of 7.8% in the linear modulation range (up to 48.8Hz) is achieved, implying better DC bus utilization as compared to conventional inverter topologies switching from hexagonal voltage space vectors. With advantages like fifth and seventh order (6n ± 1, n = odd) harmonic elimination throughout the modulation range, reduced dv/dt stress, lower switching frequency in high voltage devices, single DC supply requirement, dodecagonal voltage space vector switching, PWM technique with inherent capacitor balancing, increased linear modulation range and reduced voltage stress on high frequency switches, the proposed switched capacitive filtering scheme is well suited for low and medium power drives application with requirements for high dynamic performance and precise speed control.

The thesis deals about method of gain signals from strain gauge bridges. There are mentioned some signal conditioning methods for bridges amplifiers and charactered their properties. In the next part of this thesis are calculated the amplifier errors for various temperature. There are projected individual variants of strain gage amplifiers (instrumentation amplifier AD524, isolation amplifier, switched capacitor based instrumentation amplifier), their properties are compared with strain gage amplifier Vishay P-3500.

The presented dissertation thesis deals with a novel structure of delta-sigma () modulator which compensates influence of higher harmonic distortion and therefore it is possible to achieve high resolution up to 16 bits. This novel proposed structure combines advantages of one bit quantizer modulators with mutli-bit modulators. The novel second order structure is presented, correct function is verified in MATLAB simulation enviroment and requirements for partial block are studied. The second part of the work deals with design of converter with novel structure of modulator using switched capacitor technique utilizing ONSemi I3T25 technology. Advantages and disadvantages of the novel structure are evaluated and novel structure is compared with common structures of modulators.

La technique de haute intensité ultrasons focalisés (HIFU) est maintenant largement utilisée pour le traitement du cancer, grâce à son avantage non-invasif. Dans un système de HIFU, une matrice de transducteurs à ultrasons est pilotée en phase pour produire un faisceau focalisé d'ultrasons (1M ~ 10 MHz) dans une petite zone de l'emplacement de la cible sur le cancer dans le corps. La plupart des systèmes HIFU sont guidées par imagerie par résonance magnétique (IRM) dans de nos jours. Dans cette étude de doctorat, un amplificateur de puissance de classe D en demi-pont et un système d'accord automatique d'impédance sont proposés. Tous deux circuits proposés sont compatibles avec le système IRM. L'amplificateur de puissance proposé a été réalisé par un circuit imprimé (PCB) avec des composants discrets. Selon les résultats du test, il a rendement de conversion en puissance de 82% pour une puissance de sortie conçue de 1,25W à une fréquence de travail de 3MHz. Le système d'accord automatique d'impédance proposé a été conçu en deux versions: une version en PCB et une version en circuit intégré (IC). Contrairement aux systèmes d'accord automatique proposés dans la littérature, il n'y a pas besoin de l'unité de microcontrôleur (MCU) ou de l'ordinateur dans la conception proposée. D'ailleurs, sans l'aide de composants magnétiques volumineux, ce système d'auto-réglage est entièrement compatible avec l'équipement IRM. La version en PCB a été conçue pour vérifier le principe du système proposé, et il est également utilisé pour guider à la conception du circuit intégré. La réalisation en PCB occupe une surface de 110cm². Les résultats des tests ont confirmé la performance attendue. Le système d'auto-tuning proposé peut parfaitement annuler l'impédance imaginaire du transducteur, et il peut également compenser l'impédance de la dérive causée par les variations inévitables (variation de température, dispersion technique, etc.). La conception du système d'auto-réglage en circuit intégré a été réalisé avec une technologie CMOS (C35B4C3) fournies par Austrian Micro Systems (AMS). La surface occupée par le circuit intégré est seulement de 0,42mm². Le circuit intégré conçu est capable de fonctionner à une large gamme de fréquence tout en conservant une consommation d'énergie très faible (137 mW). D'après les résultats de la simulation, le rendement de puissance de ce circuit peut être amélioré jusqu'à 20% comparant à celui utilisant le réseau d'accord statique. / High intensity focused ultrasound (HIFU) technology is now broadly used for cancer treatment, thanks to its non-invasive property. In a HIFU system, a phased array of ultrasonic transducers is utilized to generate a focused beam of ultrasound (1M~10MHz) into a small area of the cancer target within the body. Most HIFU systems are guided by magnetic resonance imaging (MRI) in nowadays. In this PhD study, a half-bridge class D power amplifier and an automatic impedance tuning system are proposed. Both the class D power amplifier and the auto-tuning system are compatible with MRI system. The proposed power amplifier is implemented by a printed circuit board (PCB) circuit with discrete components. According to the test results, it has a power efficiency of 82% designed for an output power of 3W at 1.25 MHz working frequency. The proposed automatic impedance tuning system has been designed in two versions: a PCB version and an integrated circuit (IC) version. Unlike the typical auto-impedance tuning networks, there is no need of microprogrammed control unit (MCU) or computer in the proposed design. Besides, without using bulky magnetic components, this auto-tuning system is completely compatible with MRI equipment. The PCB version was designed to verify the principle of the proposed automatic impedance tuning system, and it is also used to help the design of the integrated circuit. The PCB realization occupies a surface of 110cm². The test results confirmed the expected performance. The proposed auto-tuning system can perfectly cancel the imaginary impedance of the transducer, and it can also compensate the impedance drifting caused by unavoidable variations (temperature variation, technical dispersion, etc.). The IC design of the auto-tuning system is realized in a CMOS process (C35B4C3) provided by Austrian Micro Systems (AMS). The die area of the integrated circuit is only 0.42mm². This circuit design can provide a wide working frequency range while keeping a very low power consumption (137 mW). According to the simulation results, the power efficiency can be improved can up to 20% by using this auto-tuning circuit compared with that using the static tuning network.

This thesis presents novel radio frequency microelectromechanical (RF MEMS) circuits based on the three-dimensional (3-D) micromachined coplanar transmission lines whose geometry is re-configured by integrated microelectromechanical actuators. Two types of novel RF MEMS devices are proposed. The first is a concept of MEMS capacitors tuneable in multiple discrete and well-defined steps, implemented by in-plane moving of the ground side-walls of a 3-D micromachined coplanar waveguide transmission line. The MEMS actuators are completely embedded in the ground layer of the transmission line, and fabricated using a single-mask silicon-on-insulator (SOI) RF MEMS fabrication process. The resulting device achieves low insertion loss, a very high quality factor, high reliability, high linearity and high self actuation robustness. The second type introduces two novel concepts of area efficient, ultra-wideband, MEMS-reconfigurable coupled line directional couplers, whose coupling is tuned by mechanically changing the geometry of 3-D micromachined coupled transmission lines, utilizing integrated MEMS electrostatic actuators. The coupling is achieved by tuning both the ground and the signal line coupling, obtaining a large tuneable coupling ratio while maintaining an excellent impedance match, along with high isolation and a very high directivity over a very large bandwidth. This thesis also presents for the first time on RF nonlinearity analysis of complex multi-device RF MEMS circuits. Closed-form analytical formulas for the IIP3 of MEMS multi-device circuit concepts are derived. A nonlinearity analysis, based on these formulas and on  measured device parameters, is performed for different circuit concepts and compared to the simulation results of multi-device  conlinear electromechanical circuit models. The degradation of the overall circuit nonlinearity with increasing number of device stages is investigated. Design rules are presented so that the mechanical parameters and thus the IIP3 of the individual device stages can be optimized to achieve a highest overall IIP3 for the whole circuit.The thesis further investigates un-patterned ferromagnetic NiFe/AlN multilayer composites used as advanced magnetic core materials for on-chip inductances. The approach used is to increase the thickness of the ferromagnetic material without increasing its conductivity, by using multilayer NiFe and AlN sandwich structure. This suppresses the induced currents very effectively and at the same time increases the ferromagnetic resonance, which is by a factor of 7.1 higher than for homogeneous NiFe layers of same thickness. The so far highest permeability values above 1 GHz for on-chip integrated un-patterned NiFe layers were achieved. / <p>QC 20140328</p>

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This thesis presents the study and characterization of organic light-emitting diodes (OLEDs) with the proposal of obtaining an equivalent model that is useful in the OLED driver design and in lighting systems projects. Initially, a literature review covering the operating principle and the constructive aspects of OLEDs is presented. From this, a model that integrates scale, photometrical, electrical and thermal aspects is proposed. This model is static and dynamic and is called EFET. A procedure for parameter identification of the model is proposed, jointly with an analysis of the intrinsic capacitance effect on the OLED electrical, thermal and photometrical performance. The proposed model is able to predict and simulate the OLED based lighting systems before building, saving time and cost. The model is validated using different OLED samples and conclusions are derived from the experimental validation and simulation results. An approach considering the dimming methods of OLEDs is presented, showing the chromatic impact caused by each method. Finally, an OLED driver based on the concept of switched capacitor converters is proposed. The thesis results are satisfactory and provide an enhancement to the state of the art in modeling and OLED driving. / A presente tese de doutorado apresenta o estudo e a caracterização de diodos orgânicos emissores de luz (OLEDs) com a proposta de um modelo equivalente que é útil no desenvolvimento de circuitos de acionamento e na análise de OLEDs, quando aplicados em sistemas de iluminação. Inicialmente, é apresentada uma revisão bibliográfica contemplando o princípio de funcionamento e os aspectos construtivos dos OLEDs. A partir disto, um modelo que integra os aspectos de escala, fotométricos, elétricos e térmicos é proposto. Esse modelo é denominado EFET e é dividido em estático e dinâmico. Uma proposta de procedimento para identificação dos parâmetros do modelo é apresentada, juntamente com a análise do efeito da capacitância intrínseca dos OLEDs no seu desempenho elétrico, térmico e fotométrico. Com o modelo proposto pode-se predizer e simular o comportamento dos OLEDs antes de construir o sistema de iluminação, reduzindo custos e tempo de desenvolvimento. O modelo é validado empregando diferentes amostras de OLEDs. Conclusões são obtidas a partir da validação experimental e de simulações empregando simuladores elétricos e da fluidodinâmica computacional através do método de elementos finitos. Uma abordagem considerando os métodos de ajuste da intensidade luminosa de OLEDs é apresentada, evidenciando o impacto cromático provocado por cada método. Por fim, um circuito de acionamento para OLEDs baseado no conceito de capacitores chaveados é proposto. Os resultados obtidos são satisfatórios e proporcionam um incremento ao estado da arte da modelagem e acionamento de OLEDs.

Thesis describes analog filters topologies with capability of tuning of the main parameters and the MOSFET-C and switched-capacitor filters are described. With focus to linearity and maximal tuning range optimal topology have been chosen. In work the issue of analog switch design is described and is solved. Design of switched-capacitor low-pass Sallen-key filter in Cadence software was made and simulation results are presented.

Abstract The goal of this dissertation was to study and model the settling transient response of switched-capacitor (SC) circuit, which is the most important building block of Analog-to-Digital converters (ADCs), and to improve the settling performance of the SC circuit implemented in ADC in CMOS technology. In the design of the SC circuit, there are common obstacles in obtaining a precise and fast settling with low power consumption. The main contribution of this thesis is to speed up different SC circuits without adding extra power consumption or to achieve the required settling precision with low power consumption. Two solutions to reduce the power consumption of SC integrators in sigma-delta (SD) ADCs were designed and verified by simulations. These implementations are based on the passive charge redistribution technique by injecting a precalculated open-loop charge in the output of the first integrator. The injected charge was implemented either by a continuous function of the input and feedback voltages or by quantizing to three levels. In both cases, the idea is to minimize the initial transient voltage in the input of the first OTA and hence bypass the slewing of the OTA. Another approach was proposed for the traditional SC residue circuit of the pipeline ADC, where a load capacitor is connected to the output during the evaluation phase. Here, a pre-charge of the load capacitance can be used. One proposed implementation is called the continuously controlled pre-charged technique. It pre-charges the load capacitor to the proper voltage during the previous phase, connects the pre-charged load capacitor to the output of the OTA during the evaluation phase, and hence pulls the charge sharing so that the initial input step of the OTA is instantaneously minimized. The other implementation called the minimal pre-charged method implemented for the SC residue circuit of the pipeline ADC is to simply pre-charge the load capacitor with the fixed existing voltage, minimized the spread of the initial input voltage. This proposed technique did not require any additional active components. / Tiivistelmä Kytkettyihin kapasitansseihin (SC-tekniikka) perustuvat vahvistimet ovat CMOS-tekniikkaan perustuvien analogia-digitaalimuuntimien (AD-muunnin) tärkeimpiä osia. Tämän väitöstyön tavoitteena oli tutkia ja mallittaa SC-tekniikkaan perustuvien vahvistinpiirien asettumisaikaa, ja etsiä piiriteknisiä keinoja asettumisajan nopeuttamiseksi. SC-piirien suunnittelun suurimpia ongelmia on saavuttaa tarkka ja nopea asettuminen mahdollisimman pienellä tehonkulutuksella. Tämän työn päätuloksina on joukko keinoja, joilla voidaan nopeuttaa SC-kytkettyjen vahvistimien asettumista ilman että niiden tehonkulutusta lisätään, tai saavuttaa aiempi suorituskyky pienemmällä tehonkulutuksella. Menetelmät perustuvat siihen, että SC-piirin passiivista varausjakautumista ohjataan niin, että vahvistimen tulosolmussa oleva transientti minimoituu, jolloin vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelle, vaan sen asettuminen nopeutuu merkittävästi. Sigma-delta-tyyppiset AD-muuntimet koostuvat SC-integraattoreista, ja näiden asettumisen nopeuttamiseen kehitettiin ja varmennettiin simuloiden kaksi tapaa. Varauksen jakautumista autettiin syöttämällä erillisellä varauspumpulla transkonduktanssivahvistimen lähtösolmuun tietty, integraattorin tilasta ja tuloista riippuva varaus. Tällöin vahvistimen tulossa näkyvä alkutransientti pienenee, ja vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelleen, jolloin sen asettumisvirhe pienenee merkittävästi. Varausinjektio toteutettiin kahdella eri tavalla: laskemalla tarvittava varaus joko jatkuvana funktiona tulosignaaleista, tai approksimoimalla sitä muutamalla diskreetillä tasolla. Pipeline-tyyppisissä AD-muuntimissa peruslohko koostuu SC-kytketystä vahvistimesta, jonka kuormakapasitanssi on kytkettynä vahvistimen lähtöön asettumisen aikana. Tämän kapasitanssin esivaraaminen sopivasti tarjoaa hyvin yksinkertaisen keinon ohjata varausjakautumista niin, että vahvistimen tulossa oleva transientti saadaan minimoitua ja toiminta virtarajoitteisessa moodissa vältettyä. Tässäkin tapauksessa kehitettiin ja varmennettiin kaksi vaihtoehtoista toteutusta. Ensimmäisessä kuormakapasitanssin esivarausjännite lasketaan tulosuureiden jatkuvana funktiona erillisellä summausvahvistimella. Toisessa, hyvin minimalistisessa ratkaisussa esivaraukseen käytetään kolmea käytettävissä olevaa kiinteää jännitettä. Tämä menetelmä ei vaadi lainkaan ylimääräisiä aktiivikomponentteja.

Indiana University-Purdue University Indianapolis (IUPUI) / This research proposes state-of-the-art multilevel converter topologies and their modulation strategies, the implementation of a conventional flying-capacitor converter topology up to four-level, and a new four-level flying-capacitor H-Bridge converter confi guration. The three phase version of this proposed four-level flying-capacitor H-Bridge converter is given as well in this study. The highlighted advantages of the proposed converter are as following: (1) the same blocking voltage for all switches employed in the con figuration, (2) no capacitor midpoint connection is needed, (3) reduced number of passive elements as compared to the conventional solution, (4) reduced total dc source value by comparison with the conventional topology. The proposed four-level capacitor-clamped H-Bridge converter can be utilized as a multilevel inverter application in an electri fied railway system, or in hybrid electric vehicles. In addition to the implementation of the proposed topology in this research, its experimental setup has been designed to validate the simulation results of the given converter topologies.