Due to the superior characteristics compared to its silicon (Si) counterpart, the wide bandgap (WBG) semiconductor enables next-generation power electronics systems with higher efficiency and higher power density. With higher blocking voltage available, WBG devices, especially the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), have been widely explored in various medium-voltage (MV) applications in both industry and academia. However, due to the high di/dt and high dv/dt during the switching transient, potential overcurrent, overvoltage, and gate failure can greatly reduce the reliability of implementing SiC MOSFETs in an MV system. By utilizing the parasitic inductance between the Kelvin- and the power-source terminal, a short-circuit (SC) and overload (OL) dual-protection scheme is proposed for overcurrent protection. A full design procedure and reliability analysis are given for SC circuit design. A novel OL circuit is proposed to protect OL faults at the gate-driver level. The protection procedure can detect an SC fault within 50 nanoseconds and protect the device within 1.1 microsecond. The proposed method is a simple and effective solution for the potential overcurrent problem of the SiC MOSFET. For SiC MOSFETs in series-connection, the unbalanced voltages can result in system failure due to device breakdown or unbalanced thermal stresses. By injecting current during the turn-off transient, an active dv/dt control method is used for voltage balancing. A 6 kV phase-leg using eight 1.7 kV SiC MOSFETs in series-connection has been tested with voltage balanced accurately. Modeling of the stacked SiC MOSFET with active dv/dt control is also done to summarize the design methodology for an effective and stable system. This method provides a low-loss and compact solution for overvoltage problems when MV SiC MOSFETs are connected in series. Furthermore, a scalable auxiliary power network is proposed to prevent gate failure caused by unstable gate voltage or EMI interference. The two-stage auxiliary power network (APN) architecture includes a wireless power transfer (WPT) converter supplied by a grounded low voltage dc bus, a high step-down-ratio (HSD) converter powered from dc-link capacitors, and a battery-based mini-UPS backup power supply. The auxiliary-power-only pre-charge and discharge circuits are also designed for a 6 kV power electronics building block (PEBB). The proposed architecture provides a general solution of a scalable and reliable auxiliary power network for the SiC-MOSFET-based MV converter. For the WPT converter, a multi-objective optimization on efficiency, EMI mitigation, and high voltage insulation capability have been proposed. Specifically, a series-series-CL topology is proposed for the WPT converter. With the optimization and new topology, a 120 W, 48 V to 48 V WPT converter has been tested to be a reliable part of the auxiliary power network. For the HSD converter, a novel unidirectional voltage-balancing circuit is proposed and connected in an interleaved manner, which provides a fully modular and scalable solution. A ``linear regulator + buck" solution is proposed to be an integrated on-board auxiliary power supply. A 6 kV to 45 V, 100 W converter prototype is built and tested to be another critical part of the auxiliary power network. / Doctor of Philosophy / The wide bandgap semiconductor enables next-generation power electronics systems with higher efficiency and higher power density which will reduce the space, weight, and cost for power supply and conversion systems, especially for renewable energy. However, by pushing the system voltage level higher to medium-voltage of tens of kilovolts, although the system has higher efficiency and simpler control, the reliability drops. This dissertation, therefore, focusing on solving the possible overcurrent, overvoltage, and gate failure issues of the power electronics system that is caused by the high voltage and high electromagnetic interference environment. By utilizing the inductance of the device, a dual-protection method is proposed to prevent the overcurrent problem. The overcurrent fault can be detected within tens of nanoseconds so that the device will not be destroyed because of the huge fault current. When multiple devices are connected in series to hold higher voltage, the voltage sharing between different devices becomes another issue. The proposed modeling and control method for series-connected devices can balance the shared voltage, and make the control system stable so that no overvoltage problem will happen due to the non-evenly distributed voltages. Besides the possible overcurrent and overvoltage problems, losing control of the devices due to the unreliable auxiliary power supply is another issue. This dissertation proposed a scalable auxiliary power network with high efficiency, high immunity to electromagnetic interference, and high reliability. In this network, a wireless power transfer converter is designed to provide enough insulation and isolation capability, while a switched capacitor converter is designed to transfer voltage from several kilovolts to tens of volts. With the proposed overcurrent protection method, voltage sharing control, and reliable auxiliary power network, systems utilizing medium-voltage wide-bandgap semiconductor will have higher reliability to be implemented for different applications.

This thesis presents a novel Resonant Switched-Capacitor Converter with Multiple Resonant Frequencies, abbreviated as MRSCC for both high density and efficiency non-isolated large step-down Intermediate Bus Converter (IBC). Conventional Resonant Switched-Capacitor Converter (RSCC) proposed by Shoyama and its high voltage conversion ratio derivation such as Switched-Tank Converter (STC) by Jiang and li employ half sinusoidal-current charge transfer method between capacitors to achieve high efficiency and density operation by adding a small resonant inductor in series to pure switched-capacitor converter's (SCC) flying capacitor. By operating switching frequency to be the same as its resonant frequency, RSCC achieves zero-current turn off operation, however, this cause RSCC and its derivation suffer from component variation issue for high-volume adoption. Derived from RSCC, MRSCC adds additional high frequency resonant component, operates only during its dead-time, by adding small capacitor in parallel to RSCC's resonant inductor. By operating switching frequency higher than its main resonant frequency, MRSCC utilizes double chopped half-sinusoidal current charge transfer method between capacitors to further improve efficiency. In addition, operating switching frequency consistently higher than its resonant frequency, MRSCC provides high immunity towards component variation, making it and its derivation viable for high-volume adoption. / MS / Following the recent trend, most internet services are moving towards cloud computing. Large data applications and growing popularity of cloud computing require hyperscale data centers and it will continue to grow rapidly in the next few years to keep up with the demand [4]. These cutting-edge data centers will require higher performance multi-core CPU and GPU installations which translates to higher power consumption. From 10MWatts of power, typical data centers deliver only half of this power to the computing load which includes processors, memory and drives. Unfortunately, the rest goes to losses in power conversion, distribution and cooling [5]. Industry members look into increasing backplane voltage from 12V to 48V in order to reduce distribution loss. This thesis proposes a novel Resonant Switched-Capacitor Converter using Multiple Resonant Frequencies to accommodate this increase of backplane voltage.

Two new classes of soft switching pulse-width-modulated (PWM) converters, named zero-voltage-switched (ZVS) PWM converters and zero-voltage-transition (ZVT) PWM converters, are proposed. The proposed ZVS-PWM converters combine the merits of conventional PWM and ZVS-QRC techniques. They are capable of regulating the output for a wide load and input voltage range while maintaining constant-frequency operation. By employing a saturable inductor, the load range under which ZVS is maintained can be significantly extended without increasing the voltage stress of the power switch. The parasitic oscillations between the diode junction capacitance and the resonant inductor are also significantly reduced. In the new class of ZVT-PWM converters, both the power switch and the rectifier diode are operated with zero-voltage switching, and are subjected to low voltage and current stresses associated with those in their PWM counterparts. Thus switching losses are significantly reduced at a slight increase in conduction losses. In addition, the circuit optimization is simplified because of constant-frequency operation. The operation principles of the proposed converters are described by using several examples. Several breadboarded converters are implemented to verify the theoretical analysis and to demonstrate the feasibility of the proposed technologies. / Master of Science

This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power by keeping the feedback factor of the active adder unity. However, the inherent delay originated from the DCT adder will cause instability to the modulator and complex additional branches are usually needed to stabilize the loop. A simple and power-efficient technique is proposed to absorb the delay from the DCT adder and the instability issue is therefore solved. Another proposed low-power design technique is to feed differentiated inverted quantization noise to the input of the last integrator. The modulator noise-shaping order with this proposed technique is effectively increased from two to three without adding additional active elements. The delta-sigma ADC with the proposed architectural design techniques has been implemented in transistor-level and fabricated in 0.18 µm CMOS technology. Measurement results showed a SNDR of 99.3 dB, a DR of 101.3 dB and a SFDR of 112 dB over 20 kHz signal bandwidth, resulting in a very low figure-of-merit (FoM) in its application category. Finally, two new circuit ideas, low-power parasitic-insensitive switched-capacitor integrator for delta-sigma ADCs and switched-resistor tuning technique for highly linear Gm-C filter design are presented. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from June 9, 2012 - June 9, 2014

This dissertation presents the design and development of a mixed-signal low noise second-order integrated circuit (IC) for the open-loop and closed-loop operation of integrated capacitive micro- and nano-gravity accelerometers. The micromechanical accelerometers are fabricated in thick (less than 100 m) silicon-on-insulator (SOI) substrates. The IC provides the 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power consumption (less than 5 mW) and maximum dynamic range (90 dB). A fully-differential sampled-data scheme is deployed with the ability of low-frequency noise reduction through the use of correlated double sampling (CDS) scheme. In this work, the measured resolution of the closed-loop CMOS-SOI accelerometer system, in the presence of high background accelerations, is in the micro-g (g: gravity) range. In this design, a second-order SC modulator is cascaded with the accelerometer and the front-end amplifier. The accelerometer operates in air and is designed for non-peaking response with a BW-3dB of 500 Hz. A 22 dB improvement in noise and hence dynamic range is achieved with a sampling clock of 40 kHz corresponding to a low oversampling ratio (OSR) of 40. The interface IC consumed a current of 1.5 mA from a supply of 3 V.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005. / A switching state substitution must be developed that will make use of both single-phase redundancies and three-phase redundancies in the flying-capacitor topology. Losses should be taken into consideration and the algorithm must be designed for implementation on the existing PEC33 system, with on-board DSP (TMS320VC33) and FPGA (EP1K50QC208). The specific power-electronics application is a medium-voltage active filter. Existing capacitor voltage stabilisation schemes are investigated and a capacitor-voltage based algorithm is developed that is investigated in parallel with the Donzel and Bornard algorithm. Detailed simulation models are built for the evaluation of both existing and the proposed algorithm. Three-phase control is also evaluated. Timing analysis of the proposed algorithm shows that a DSP-only implementation of the proposed capacitor-based solution is not feasible. Detail design of the digital controller hereof is implemented in VHDL. Finally, a four-cell controller is fitted into the FPGA. A scalable hardware sorting architecture is utilised.

Analog-to-Digital Converters (ADCs) can be classified into two categories namely Nyquist-rate ADCs and OversampledADCs. Nyquist-rate ADCs can process very high bandwidths while Oversampling ADCs provide high resolution using coarse quantizers and support lower input signal bandwidths. This work describes a Reconfigurable ADC (R-ADC) architecture which models 14 different ADCs utilizing four four-bit flash ADCs and four Reconfigurable Blocks (RBs). Both Nyquist-rate and Oversampled ADCs are included in the reconfiguration scheme. The R-ADC supports first- and second-order Sigma-Delta (ΣΔ) ADCs. Cascaded ΣΔ ADCs which provide high resolution while avoiding the stability issues related to higher order ΣΔ loops are also included. Among the Nyquist-rate ADCs, pipelined and time interleaved ADCs are modeled. A four-bit flash ADC with calibration is used as the basic building block for all ADC configurations. The R-ADC needs to support very high sampling rates (1 GHz to 2 GHz). Hence switched-capacitor (SC) based circuits are used for realizing the loop filters in the ΣΔ ADCs. The pipelined ADCs also utilize an SC based block called Multiplying Digital-to-Analog Converter (MDAC). By analyzing the similarities in structure and function of the loop filter and MDAC, a RB has been designed which can accomplish the function of either block based on the selected configuration. Utilizing the same block for various configurations reduces power and area requirements for the R-ADC. In SC based circuits, the minimum sampling capacitance is limited by the thermal noise that can be tolerated in order to achieve a specific ENOB. The thermal noise in a ΣΔ ADC is subjected to noise shaping. This results in reduced thermal noise levels at the inputs of successive loop filters in cascaded or multi-order ΣΔ ADCs. This property can be used to reduce the sampling capacitance of successive stages in cascaded and multi-order ΣΔ ADCs. In pipelined ADCs, the thermal noise in successive stages are reduced due to the inter-stage gain of the MDAC in each stage. Hence scaling of sampling capacitors can be applied along the pipeline stages. The RB utilizes the scaling of capacitor values afforded by the noise shaping property of ΣΔ loops and the inter-stage gain of stages in pipelined ADCs to reduce the total capacitance requirement for the specified Effective Number Of Bits (ENOB). The critical component of the RB is the operational amplifier (opamp). The speed of operation and ENOB for different configurations are determined by the 3 dB frequency and DC gain of the opamp. In order to find the specifications of the opamp, the errors introduced in ΣΔ and pipelined ADCs by the finite gain and bandwidth of the opamp were modeled in Matlab.The gain and bandwidth requirements for the opamp were derived from the simulation results. Unlike Nyquist-rate ADCs, the ΣΔ ADCs suffer from stability issues when the input exceeds a certain level. The maximum usable input level is determined by the resolution of the quantizer and the order of the loop filter in the ΣΔADC. Using Matlab models, the maximum value of input for different oversampling ADC configurations in the R-ADC were found. The results obtained from simulation are comparable to the theoretical values. The cascaded ADCs require digital filter functions which enable the cancellation of quantization noise from certain stages. These functions were implemented in Matlab. For the R-ADC, these filter functions need to run at very high sampling rates. The ΣΔ loop filter transfer functions were chosen such that their coefficients are powers of two, which would allow them to be implemented as shift and add operations instead of multiplications. The R-ADC configurations were simulated in Matlab. A schematic for the R-ADC was developed in Cadence using ideal switches and a finite gain, single-pole operational transconductance amplifier model. The ADC configuration was selected by four external bits. Performance parameters such as SNR, SNDR and SFDR obtained from simulations in Cadence agree with those from Matlab for all ADC configurations.

This thesis presents a new DC/AC inverter circuit which is based on a switched-capacitor circuit topology with reduced components (power switch and capacitor) count for low power applications. The proposed circuit has distinct features of both voltage boost-up and near sinusoidal (multi-level/staircase) AC output voltage. The main idea is to utilise a simple circuit technique called resonant-based Double Switch Single Capacitor Switched-Capacitor (DSSC SCC) with variable duty cycle Pulse Width Modulation (PWM) control technique in such a way that multi-level voltage can be realised across a capacitor. In order to show the superiority of the applied technique, comparisons with other techniques/circuits configurations are presented. The circuit technique can significantly reduce the number of multiple stages of switched-capacitor circuit cells of the recent switched-capacitor multi-level inverter topology. The proposed inverter (with integrated DSSC SCC technique) can generate a line-frequency with 13-levels near sinusoidal AC output voltage with low total harmonics distortion. The output voltage can be achieved with the least number of components use and only a single DC source is used as an input. The proposed inverter topology is also reviewed against other inverter-based switched-capacitor circuit topology and the well-known multi-level inverter topology. The proposed inverter has shown a tremendous reduction in the total harmonics distortion and circuit component count in comparison with the recent Switched-Capacitor Boost multi-level inverter and the classical Cascaded H-Bridge multi-level inverter. Mathematical analysis shows the design of the proposed inverter and PSPICE simulation result to verify the design is also presented. The practical experiment implementation of the proposed system is presented and proves the correct operation of the proposed inverter topology by showing consistency between simulation results and practical results.

The most accurate method for performing analog signal processing in MOS (metal-oxide-semiconductor) integrated circuits is through the use of switched-capacitor circuits. A switched-capacitor circuit operates as a discrete-time signal processor. These circuits have been used in a variety of applications, such as filters, gain stages, voltage-controlled oscillators, and modulators. A switched-capacitor circuit contains operational amplifiers (opamps), capacitators, switches, and a clock generator. Capacitors are used to define the state variables of a system. They store charges for a defined time interval, and determine the state variables as voltage differences. Switches are used to direct the flow of charges and to enable the charging and discharging of capacitors. Nonoverlapping clock signals control the switches and allow charge transfer between the capacitors. Opamps are used in order to perform high-accuracy charge transfer from one capacitor to another. The goal of this research is to design and explore future low-voltage switched-capacitor circuits, which are crucial for portable devices. Low-voltage operation is needed for two reasons: making reliable and accurate systems compatible with the submicron CMOS technology and reducing power consumption of the digital circuits. To this end, three different switched-capacitor integrators are proposed, which function with very low supply voltages. One of these configurations is used to design a lowpass ����� modulator for digital-audio applications. This modulator is fabricated and tested demonstrating 80 dB dynamic range with a 1-V supply voltage. The second part of this research is to show that these low-voltage circuits are suitable for modern wireless communication applications, where the clock and signal frequencies are very high. This part of the research has focused on bandpass analog-to-digital converters. Bandpass analog-to-digital converters are among the key components in wireless communication systems. They are used to digitize the received analog signal at an intermediate center frequency. Such converters are used for digital FM or AM radio applications and for portable communication devices, such as cellular phones. The main block, in these converters, is the resonator, which is tuned to a particular center frequency. A resonator must be designed such that it has a sharp peak at a specific center frequency. However, because of circuit imperfections, the resonant peak gain and/or the center frequency are degraded in existing architectures. Two novel switched-capacitor resonators were invented during the second part of this research. These resonators demonstrate superior performance as compared to previous architectures. A fourth-order low-voltage bandpass ����� modulator, using one of these resonators, has been designed. / Graduation date: 2002

Uno de los campos más importantes de la Electrónica de Potencia es el de los convertidores de potencia conmutados, que debido a sus características de alto rendimiento energético, reducido tamaño, posibilidades de regulación del factor de potencia y de elevación de tensión, etc., están presentes en un gran número de las etapas de alimentación de los equipos electrónicos actuales.Las mejoras tecnológicas en ámbitos como el de la integración de circuitos han permitido importantes reducciones en el tamaño de los equipos (por ejemplo en los ordenadores). Sin embargo, este proceso de reducción de tamaño que, además, suele venir unido a unas especificaciones más rígidas en cuanto a costes, rendimiento, seguridad y prestaciones en general, no se ha producido en igual medida en las etapas de alimentación. El estudio de los convertidores conmutados es por lo tanto un campo necesitado de esfuerzos de investigación y desarrollo.Para potencias superiores a 25 W, y especialmente en potencias superiores a 150 W, una de las estrategias utilizadas para mejorar las prestaciones de los convertidores es el uso del denominado "interleaving" o entrelazado , definido como la puesta en paralelo de N convertidores idénticos desfasando sus señales de control de forma uniforme a lo largo del periodo de conmutación.Con el objetivo principal de reducir al máximo los rizados de la tensión de salida y de la corriente de entrada, en esta tesis se estudian casos particulares de "interleaving" en estructuras convertidoras continua-continua que utilizan el convertidor elevador ("boost") como célula básica y cuyas tensiones de salida son, idealmente y operando en modo de conducción continua, múltiplos enteros positivos de la tensión de entrada, de ahí la denominación de multiplicadores de tensión que aparece en el título de tesis propuesto. Posteriormente se analizan las posibilidades de regulación de tensión que presentan algunos de los casos de estudio, a costa de incrementar los rizados.