The objective of this investigation was to develop micro/nano-scale temperature sensors for measuring surface temperature transients in multi-phase flows and heat transfer. Surface temperature fluctuations were measured on substrates exposed to phase change processes. Prior reports in the literature indicate that these miniature scale surface temperature fluctuations can result in 60-90 percent of the total heat flux during phase change heat transfer. In this study, DTS (Diode Temperature Sensors) were fabricated with a doping depth of ~100 nm on n-type silicon to measure the surface temperature transients on a substrate exposed to droplet impingement cooling. DTS are expected to have better sensor characteristics compared to TFTs (Thin Film Thermocouples), due to their small size and faster response (which comes at the expense of the smaller operating temperature range). Additional advantages of DTS include the availability of robust commercial micro fabrication processes (with diode and transistor node sizes currently in the size range of ~ 30 nm), and that only 2N wire leads can be used to interrogate a set of N x N array of sensors (in contrast thermocouples require 2 N x N wire leads for N x N sensor array). The DTS array was fabricated using conventional semi-conductor processes. The temperature response of the TFT and DTS was also calibrated using NIST standards. Transient temperature response of the DTS was recorded using droplet impingement cooling experiments. The droplet impingement cooling experiments were performed for two different test fluids (acetone and ethanol). An infrared camera was used to verify the surface temperature of the substrate and compare these measurements with the temperature values recorded by individual DTS. PVD (Physical Vapor Deposition) was used for obtaining the catalyst coatings for subsequent CNT synthesis using CVD (Chemical Vapor Deposition) as well as for fabricating the thin film thermocouple (TFT) arrays using the "lift-off" process. Flow boiling experiments were conducted for three different substrates. Flow boiling experiments on bare silicon wafer surface were treated as the control experiment, and the results were compared with that of CNT (Carbon Nano-Tube) coated silicon wafer surfaces. Similar experiments were also performed on a pure copper surface. In addition, experiments were performed using compact condensers. Micro-scale patterns fabricated on the refrigerant side of the compact heat exchanger were observed to cause significant enhancement of the condensation heat transfer coefficient.

Tantalum diffusion barrier coatings were investigated as a way to improve the conversion efficiency of CIGS (copper indium gallium diselenide) solar cells.  Tantalum coatings were deposited upon silicon and stainless steel foil substrates using direct current magnetron sputtering (DcMS) and high power impulse magnetron sputtering (HiPIMS).  The coatings were characterized using scanning electron microscopy (SEM).  Cross-sectional scanning electron micrographs revealed that the HiPIMS coatings appeared denser than the DcMS coatings.

A novel polymer semiconductor with side chains thermally cleavable at a low temperature of 200 °C was synthesized. The complete cleavage and removal of the insulating 2-octyldodecanoyl side chains were verified with TGA, FT-IR, and NMR data. The N-H groups on the native polymer backbone are expected to form intermolecular hydrogen bonds with the C=O groups on the neighboring polymer chains to establish 3-D charge transport networks. The resulting side chain-free conjugated polymer is proven to be an active p-type semiconductor material for organic thin film transistors (OTFTs), exhibiting hole mobility of up to 0.078 cm2V-1s-1. This thermo-cleavable polymer was blended with PDQT to form films that showed a higher performance than the pure individual polymers in OTFTs. MoO3 or NPB was used as a hole injection buffer layer between the metal electrodes and the polymer semiconductor film layer in OTFT devices. This buffer layer improved hole injection, while its use in the OTFT, improved the field-effect mobility significantly due to better matched energy levels between the electrodes and the polymer semiconductor.

Hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) are used as charge switches in flat-panel X-ray detectors. The inherent noise in the TFTs contributes to the overall noise figure of the detectors and degrades the image quality. Measurements of the noise provide an important parameter for modeling the performance of the detectors and are a sensitive diagnostic tool for device quality. Furthermore, understanding the origins of the noise could lead to change a method of a-Si:H deposition resulting in a reduction of the noise level. This thesis contains measurements of the low-frequency noise in a-Si:H TFTs with an inverted staggered structure. The noise power density spectrum fits well to a power law with Ñ near one. The normalized noise power is inversely proportional to gate voltage and also inversely proportional to channel length in both the linear and saturation regions. The noise is nearly independent of the drain-source voltage and drain-source current. The noise is unaffected by degrading the amorphous silicon through gate-biasing stress. Hooge¡¦s parameter is in the range 1-2*E-3 or 2-4*E-4 depending on whether the parameter is calculated using the total number of charge carriers in the accumulation layer or just the number of free carriers. As an example, the signal to noise ratio is calculated for photodiode detector gated by a TFT using the results from the noise measurements.

Increasing attention has been directed towards the development of optically transparent and mechanically flexible thin film transistors (TFTs) and associated circuits based on the transition metal oxides. These flexible see-through structures offer reduced weight, potential low-cost fabrication, and high performance compared to commonly used hydrogenated amorphous silicon (a-Si:H) in applications for large-area electronics and displays. As these emerging technologies evolve towards commercialization, a thorough investigation of the impacts of the thermo-mechanical stress and strain and their effects on the electrical and mechanical stability of the flexible microelectronic devices have become increasingly necessary. However, not much progress has been reported in this area, and the numerical modeling of the flexible transistors with the Finite Element Method (FEM) would provide unique insight to the design and operation of the flexible TFTs. In this thesis, numerical models of flexible TFTs are built up by COMSOL Multiphysics and compared with analytical models to reach the best agreement between the experimental measurements and the numerical analyses. These simulations provide additional insight into the local stress induced strain within the device due to both intrinsic and applied stress. It was shown that the thermal and mechanical impacts on the TFT performance can be reduced by placing the vital active layer of the flexible device near the neutral mechanical plane or by proper designing the device structure and processing conditions based on the data derived from the numerical models. The mathematical analysis and numerical simulation will be used to improve the electrical and mechanical performance and the reliability of the transistors for flexible applications.

No description available.

Thin film transistor (TFT) backplanes are being continuously researched for new applications such as active-matrix organic light emitting diode (AMOLED) displays, sensors, and x-ray imagers. However, the circuits implemented in presently available fabrication technologies including poly silicon (poly-Si), hydrogenated amorphous silicon (a-Si:H), and organic semiconductor, are prone to spatial and/or temporal non-uniformities. While current-programmed active matrix (AM) can tolerate mismatches and non-uniformity caused by aging, the long settling time is a significant limitation. Consequently, acceleration schemes are needed and are proposed to reduce the settling time to 20 µs. This technique is used in the development of a pixel circuit and system for biomedical imager and sensor. Here, a metal-insulator-semiconductor (MIS) capacitor is adopted for adjustment and boost of the circuit gain. Thus, the new pixel architecture supports multi-modality imaging for a wide range of applications with various input signal intensities. Also, for applications with lower current levels, a fast current-mode line driver is developed based on positive feedback which controls the effect of the parasitic capacitance. The measured settling time of a conventional current source is around 2 ms for a 100-nA input current and 200-pF parasitic capacitance whereas it is less than 4 μs for the driver presented here. For displays needed in mobile devices such as cell phones and DVD players, another new driving scheme is devised that provides for a high temporal stability, low-power consumption, high tolerance of temperature variations, and high resolution. The performance of the new driving scheme is demonstrated in a 9-inch fabricated display intended for DVD players. Also, a multi-modal imager pixel circuit is developed using this technique to provide for gain-adjustment capability. Here, the readout operation is not destructive, enabling the use of low-cost readout circuitry and noise reduction techniques. In addition, a highly stable and reliable driving scheme, based on step calibration is introduced for high precision displays and imagers. This scheme takes advantage of the slow aging of the electronics in the backplane to simplify the drive electronics. The other attractive features of this newly developed driving scheme are its simplicity, low-power consumption, and fast programming critical for implementation of large-area and high-resolution active matrix arrays for high precision.

Hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) has been used in active matrix liquid crystal displays (LCDs) and medical x-ray imagers, in which the TFT acts as pixel switches. However, instability of a-Si:H TFT is a major issue in applications where TFTs are also required to function as analogue circuit elements, such as in emerging organic light emitting diode (OLED) displays. It is known that a-Si:H TFT shows drain current degradation under electrical operation, due to two instability mechanisms: (i) defect creation in the a-Si:H active layer, and (ii) charge trapping in the gate dielectric. Nanocrystalline silicon (nc-Si) TFT has been proposed as a high performance alternative. Therefore, this thesis focuses on the design of nc-Si TFT and its outstanding issues, in the industry standard bottom-gate structure. The key for obtaining a stable TFT lies in developing a highly crystalline nc-Si active layer, without the so-called amorphous incubation layer. Therefore, processing of nc-Si by plasma enhanced chemical vapor deposition (PECVD) is studied and PECVD parameters are optimized. It is shown that very thin (15 nm) layers with crystallinity of around 60% can be obtained. Moreover, it is possible to eliminate the amorphous incubation layer, as transmission electron microscope (TEM) images showed that crystalline grains start growing immediately upon deposition at the gate dielectric interface. The nc-Si TFT reported in this work advances the state-of-the-art, by demonstrating that defect state creation is absent in the nc-Si active layer, which is deduced by performing several characterization techniques. In addition, with the proper design of the nitride gate dielectric, i.e. by using a nitrogen-rich nitride, the charge trapping instability can be minimized. Thus, it is shown that the nc-Si TFT is much more stable than the a-Si:H counterpart. Another issue with nc-Si TFT is its high drain leakage current, i.e. off-current. It is shown that off-current is determined by the conductivity of nc-Si active layer, and also affected by the quality of the silicon/passivation nitride interface. The off-current can be minimized by using a bi-layer structure so that a thin (15 nm) nc-Si is capped with a thin (35nm) a-Si:H, and values as low as 0.1 pA can be obtained. The low off-current along with superior stability of nc-Si TFT, coupled with its fabrication in the industry standard 13.56 MHz PECVD system, make it very attractive for large area applications such as pixel drivers in active matrix OLED displays and x-ray imagers.

Thin film transistors (TFTs), the heart of highly functional and ultra-compact active-matrix (AM) backplanes, have driven explosive growth in both the variety and utility of large-area electronics over the past few decades. Nanocrystalline silicon (nc-Si:H) TFTs have recently attracted attention as a high-performance and low-cost alternative to existing amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) TFTs, in that they have the strong potentials which a-Si:H (low carrier mobility and poor device stability) and poly-Si (poor device uniformity and high manufacturing cost) counterparts do not have. However, the current nc-Si:H TFTs expose several challenging material and devices issues, on which the dissertation focuses. In our material study, the growth of gate-quality SiO2 films and highly conductive nc-Si:H contacts based on conventional plasma-enhanced chemical vapor deposition (PECVD) is systematically investigated, which can lead to high performance, reproducibility, predictability, and stability in the nc-Si:H TFTs. Particularly to overcome a low field effect mobility in the p-channel transistors, the possibility of B(CH3)3 as an alternative dopant source to current B2H6 is examined. The resultant p-doped nc-Si:H contacts demonstrate comparable performance to the state of the art with the maximum dark conductivity of 1.11 S/cm over 70% film crystallinity. Based on the highest-quality SiO2 and nc-Si:H contacts developed, complementary (n- and p-channel) top-gate nc-Si:H TFTs with a staggered source/drain geometry are designed, fabricated, and characterized. The n-channel TFTs demonstrate a threshold voltage VTn of 6.4 V, a field effect mobility of electrons μn of 15.54 cm2/Vs, a subthreshold slope S of 0.67 V/decade, and an on/off current ratio Ion/Ioff of 10^5, while the corresponding p-channel TFTs exhibit VTp of -26.2 V, μp of 0.24 cm2/Vs, S of 4.72 V/ decade, and Ion/Ioff of 10^4. However, the TFTs show significant non-ideal behaviors that considerably limit device performance: high leakage current in the off-state, transconductance degradation under high gate bias, and threshold voltage instability in time. Quantitative insight into each non-ideality is provided in this research. Our study on the off-state conduction in the nc-Si:H TFTs reveals that the responsible mechanism for high leakage current, particularly at a high bias regime, is largely due to Poole-Frenkel emission of trapped carriers in the reverse-biased drain depletion region. This could be effectively suppressed by proposed offset-gated structure without compromising the on-state performance. A numerical analysis of the transconductance degradation shows that the parasitic resistance components that are present in the nc-Si:H TFTs strongly degrade transconductance and thus a field effect mobility. Correspondingly, strategies for reduction in parasitic resistance of the TFT are presented. Lastly, the threshold voltage shift in the nc-Si:H TFT is attributed to the flatband voltage shift, which is mainly due to charge trapping in the PECVD SiO2 gate dielectric. Material and device study, and physical insight into non-ideal behaviors in the top-gate nc-Si:H TFTs reported in the dissertation constitute an arguably important step towards monolithic integration of pixels and peripheral driving circuits on a versatile active-matrix TFT backplane for high-performance and low-cost large-area electronics. However, the gate dielectric and the highly doped nc-Si:H contacts, still imposing considerable challenges, may require entirely new approaches.

Thin film transistors (TFTs) have brought prominent growth in both variety and utility of large area electronics market over the past few decades. Nanocrystalline silicon (nc-Si:H) TFTs have attracted attention recently, due to high-performance and low-cost, as an alternative of amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) TFTs. The nc-Si:H TFTs has higher carrier mobility and better device stability than a-Si:H TFTs while lower manufacturing cost than poly-Si TFTs. However, current nc-Si:TFTs have several challenging issues on materials and devices, on which this thesis focuses. In the material study, the gate quality silicon nitride (a-SiNx) films and doped nc-Si:H contacts based on conventional plasma enhanced chemical vapor deposition (PECVD) are investigated. The feasibility of a-SiNx on TFT application is discussed with current-voltage (I-V)/capacitance-voltage(C-V) measurement and Fourier Transform Infrared Spectroscopy (FTIR) results which demonstrate 4.3 MV/cm, relative permittivity of 6.15 and nitrogen rich composition. The doped nc-Si:H for contact layer of TFTs is characterized with Raman Spectroscopy and I-V measurements to reveal 56 % of crystalinity and 0.42 S/cm of dark conductivity. Inverted staggered TFT structure is fabricated for nc-Si:H TFT device research using fully wet etch fabrication process which requires five lithography steps. The process steps are described in detail as well as adaptation of the fabrication process to a backplane fabrication for direct conversion X-ray imagers. The modification of TFT process for backplane fabrication involves two more lithography steps for mushroom electrode formation while other pixel components is incorporated into the five lithography step TFT process. The TFTs are electrically characterized demonstrating 7.22 V of threshold voltage, 0.63 S/decade of subthreshold slope, 0.07 cm2/V•s of field effect mobility, and 106 of on/off ratio. The transfer characteristics of TFTs reveal a severe effect of parasitic resistance which is induced from channel layer itself, a contact between channel layer and doped nc-Si:H contact layer, the resistance of doped nc-Si:H contact layer, and a contact between the doped nc-Si:H layer and source/drain metal electrodes. The parasitic resistance effect is investigated using numerical simulation method by various parasitic resistances, channel length of the TFT, and intrinsic properties of nc-Si:H channel layer. It reveals the parasitic resistance effect become severe when the channel is short and has better quality, therefore, several further research topics on improving contact nc-Si:H quality and process adjustment are required.