The aim of this master thesis has been to design, and partly manufacture and evaluate, a highly miniaturized, on-chip conductivity-temperature-depth (CTD) sensor system for deepwater analysis also including electrodes for pH and chloride ion concentration measurements. The microtechnology-based sensor system will be a vital instrument onboard the Deeper Access, Deeper Understanding submersible, which will be small enough for deployment through bore holes into the subglacial lakes of Antarctica. Design of the complete 15 x 30 mm chip, including variations of each sensor type (in total 39 sensors), is presented. Salinity (through conductivity), temperature, chloride ion concentration and pH sensors have been manufactured using conventional lithography, evaporation, wet etching and lift off techniques. Simulations of the pressure sensors (not manufactured) show how the set of four bossed membranes with integrated strain gauges combine to cover, yet withstand, pressures of 1-100 atm. Salinity is measured conductively with gold electrodes. The temperature sensor is a platinum thermoresistor. Chloride ion concentration and pH are measured potentiometrically with ion-selective microelectrodes of silver/silver chloride and iridium oxide, respectively. Tests of the conductivity sensor gave good results also on sea water samples of known salinity. The temperature sensor showed good linearity to a reference sensor in the tested range of 5-35 C. Issues with evaporation and lift off are discussed, and a process identification document is attached. / DADU

Thin film transistor (TFT) backplanes are being continuously researched for new applications such as active-matrix organic light emitting diode (AMOLED) displays, sensors, and x-ray imagers. However, the circuits implemented in presently available fabrication technologies including poly silicon (poly-Si), hydrogenated amorphous silicon (a-Si:H), and organic semiconductor, are prone to spatial and/or temporal non-uniformities. While current-programmed active matrix (AM) can tolerate mismatches and non-uniformity caused by aging, the long settling time is a significant limitation. Consequently, acceleration schemes are needed and are proposed to reduce the settling time to 20 µs. This technique is used in the development of a pixel circuit and system for biomedical imager and sensor. Here, a metal-insulator-semiconductor (MIS) capacitor is adopted for adjustment and boost of the circuit gain. Thus, the new pixel architecture supports multi-modality imaging for a wide range of applications with various input signal intensities. Also, for applications with lower current levels, a fast current-mode line driver is developed based on positive feedback which controls the effect of the parasitic capacitance. The measured settling time of a conventional current source is around 2 ms for a 100-nA input current and 200-pF parasitic capacitance whereas it is less than 4 μs for the driver presented here. For displays needed in mobile devices such as cell phones and DVD players, another new driving scheme is devised that provides for a high temporal stability, low-power consumption, high tolerance of temperature variations, and high resolution. The performance of the new driving scheme is demonstrated in a 9-inch fabricated display intended for DVD players. Also, a multi-modal imager pixel circuit is developed using this technique to provide for gain-adjustment capability. Here, the readout operation is not destructive, enabling the use of low-cost readout circuitry and noise reduction techniques. In addition, a highly stable and reliable driving scheme, based on step calibration is introduced for high precision displays and imagers. This scheme takes advantage of the slow aging of the electronics in the backplane to simplify the drive electronics. The other attractive features of this newly developed driving scheme are its simplicity, low-power consumption, and fast programming critical for implementation of large-area and high-resolution active matrix arrays for high precision.

Hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) has been used in active matrix liquid crystal displays (LCDs) and medical x-ray imagers, in which the TFT acts as pixel switches. However, instability of a-Si:H TFT is a major issue in applications where TFTs are also required to function as analogue circuit elements, such as in emerging organic light emitting diode (OLED) displays. It is known that a-Si:H TFT shows drain current degradation under electrical operation, due to two instability mechanisms: (i) defect creation in the a-Si:H active layer, and (ii) charge trapping in the gate dielectric. Nanocrystalline silicon (nc-Si) TFT has been proposed as a high performance alternative. Therefore, this thesis focuses on the design of nc-Si TFT and its outstanding issues, in the industry standard bottom-gate structure. The key for obtaining a stable TFT lies in developing a highly crystalline nc-Si active layer, without the so-called amorphous incubation layer. Therefore, processing of nc-Si by plasma enhanced chemical vapor deposition (PECVD) is studied and PECVD parameters are optimized. It is shown that very thin (15 nm) layers with crystallinity of around 60% can be obtained. Moreover, it is possible to eliminate the amorphous incubation layer, as transmission electron microscope (TEM) images showed that crystalline grains start growing immediately upon deposition at the gate dielectric interface. The nc-Si TFT reported in this work advances the state-of-the-art, by demonstrating that defect state creation is absent in the nc-Si active layer, which is deduced by performing several characterization techniques. In addition, with the proper design of the nitride gate dielectric, i.e. by using a nitrogen-rich nitride, the charge trapping instability can be minimized. Thus, it is shown that the nc-Si TFT is much more stable than the a-Si:H counterpart. Another issue with nc-Si TFT is its high drain leakage current, i.e. off-current. It is shown that off-current is determined by the conductivity of nc-Si active layer, and also affected by the quality of the silicon/passivation nitride interface. The off-current can be minimized by using a bi-layer structure so that a thin (15 nm) nc-Si is capped with a thin (35nm) a-Si:H, and values as low as 0.1 pA can be obtained. The low off-current along with superior stability of nc-Si TFT, coupled with its fabrication in the industry standard 13.56 MHz PECVD system, make it very attractive for large area applications such as pixel drivers in active matrix OLED displays and x-ray imagers.

Thin film transistors (TFTs), the heart of highly functional and ultra-compact active-matrix (AM) backplanes, have driven explosive growth in both the variety and utility of large-area electronics over the past few decades. Nanocrystalline silicon (nc-Si:H) TFTs have recently attracted attention as a high-performance and low-cost alternative to existing amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) TFTs, in that they have the strong potentials which a-Si:H (low carrier mobility and poor device stability) and poly-Si (poor device uniformity and high manufacturing cost) counterparts do not have. However, the current nc-Si:H TFTs expose several challenging material and devices issues, on which the dissertation focuses. In our material study, the growth of gate-quality SiO2 films and highly conductive nc-Si:H contacts based on conventional plasma-enhanced chemical vapor deposition (PECVD) is systematically investigated, which can lead to high performance, reproducibility, predictability, and stability in the nc-Si:H TFTs. Particularly to overcome a low field effect mobility in the p-channel transistors, the possibility of B(CH3)3 as an alternative dopant source to current B2H6 is examined. The resultant p-doped nc-Si:H contacts demonstrate comparable performance to the state of the art with the maximum dark conductivity of 1.11 S/cm over 70% film crystallinity. Based on the highest-quality SiO2 and nc-Si:H contacts developed, complementary (n- and p-channel) top-gate nc-Si:H TFTs with a staggered source/drain geometry are designed, fabricated, and characterized. The n-channel TFTs demonstrate a threshold voltage VTn of 6.4 V, a field effect mobility of electrons μn of 15.54 cm2/Vs, a subthreshold slope S of 0.67 V/decade, and an on/off current ratio Ion/Ioff of 10^5, while the corresponding p-channel TFTs exhibit VTp of -26.2 V, μp of 0.24 cm2/Vs, S of 4.72 V/ decade, and Ion/Ioff of 10^4. However, the TFTs show significant non-ideal behaviors that considerably limit device performance: high leakage current in the off-state, transconductance degradation under high gate bias, and threshold voltage instability in time. Quantitative insight into each non-ideality is provided in this research. Our study on the off-state conduction in the nc-Si:H TFTs reveals that the responsible mechanism for high leakage current, particularly at a high bias regime, is largely due to Poole-Frenkel emission of trapped carriers in the reverse-biased drain depletion region. This could be effectively suppressed by proposed offset-gated structure without compromising the on-state performance. A numerical analysis of the transconductance degradation shows that the parasitic resistance components that are present in the nc-Si:H TFTs strongly degrade transconductance and thus a field effect mobility. Correspondingly, strategies for reduction in parasitic resistance of the TFT are presented. Lastly, the threshold voltage shift in the nc-Si:H TFT is attributed to the flatband voltage shift, which is mainly due to charge trapping in the PECVD SiO2 gate dielectric. Material and device study, and physical insight into non-ideal behaviors in the top-gate nc-Si:H TFTs reported in the dissertation constitute an arguably important step towards monolithic integration of pixels and peripheral driving circuits on a versatile active-matrix TFT backplane for high-performance and low-cost large-area electronics. However, the gate dielectric and the highly doped nc-Si:H contacts, still imposing considerable challenges, may require entirely new approaches.

Thin film transistors (TFTs) have brought prominent growth in both variety and utility of large area electronics market over the past few decades. Nanocrystalline silicon (nc-Si:H) TFTs have attracted attention recently, due to high-performance and low-cost, as an alternative of amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) TFTs. The nc-Si:H TFTs has higher carrier mobility and better device stability than a-Si:H TFTs while lower manufacturing cost than poly-Si TFTs. However, current nc-Si:TFTs have several challenging issues on materials and devices, on which this thesis focuses. In the material study, the gate quality silicon nitride (a-SiNx) films and doped nc-Si:H contacts based on conventional plasma enhanced chemical vapor deposition (PECVD) are investigated. The feasibility of a-SiNx on TFT application is discussed with current-voltage (I-V)/capacitance-voltage(C-V) measurement and Fourier Transform Infrared Spectroscopy (FTIR) results which demonstrate 4.3 MV/cm, relative permittivity of 6.15 and nitrogen rich composition. The doped nc-Si:H for contact layer of TFTs is characterized with Raman Spectroscopy and I-V measurements to reveal 56 % of crystalinity and 0.42 S/cm of dark conductivity. Inverted staggered TFT structure is fabricated for nc-Si:H TFT device research using fully wet etch fabrication process which requires five lithography steps. The process steps are described in detail as well as adaptation of the fabrication process to a backplane fabrication for direct conversion X-ray imagers. The modification of TFT process for backplane fabrication involves two more lithography steps for mushroom electrode formation while other pixel components is incorporated into the five lithography step TFT process. The TFTs are electrically characterized demonstrating 7.22 V of threshold voltage, 0.63 S/decade of subthreshold slope, 0.07 cm2/V•s of field effect mobility, and 106 of on/off ratio. The transfer characteristics of TFTs reveal a severe effect of parasitic resistance which is induced from channel layer itself, a contact between channel layer and doped nc-Si:H contact layer, the resistance of doped nc-Si:H contact layer, and a contact between the doped nc-Si:H layer and source/drain metal electrodes. The parasitic resistance effect is investigated using numerical simulation method by various parasitic resistances, channel length of the TFT, and intrinsic properties of nc-Si:H channel layer. It reveals the parasitic resistance effect become severe when the channel is short and has better quality, therefore, several further research topics on improving contact nc-Si:H quality and process adjustment are required.

Hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) are used as charge switches in flat-panel X-ray detectors. The inherent noise in the TFTs contributes to the overall noise figure of the detectors and degrades the image quality. Measurements of the noise provide an important parameter for modeling the performance of the detectors and are a sensitive diagnostic tool for device quality. Furthermore, understanding the origins of the noise could lead to change a method of a-Si:H deposition resulting in a reduction of the noise level. This thesis contains measurements of the low-frequency noise in a-Si:H TFTs with an inverted staggered structure. The noise power density spectrum fits well to a power law with Ñ near one. The normalized noise power is inversely proportional to gate voltage and also inversely proportional to channel length in both the linear and saturation regions. The noise is nearly independent of the drain-source voltage and drain-source current. The noise is unaffected by degrading the amorphous silicon through gate-biasing stress. Hooge¡¦s parameter is in the range 1-2*E-3 or 2-4*E-4 depending on whether the parameter is calculated using the total number of charge carriers in the accumulation layer or just the number of free carriers. As an example, the signal to noise ratio is calculated for photodiode detector gated by a TFT using the results from the noise measurements.

No description available.

Non-volatile memory is slower than DRAM (Dynamic Random Access Memory) but faster than HDD (Hard Disk Drive). In addition, compared to volatile memory, the non-volatile memory can retain stored information without power, and consume only low power. These characteristics show its popularity of flash memory built in portable devices. Currently the non-volatile memory applies the polysilicon and SONOS structure as floating gate, however, the new technologies of nanocrystal non-volatile memory are processed at high temperature. The manufacturing cost is rather high, so the process at lower temperature is very necessary. In this work, mixed zinc and silica amorphous layers are applied as floating gate to construct nano thin film non-volatile memory devices. The process does not need high temperature to form crystalline, and the defects in zinc oxide can be applied for charge storage. Supercritical carbon dioxide (SCCO2) treatment has been studied for the passivation of dielectric and reducing the activation energy. Using this low-temperature SCCD process ZnO nanocrystal can be formed, and the feasibility of fabricating nanocrystal NVMs device with low temperature SCCO2 is possible. The nonvolatile memory devices with Zn nano thin film embedded in MIS structure are performed. From C-V measurement, it is found that defects in SiO2 are repaired after 500¢J annealing. Because of the thermal diffusion, the storage layer SiO2/Zn-SiO2/SiO2 in device cannot be observed and the memory window disappears when the annealing temperature is higher than 700¢J. Therefore, the annealing process should be performed between 500¢J - 700¢J in making memory device. From DLTS analysis, a species with energy level of 0.6 eV is found in the as deposited Zn-SiO2 layer. After annealing in Ar, a new energy level 0.47 eV is found, and which shifts to energy level 0.85 eV after annealing in O2. In comparison to XPS results, traps of Zn-SiO2 exist before annealing, and after annealing in Ar, Zn-SiO2 transforms into Zn-O-Si. Traps of ZnO-SiO2 have been found after annealing in O2, which increases the memory effect with a 2 Volt memory window, so that more charges can be stored in the deep level traps of ZnO-SiO2 in the storage layer.

Polycrystalline Cu(In,Al)Se2 films were deposited by four-source evaporation of Cu, In, Al, and Se using Knudsen type sources in which the elemental fluxes were coincident onto soda lime glass substrates. The single-phase films with composition of Cu:In:Al:Se = 28:15:9:48 which were confirmed by X-ray diffraction and micro-Raman spectroscopy were deposited at substrate temperature of 560¢J. Secondary phases were observed when temperature of substrate is below 560¢J due to incompletely reaction. Under fixed effusion flux, the value of Cu/(In+Al) becomes larger as temperature of substrate increase. However, the value of Al/(In+Al) keeps nearly constant as temperature increase. The band gap is 1.53 eV derived from the result of spectrophotometer. The room temperature resistivity, Hall mobility and carrier concentration of the films are 0.28 £[cm, 24.63 cm2V-1s-1 and 1.27x1019 cm-3 respectively. And the conductive type is p-type. By the way, we try to grow Cu(In,Al)Se2 film in the presence of an Sb beam at substrate temperature of 440¢J. After the addition of an Sb beam, surface morphology become smooth and compact, but there is no significant grain growth. No matter an Sb beam adds or not, secondary phases were observed in both case due to the low temperature of substrate.

Since the first discovery of amorphous alloys in 1960, researchers have explored many unique mechanical, magnetic, and optical characteristics of such materials for potential applications. Up to now, well-developed processes, such as rapid quenching, sputtering, evaporation, pulse laser deposition, etc, have been applied for different applications in micro-electro-mechanical systems (MEMS). Due to the lack of ordered structure, amorphous alloys can bear a high stress in the elastic region. Their plastic deformation stability is also of interest and has been widely studied. The shear-band characteristic, a kind of inhomogeneous deformation mechanism, dominates the deformation after yielding at room temperature. While a shear band nucleate, its propagation usually cannot be arrested or stopped. In other words, the occurrence of matured shear bands needs to be prevented. There are two major approaches in this aspect. The first is to increase the material yield strength so as to delay the shear band nucleation. Another is to incorporate intrinsic or extrinsic particles so as to absorb the kinetic energy of shear bands in the amorphous matrix. In this study, we utilize three strategies to control the propagation of shear bands in thin film metallic glasses (TFMGs): sub-Tg annealing, the addition of strong element in solute form, and the introduction of strong nanocrystalline layers. For sub-Tg annealing, the base alloy system is Zr69Cu31, with a base film hardness of 5.1 GPa measured by nanoindentation. After annealing, the hardness exhibits ~30% increase. Without the occurrence of the phase transformation, as confirmed by X-ray diffraction, the possible reaction during sub-Tg annealing is attributed to structural relaxation, not crystallization. The full width at half maximum of the X-ray peak exhibits a decreasing trend in the using X-ray and transmission electron microscopy diffraction, meaning the excess free volumes forming during vapor-to-solid deposition process would be annihilated by localized atomic re-arrangement. Moreover, the formation of medium-ordering-range clusters was confirmed utilizing high-resolution transmission electronic microscopy. The denser amorphous structure leads to the increment of hardness. For the addition of Ta in Zr55Cu31Ti14, sputtering provides a wide glass forming range with solubility of Ta approaching ~75 at%. With increasing Ta content, the elastic modulus and hardness increase slowly. A steep rise occurs at ~50 at% of Ta. Up to 75 at% of Ta, the elastic modulus and hardness approaches 140 GPa and 10.0 GPa, respectively (100% increment). Up to now, Ta-rich TFMGs exhibit the highest elastic modulus and hardness among all amorphous alloys fabricated using vapor deposition techniques. The irregular increase is attributed to the formation of Ta-Ta bonding. A large quantity of Ta bonds would lead to the formation of Ta-rich nanoclusters, drastically decreasing the strain rate while shear band propagates under nanoindentation and microcompression tests. The introduction of nanocrystalline Ta layers can not only effectively enhance the yield strength but also serve as the absorber for the kinetic energy of shear bands, revealing ductility in the microcompression test.