<p>The last few decades have been a very exciting period in thedevelopment of micro-electronics and brought us to the brink ofimplementing entire systems on a single chip, on a hithertounimagined scale. However an unforeseen challenge has croppedup in the form of managing wires, which have become the mainbottleneck in performance, masking the blinding speed of activedevices. A major problem is that increasingly complicatedeffects need to be modelled, but the computational complexityof any proposed model needs to be low enough to allow manyiterations in a design cycle.</p><p>This thesis addresses the issue of closed form modelling ofthe response of coupled interconnect systems. Following astrict mathematical approach, second order models for thetransfer functions of coupled RC trees based on the first andsecond moments of the impulse response are developed. The2-pole-1-zero transfer function that is the best possible fromthe available information is obtained for the signal path fromeach driver to the output in multiple aggressor systems. Thisallows the complete response to be estimated accurately bysumming up the individual waveforms. The model represents theminimum complexity for a 2-pole-1-zero estimate, for this classof circuits.</p><p>Also proposed are new techniques for the optimisation ofwires in on-chip buses. Rather than minimising the delay overeach individual wire, the configuration that maximises thetotal bandwidth over a number of parallel wires isinvestigated. It is shown from simulations that there is aunique optimal solution which does not necessarily translate tothe maximum possible number of wires, and in fact deviatesconsiderably from it when the resources available for repeatersare limited. Analytic guidelines dependent only on processparameters are derived for optimal sizing of wires andrepeaters.</p><p>Finally regular tiled architectures with a commoncommunication backplane are being proposed as being the mostefficient way to implement systems-on-chip in the deepsubmicron regime. This thesis also considers the feasibility ofimplementing a regular packet-switched network-on-chip in atypical future deep submicron technology. All major physicalissues and challenges are discussed for two differentarchitectures and important limitations are identified.</p>

La complexité des architectures de communication avioniques ne cesse de croître avec l’augmentation du nombre des terminaux interconnectés et l’expansion de la quantité des données échangées. Afin de répondre aux besoins émergents en terme de bande passante, latence et modularité, l’architecture de communication avionique actuelle consiste à utiliser le réseau AFDX (Avionics Full DupleX Switched Ethernet) pour connecter les calculateurs et utiliser des bus d’entrée/sortie (par exemple le bus CAN (Controller Area Network)) pour connecter les capteurs et les actionneurs. Les réseaux ainsi formés sont connectés en utilisant des équipements d’interconnexion spécifiques, appelés RDC (Remote Data Concentrators) et standardisé sous la norme ARINC655. Les RDCs sont des passerelles de communication modulaires qui sont reparties dans l’avion afin de gérer l’hétérogénéité entre le réseau cœur AFDX et les bus d’entrée/sortie. Certes, les RDCs permettent d’améliorer la modularité du système avionique et de réduire le coût de sa maintenance; mais, ces équipements sont devenus un des défis majeurs durant la conception de l’architecture avionique afin de garantir les performances requises du système. Les implémentations existantes du RDC effectuent souvent une translation direct des trames et n’implémentent aucun mécanisme de gestion de ressources. Or, une utilisation efficace des ressources est un besoin important dans le contexte avionique afin de faciliter l’évolution du système et l’ajout de nouvelles fonctions. Ainsi, l’objectif de cette thèse est la conception et la validation d’un RDC optimisé implémentant des mécanismes de gestion des ressources afin d’améliorer les performances de l’architecture de communication avionique tout en respectant les contraintes temporelles du système. Afin d’atteindre cet objectif, un RDC pour les architectures réseaux de type CAN-AFDX est conçu, intégrant les fonctions suivantes: (i) groupement des trames appliqué aux flux montants, i.e., flux générés par les capteurs et destinés à l’AFDX, pour minimiser le coût des communication sur l’AFDX; (ii) la régulation des flux descendants, i.e., flux générés par des terminaux AFDX et destinés aux actionneurs, pour réduire les contentions sur le bus CAN. Par ailleurs, notre RDC permet de connecter plusieurs bus CAN à la fois tout en garantissant une isolation entre les flux. Par la suite, afin d’analyser l’impact de ce nouveau RDC sur les performances du système avionique, nous procédons à la modélisation de l’architecture CAN-AFDX, et particulièrement le RDC et ses nouvelles fonctions. Ensuite, nous introduisons une méthode d’analyse temporelle pour calculer des bornes maximales sur les délais de bout en bout et vérifier le respect des contraintes temps-réel. Plusieurs configurations du RDC peuvent répondre aux exigences du système avionique tout en offrant des économies de ressources. Nous procédons donc au paramétrage du RDC afin de minimiser la consommation de bande passante sur l’AFDX tout en respectant les contraintes temporelles. Ce problème d’optimisation est considéré comme NP-complet, et l’introduction des heuristiques adéquates s’est avérée nécessaire afin de trouver la meilleure configuration possible du RDC. Enfin, les performances de ce nouveau RDC sont validées à travers une architecture CAN-AFDX réaliste, avec plusieurs bus CAN et des centaines de flux échangés. Différents niveaux d’utilisation des bus CAN ont été considérés et les résultats obtenus ont montré l’efficacité de notre RDC à améliorer la gestion des ressources du système avionique tout en respectant les contraintes temporelles de communication. En particulier, notre RDC offre une réduction de la bande passante AFDX allant jusqu’à 40% en comparaison avec le RDC actuellement utilisé. / The aim of my thesis is to provide a resources-efficient gateway to connect Input/Output (I/O) CAN buses to a backbone network based on AFDX technology, in modern avionics communication architectures. Currently, the Remote Data Concentrator (RDC) is the main standard for gateways in avionics; and the existing implementations do not integrate any resource management mechanism. To handle these limitations, we design an enhanced CAN-AFDX RDC integrating new functions: (i) Frame Packing (FP) allowing to reduce communication overheads with reference to the currently used "1 to 1" frame conversion strategy; (ii) Hierarchical Traffic Shaping (HTS) to reduce contention on the CAN bus. Furthermore, our proposed RDC allows the connection of multiple I/O CAN buses to AFDX while guaranteeing isolation between different criticality levels, using a software partitioning mechanism. To analyze the performance guarantees offered by our proposed RDC, we considered two metrics: the end-to-end latency and the induced AFDX bandwidth consumption. Furthermore, an optimization process was proposed to achieve an optimal configuration of our proposed RDC, i.e., minimizing the bandwidth utilization while meeting the real-time constraints of communication. Finally, the capacity of our proposed RDC to meet the emerging avionics requirements has been validated through a realistic avionics case study.

This master’s thesis deals with project management and the proposal of processing of processes centralized procurement purchases. It mentions the issue of theoretical knowledge in project management and planning and principles for legislation of public procurement. Includes analysis of company and of the solved problem, including the proposed solution.

The subject of Diploma thesis is the design of bridge on the highway Jánovce - Jablonov and his static solution. Selected variant is made from four span 34+44+44+34m and supporting structure consist of monolithic two beams of prestressed concrete. Height of cross section is over the whole lenght of the bridge constant. Each beams will be built on sliding formwork. The design of supporting structure is made according to limit states, including addressing timing analysis. Calculation of the effects of loading is made by software and reviews are calculated by hand according to Eurocode.

The project is dedicated to the identification of the problems found while building RT operating systems for use in embedded devices. The project's main topic is the possibility of using RT system in the FITkit platform and it also discusses individual problems and their possible solutions. One of the problems is the way of acquiring the timing information for tasks to ensure their RT properties. We have extended existing simulator for given microcontroller that is also part of the FITkit. The simulator can be used for detailed monitoring of the execution of individual tasks in the system based on dynamic analysis, collecting timing statistics for given blocks of the program or it can be extended by new modules. The RM scheduling mechanism has been integrated into the FreeRTOS system as an example by considering the knowledge of the concrete operating system and acquired timing information.

Aujourd'hui, les applications automobiles sont devenues de plus en plus complexes avec des ressources limitées et plus de contraintes de temps et de safety. La vérification temporelle est effectuée très tard aujourd'hui au cours du processus de développement automobile (après l'implémentation et au cours de la phase d'intégration). Pour apporter des solutions aux problèmes du développement logiciel automobile, plusieurs approches de développement dirigé par les modèles ont été définit. Ces approches donnent des langages, des concepts et des méthodologies pour la description de l'architecture des systèmes automobiles. Cependant, ces approches ne donnent aucun guide méthodologique pour intégrer l'analyse temporelle (notamment l'analyse d'ordonnancement) tout au long du processus de développement. Ce travail de thèse propose de développer une méthodologie décrivant un processus d'analyse temporelle dirigé par les modèles. Cette méthodologie décrit les différentes phases du processus de développement dirigé par les modèles et comment l'analyse temporelle est effectuée durant chaque phase. / Automotive systems are characterized today by increasing complexity, limited resources and more and more timing and safety requirements. Timing verification is performed too late during the development process. It is addressed by means of measurements and tests rather than through formal and systematic analysis. To meet the challenges of automotive software development, many model-based approaches have been developed. These approaches give modeling languages, concepts and methodologies allowing the description of automotive architecture. However, these approaches give no guidance for the integration of timing analysis (mainly scheduling analysis) during the phases of the model-based development process. This PhD work aims at defining a methodology that describes a model-based timing analysis process. This methodology describes the different phases of the model-based development process and how timing analysis is performed during each phase. This work has been performed in the context of a technical collaboration between Continental Automotive and the CEA laboratory.

Designing Resilient Distributed embedded Systems is a challenging task. One of the design issues is to guarantee correct behavior of the system during the runtime. It demands verification that information propagated through the system is reliable. The goal of this thesis is a research and implementation of an analysis that should identify obsolescence of variables due to delays caused by scheduling and communication in real-time systems. Analysis will be designed for Ensemble-Based Component System (EBCS) semantics because it enables precise specification and analysis of important properties. The main problem is to find a suitable input model of the analysis and find its possible limits. Effort should be put in balancing between the level of abstraction given to a RDS developer and power of the analysis itself. The main benefit of the analysis will be detection of situations in which data processed in RDS are outdated and can cause incorrect behavior of particular components.

<p>Real-time systems do not only require that the logical operations are correct. Equally important is that the specified time constraints always are complied. This has successfully been studied before for mono-processor systems. However, as the hardware in the systems gets more complex, the previous approaches become invalidated. For example, multi-processor systems-on-chip (MPSoC) get more and more common every day, and together with a shared memory, the bus access time is unpredictable in nature. This has recently been resolved, but a safe and not too pessimistic cache analysis approach for MPSoC has not been investigated before. This thesis has resulted in designed and implemented algorithms for cache analysis on real-time MPSoC with a shared communication infrastructure. An additional advantage is that the algorithms include improvements compared to previous approaches for mono-processor systems. The verification of these algorithms has been performed with the help of data flow analysis theory. Furthermore, it is not known how different types of cache miss characteristic of a task influence the worst case execution time on MPSoC. Therefore, a program that generates randomized tasks, according to different parameters, has been constructed. The parameters can, for example, influence the complexity of the control flow graph and average distance between the cache misses.</p>

Frontend and backend wearout mechanisms are major reliability concerns for modern microprocessors. In this research, a framework which contains modules for negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate-oxide breakdown (GOBD), backend time-dependent dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV) is proposed to analyze the impact of each wearout mechanism on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Taking into account the detailed thermal profiles, electrical stress profiles and a variety of use scenarios, composed of a fraction of time in operation, a fraction of time in standby, and a fraction of time when the system is off, this work provides insight into lifetime-limiting wearout mechanisms, along with the reliability-critical microprocessor functional units for a system. This enables circuit designers to know if their designs will achieve an adequate lifetime and further make any updates in the designs to enhance reliability prior to committing the designs to manufacture.

La prédictibilité est un aspect important des systèmes temps-réel critiques. Garantir la fonctionnalité de ces systèmespasse par la prise en compte des contraintes temporelles. Les architectures mono-cœurs traditionnelles ne sont plussuffisantes pour répondre aux besoins croissants en performance de ces systèmes. De nouvelles architectures multi-cœurssont conçues pour offrir plus de performance mais introduisent d'autres défis. Dans cette thèse, nous nous intéressonsau problème d’accès aux ressources partagées dans un environnement multi-cœur.La première partie de ce travail propose une approche qui considère la modélisation de programme avec des formules desatisfiabilité modulo des théories (SMT). On utilise un solveur SMT pour trouverun chemin d’exécution qui maximise le temps d’exécution. On considère comme ressource partagée un bus utilisant unepolitique d’accès multiple à répartition dans le temps (TDMA). On explique comment la sémantique du programme analyséet le bus partagé peuvent être modélisés en SMT. Les résultats expérimentaux montrent une meilleure précision encomparaison à des approches simples et pessimistes.Dans la deuxième partie, nous proposons une analyse de temps de réponse de programmes à flot de données synchroness'exécutant sur un processeur pluri-cœur. Notre approche calcule l'ensemble des dates de début d'exécution et des tempsde réponse en respectant la contrainte de dépendance entre les tâches. Ce travail est appliqué au processeur pluri-cœurindustriel Kalray MPPA-256. Nous proposons un modèle mathématique de l'arbitre de bus implémenté sur le processeur. Deplus, l'analyse de l'interférence sur le bus est raffinée en prenant en compte : (i) les temps de réponseet les dates de début des tâches concurrentes, (ii) le modèle d'exécution, (iii) les bancsmémoires, (iv) le pipeline des accès à la mémoire. L'évaluation expérimentale est réalisé sur desexemples générés aléatoirement et sur un cas d'étude d'un contrôleur de vol. / Predictability is of paramount importance in real-time and safety-critical systems, where non-functional properties --such as the timing behavior -- have high impact on the system's correctness. As many safety-critical systems have agrowing performance demand, classical architectures, such as single-cores, are not sufficient anymore. One increasinglypopular solution is the use of multi-core systems, even in the real-time domain. Recent many-core architectures, such asthe Kalray MPPA, were designed to take advantage of the performance benefits of a multi-core architecture whileoffering certain predictability. It is still hard, however, to predict the execution time due to interferences on sharedresources (e.g., bus, memory, etc.).To tackle this challenge, Time Division Multiple Access (TDMA) buses are often advocated. In the first part of thisthesis, we are interested in the timing analysis of accesses to shared resources in such environments. Our approach usesSatisfiability Modulo Theory (SMT) to encode the semantics and the execution time of the analyzed program. To estimatethe delays of shared resource accesses, we propose an SMT model of a shared TDMA bus. An SMT-solver is used to find asolution that corresponds to the execution path with the maximal execution time. Using examples, we show how theworst-case execution time estimation is enhanced by combining the semantics and the shared bus analysis in SMT.In the second part, we introduce a response time analysis technique for Synchronous Data Flow programs. These are mappedto multiple parallel dependent tasks running on a compute cluster of the Kalray MPPA-256 many-core processor. Theanalysis we devise computes a set of response times and release dates that respect the constraints in the taskdependency graph. We derive a mathematical model of the multi-level bus arbitration policy used by the MPPA. Further,we refine the analysis to account for (i) release dates and response times of co-runners, (ii)task execution models, (iii) use of memory banks, (iv) memory accesses pipelining. Furtherimprovements to the precision of the analysis were achieved by considering only accesses that block the emitting core inthe interference analysis. Our experimental evaluation focuses on randomly generated benchmarks and an avionics casestudy.