Relays can be used in wireless communication systems to provide cell coverage extension, reduce coverage holes and increase throughput. Full duplex (FD) relays, which transmit and receive in the same time slot, can have a higher transmission rate compared with half duplex (HD) relays. However, FD relays suffer from self interference (SI) problems, which are caused by the transmitted relay signal being received by the relay receiver. This can reduce the performance of FD relays. In the literature, the SI channel is commonly nulled and removed as it simplifies the problem considerably. In practice, complete nulling is impossible due to channel estimation errors. Therefore, in this thesis, we consider the leakage of the SI from the FD relay. Our goal is to reduce the SI and increase the signal to noise ratio (SNR) of the relay system. Hence, we propose different precoder and weight vector designs. These designs may increase the end to end (e2e) signal to interference and noise ratio (SINR) at the destination. Here, a precoder is multiplied to a signal before transmission and a weight vector is multiplied to the received signal after reception. Initially, we consider an academic example where it uses a two path FD multiple input and multiple output (MIMO) system. The analysis of the SINR with the implementation of precoders and weight vectors shows that the SI component has the same underlying signal as the source signal when a relay processing delay is not being considered. Hence, to simulate the SI problem more realistically, we alter our relay design and focus on a one path FD MIMO relay system with a relay processing delay. For the implementation of precoders and weight vectors, choosing the optimal scheme is numerically challenging. Thus, we design the precoders and weight vectors using ad-hoc and near-optimal schemes. The ad-hoc schemes for the precoders are singular value decomposition (SVD), minimising the signal to leakage plus noise ratio (SLNR) using the Rayleigh Ritz (RR) method and zero forcing (ZF). The ad-hoc schemes for the weight vectors are SVD, minimum mean squared error (MMSE) and ZF. The near-optimal scheme uses an iterative RR method to compute the source precoder and destination weight vector and the relay precoder and weight vector are computed using the ad-hoc methods which provide the best performance. The average power and the instantaneous power normalisations are the two methods to constrain the relay precoder power. The average power normalisation method uses a novel closed form covariance matrix with an optimisation approach to constrain the relay precoder. This closed form covariance matrix is mathematically derived using matrix vectorization techniques. For the instantaneous power normalisation method, the constraint process does not require an optimisation approach. However, using this method the e2e SINR is difficult to calculate, therefore we use symbol error rate (SER) as a measure of performance. The results from the different precoder and weight vector designs suggest that reducing the SI using the relay weight vector instead of the relay precoder results in a higher e2e SINR. Consequently, to increase the e2e SINR, performing complicated processing at the relay receiver is more effective than at the relay transmitter.

Le sujet de recherche prévoit l'amélioration des performances des inductances actives de type TOSI (transistor only simulated inductor), réalisées en technologie CMOS pour des applications de filtrage RF. Ces structures montrent de bien meilleures performances que les filtres classiques Gm–C par le petit nombre de transistors, la consommation d'énergie, la bande de fréquence et la surface du circuit intégré. En outre, les architectures TOSI peuvent être utilisées pour d'autres applications potentielles, comme les amplificateurs LNA et oscillateurs (VCO ou CCO). Dans le contexte du trend multi-standard suivi par les circuits de télécommunications (notamment sans fil), les filtres RF basés sur le concept TOSI offrent la possibilité de mise en œuvre des dispositifs accordables. pour répondre aux exigences des normes de télécommunications, la mise en œuvre des filtres d'ordre élevé est indispensable. Dans ce cas, l'utilisation de cellules de deuxième ordre est une question cruciale. Nos contributions les plus importantes présentées dans cette thèse consistent en un nouveau principe de réglage presque indépendamment de la fréquence de résonance et son facteur de qualité mais aussi sont proposées deux architectures de l'inductance TOSI avec une réponse améliorée en fréquence. D'autres résultats sont en cours de validation expérimentale. Nos travaux ont donné lieu à 12 articles publiés dans des revues prestigieuses ou présentés lors de conférences et workshops internationaux. En plus de ces aspects innovateurs, nous présentons dans ce mémoire un large descriptif des architectures des émetteurs-récepteurs sans fil utilisés pratique et un état de l'art des technologies et performances d'inductances TOSI proposées en technologie CMOS. / The scope of this thesis is to propose solutions to improve the performances of the CMOS transistor only simulated inductors (TOSI) aiming RF filtering applications. We are interested in TOSI architectures because they prove better performances than the classical gm–C filters, being superior with respect to the number of transistors, power consumption, frequency capability and chip area. Furthermore, TOSI architectures have many potential applications in RF design. In the general context of the multi–standard trend followed by wireless transceivers, TOSI based RF filters may offer the possibility of implementing reconfigurable devices. However, satisfying the telecommunications requirements is not an easy task therefore high order TOSI based filters should be implemented. Consequently, using good second order TOSI cells is a matter of the utmost importance and we propose a novel quality factor tuning principle which offers an almost independent tuning of self resonant frequency and quality factor for simulated inductors. An improved TOSI architecture with increased frequency capability is also reported.

The continuing trend of miniaturization in semiconductor devices has enabled the integration of complex functionalities on-chip, leading to a proliferation of wireless devices for both mobile and in-office applications. The use of scaled CMOS technologies for high-frequency wireless devices is posing daunting technological challenges, both in the design and post-manufacture testing of such devices. The issue of device power consumption and heat dissipation is also dominating future wireless transceiver designs. This is driven by the trend of increasing operating speeds coupled with dense integration of multi-mode functionalities onto compact form-factors on-chip. In this thesis, a framework for reliable low-power operation of wireless devices is presented. The presented approaches significantly reduce device test costs during production, and operate the device at very low power consumption levels during field operation of the device. Low-cost test, diagnosis, and tuning techniques to reduce to reduce test cost of devices and operational reliability in field. To reduce device power consumption during field operation, adaptation is performed continuously while ensuring that system-level performance metrics are never violated. This approach has direct implications for boosting the battery life of portable wireless devices while ensuring their operational reliability.

We are investigating the use of ultrasound in Haptic applications. Initially abrief background of ultrasonic transducers and its characteristics were presented.Then a theoretical research was documented to understand the concepts that govern haptics. This section also discusses the algorithm adopted by various researches to implement haptics in the professional world. Then investigations were made to understand the behavior of ultrasonic transducers and conduct soft-ware simulations to obtain various results. At first simulations were conducted on Field II software. This simulations involved the creation of elements in trans-ducers, transducer’s spatial impulse responses, transducer’s impulse responsein time and frequency domain, effect of adding apodization to the transducers,pulse echo response of the transducers, beam profile variation along the focallength of the transducers. Then a Matlab based GUI was used to study the relationship between number of elements in transducers, the frequency of the input signal and duty cycle variation of the input wave. A concept of phase shift, which explains the time delay generation was also coded in Matlab.

abstract: As integrated technologies are scaling down, there is an increasing trend in the process,voltage and temperature (PVT) variations of highly integrated RF systems. Accounting for these variations during the design phase requires tremendous amount of time for prediction of RF performance and optimizing it accordingly. Thus, there is an increasing gap between the need to relax the RF performance requirements at the design phase for rapid development and the need to provide high performance and low cost RF circuits that function with PVT variations. No matter how care- fully designed, RF integrated circuits (ICs) manufactured with advanced technology nodes necessitate lengthy post-production calibration and test cycles with expensive RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast measurement of performance parameters during both post-production and in-eld op- eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip measurement of RF performance parameters. In this dissertation, three aspects of automated test and calibration, including DFT mathematical model, BIST hardware and built-in calibration are covered for RF front-end blocks. First, the theoretical foundation of a post-production test of RF integrated phased array antennas is proposed by developing the mathematical model to measure gain and phase mismatches between antenna elements without any electrical contact. The proposed technique is fast, cost-efficient and uses near-field measurement of radiated power from antennas hence, it requires single test setup, it has easy implementation and it is short in time which makes it viable for industrialized high volume integrated IC production test. Second, a BIST model intended for the characterization of I/Q offset, gain and phase mismatch of IQ transmitters without relying on external equipment is intro- duced. The proposed BIST method is based on on-chip amplitude measurement as in prior works however,here the variations in the BIST circuit do not affect the target parameter estimation accuracy since measurements are designed to be relative. The BIST circuit is implemented in 130nm technology and can be used for post-production and in-field calibration. Third, a programmable low noise amplifier (LNA) is proposed which is adaptable to different application scenarios depending on the specification requirements. Its performance is optimized with regards to required specifications e.g. distance, power consumption, BER, data rate, etc.The statistical modeling is used to capture the correlations among measured performance parameters and calibration modes for fast adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by embedding built-in tuning knobs in LNA design in 130nm technology. The tuning knobs are carefully designed to provide independent combinations of important per- formance parameters such as gain and linearity. Minimum number of switches are used to provide the desired tuning range without a need for an external analog input. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

With the emergence of the Internet of things (IoT) networks, the replacement of batteries for IoT devices became challenging. In particular, the battery replacement is more expensive and cumbersome for scenarios where there are many IoT devices; or where the IoT devices are in unreachable locations; or when they have to be replaced often. Some IoT devices might be lost or forgotten, and there is a risk of hazardous chemicals leakage and e-waste in large scale in nature. Radio frequency (RF) wireless power transfer (WPT) is an alternative technology for powering those devices. It has been shown that only less than one millionth of the transmitted energy is absorbed by the receivers, the rest is absorbed by the objects in the environment. We can utilize the existing infrastructure for wireless communications such as base stations (BS) to charge IoT devices. The present work is devoted to analyze the feasibility and limitations of the battery-less operation of IoT devices with RF WPT technology and energy harvesting from existing infrastructure for wireless communications. We study the indoor and outdoor scenarios for powering of IoT devices. In the first scenario, we consider an outdoor environment where an IoT device periodically harvests energy from an existing BS and transmits a data packet related to the sensor measurement under shadow fading channel conditions. We analyze the limits (e.g., coverage range) of energy harvesting from a BS for powering IoT devices. We characterize the "epsilon-coverage range, where" is the probability of the coverage. Our analysis shows a tradeoff between the coverage range and the rate of sensor measurements, where the maximal "epsilon-coverage range is achieved as the sensor measurement rate approaches zero. We demonstrate that the summation of the sleep power consumption and the harvesting sensitivity power of an IoT device limits the maximal "epsilon-coverage range. Beyond that range, the IoT device cannot harvest enough energy to operate. The desired rate of the sensor measurements also significantly impacts the "epsilon-coverage range. We also compare the operational domain in terms of the range and measurement rate for the WPT and battery-powered technologies. In the second scenario, we consider the remote powering of IoT devices inside an aircraft. Sensors currently deployed on board have wired connectivity, which increases weight and maintenance costs for aircraft. Removing cables for wireless communications of sensors on board alleviates the cost, however, the powering of sensors becomes a challenge inside aircraft. We assume that the IoT devices have fixed and known locations inside an aircraft. The design problem is to minimize the number of WPT transmitters given constraints based on the cabin geometry and duty cycle of the IoT devices. We formulate a robust optimization problem to address the WPT system design under channel uncertainties. We also derive an equivalent integer linear programming and solve that for an optimal deployment to satisfy the duty cycle requirements of the cabin sensors. / <p>QC 20220223</p><p></p>

A significant growth was witnessed in the field of Wireless Sensor Networks (WSNs), in the previous decade. The objective of this study has been Survey of micro controllers and short-range radio transceivers for wireless sensors and provide an extensive overview of micro controllers and RF-transceivers in the Market and compare the relevant properties for designing wireless sensor nodes. In the survey, RF-transvers from Nordic semiconductors is extensively presented for short-rang wireless protocols some of the protocols are RF-Communication Module, Bluetooth Low Energy Module, ZigBee module and Wi-Fi module.          In WSNs node design Power consumption is one the most important design issue, this thesis work present the different type of WSN protocols energy consumption efficiency and power consumption, compared and conclude graphically.        Microcontrollers are the main part of WSNs node for processing and gathering sensor data. There is different microcontroller’s products in the market however the WSN protocols presented in this thesis uses Cortex-M4 processor which is one of ARM product, the specification and comparison of this product with other products is presented.

No description available.

Ever since the FCC allocated 7.5 GHz (from 3.1 GHz to 10.6 GHz) for ultra wideband (UWB) technology, interest has been renewed in both academic and industrial circles to exploit this vast spectrum for short range, high data rate wireless applications. The great potential of UWB lies in the fact that it can co-exist with the already licensed spectrum users and can still pave the way for a wide range of applications. However, this wide bandwidth complicates the circuit level implementation of key RF blocks like the power amplifier (PA), transmit/receive switch, low noise amplifier (LNA) and mixers in an UWB transceiver. Though expensive technologies like SiGe or GaAs have been used for transceiver realizations, the ultimate goal is to have a single-chip, low-cost solution which can only be achieved by using CMOS technology. Nevertheless, some of the inherent limitations of CMOS like lower fT of transistors make the design of UWB circuits in CMOS an extremely challenging task. Two proposals- Multi-Band OFDM and Direct-Sequence CDMA have been put before the IEEE 802.15.3a task group to decide on the industry standard for the commercial deployment of this technology. Though the debate on which standard is better has not been resolved, proponents of both the groups have already begun to develop prototypes of their respective proposals. This thesis describes the design of a key RF block in the UWB transceiver - the Power Amplifier. For the first part of this work, a PA suitable for MB-OFDM specifications was designed and fabricated in TSMC 0.18um CMOS technology. The class-AB PA is able to cover the lower UWB frequency band from 3.1 GHz to 4.75 GHz and delivers an output power of -2 dBm at 4 GHz. Simulated results show a gain of 19±2 dB achieved over the entire band and the PA consumes 36.54 mW from a 1.8V supply. In the second part of this work, a PA that meets the DS-CDMA specifications was designed and fabricated. This PA operates in the class-AB regime, delivering an output power of -4.2 dBm with input-1dB compression point at -22 dBm. Complete design and implementation was done using TSMC 0.18um CMOS technology and it consumes a very low power of 25 mW, while realizing a flat gain of 19±1 dB across the whole band of operation. All the above mentioned results are from simulations in SpectreRF and measurements are yet to be taken. Additional features like power ON/OFF scheme and output impedance control has also been incorporated in the design. / Master of Science

The objective of the proposed research is to present a compact system-on-package (SOP)-based passive front-end solution for millimeter-wave wireless communication/sensor applications, that consists of fully integrated three dimensional (3D) cavity filters/duplexers and antenna. The presented concept is applied to the design, fabrication and testing of V-band transceiver front-end modules using multilayer low temperature co-fired (LTCC) technology. The millimeter-wave front-end module is the foundation of 60 GHz (V-band) wireless systems for short-range multimedia applications, such as high-speed internet access, video streaming and content download. Its integration poses stringent challenges in terms of high performance, large number of embedded passive components, low power consumption, low interference between integrated components and compactness. To overcome these major challenges, a high level of integration of embedded passive functions using low-cost and high-performance materials that can be laminated in 3D, such as the multilayer LTCC, is significantly critical in the module-level design. In this work, various compact and high-performance passive building blocks have been developed in both microstrip and cavity configurations and their integration, enabling a complete passives integration solution for 3D low-cost wireless millimeter-wave front-end modules. It is worthy to note that most of the designs implemented comes away with novel ideas and is presented as the first extensive state-of-art components, entirely validated by measured data at 60 GHz bands.