Este trabalho apresenta o projeto, a verificação funcional e a síntese dos módulos funcionais de um comutador Gigabit Ethernet. As funções destes módulos encontramse definidas nos padrões IEEE 802.1D, IEEE 802.1Q, IEEE 802.3 e nos seguintes RFCs (Request for Comments): RFC 2697, RFC 2698 e RFC 4115. Estes módulos formam o núcleo funcional do comutador e implementam as principais funções dele. Neste trabalho quatro módulos são desenvolvidos e validados. Estes módulos foram projetados para serem inseridos na plataforma NetFPGA, formando o chamado “User Data Path”. Esta plataforma foi desenvolvida pela universidade de Stanford para permitir a prototipagem rápida de hardware para redes. O primeiro módulo chamado de “Árbitro de entrada” decide qual das portas de entrada do comutador ele vai atender, para que os quadros que ingressam por essa porta sejam processados. Este módulo utiliza um algoritmo Deficit Round Robin (DRR). Este algoritmo corrige um problema encontrado no módulo original desenvolvido na plataforma NetFPGA. O segundo módulo é o “Pesquisador da porta de saída”. O bloco principal deste módulo é o motor de classificação. A função principal do motor de classificação e aprendizagem de endereços MAC é encaminhar os quadros à suas respectivas portas de saída. Para cumprir esta tarefa, ele armazena o endereço MAC de origem dos quadros em uma memória SRAM e é associado a uma das portas de entrada. Este motor de classificação utiliza um mecanismo de hashing que foi provado que é eficaz em termos de desempenho e custo de implementação. São apresentadas duas propostas para implementar o motor de classificação. Os resultados da segunda proposta permite pesquisar efetivamente 62,5 milhões de quadros por segundo, que é suficiente para trabalhar a uma taxa wire-speed em um comutador Gigabit de 42 portas. O maior desafio foi conseguir a taxa de wire-speed durante o processo de “aprendizagem” usando uma memória SRAM externa. O terceiro módulo é o marcador de quadros. Este módulo faz parte do mecanismo de qualidade de serviço (QoS). Com este módulo é possível definir uma taxa máxima de transferência para cada uma das portas do comutador. O quarto módulo (Output Queues) implementa as filas de saída do comutador. Este módulo faz parte de plataforma NetFPGA, mas alguns erros foram encontrados e corrigidos durante o processo de verificação. Os blocos foram projetados utilizando Verilog HDL e visando as suas implementações em ASIC, baseado em uma tecnologia de 180 nanômetros da TSMC com a metodologia Semi-Custom baseada em standard cells. Para a verificação funcional foi utilizada a linguagem SystemVerilog. Uma abordagem de estímulos aleatórios restritos é utilizada em um ambiente de testbench com capacidade de verificação automática. Os resultados da verificação funcional indicam que foi atingido um alto porcentual de cobertura de código e funcional. Estes indicadores avaliam a qualidade e a confiabilidade da verificação funcional. Os resultados da implementação em ASIC amostram que os quatro módulos desenvolvidos atingem a freqüência de operação (125 MHz) definida para o funcionamento completo do comutador. Os resultados de área e potência mostram que o módulo das Filas de saída possui a maior área e consumo de potência. Este módulo representa o 92% da área (115 K portas lógicas equivalentes) e o 70% da potência (542 mW) do “User Data Path”. / This work presents the design, functional verification and synthesis of the functional modules of a Gigabit Ethernet switch. The functions of these modules are defined in the IEEE 802.1D, IEEE 802.1Q, IEEE 802.3 standards and the following RFCs (Request for Comments): RFC 2697, RFC 2698 and RFC 4115. These modules are part of the functional core of the switch and implement the principal functions of it. In this work four modules are developed and validated. These modules were designed to be inserted in the NetFPGA platform, as part of the “User Data Path”. This platform was developed at Stanford University to enable the fast prototype of networking hardware. The first module called “input arbiter” decides which input port to serve next. This module uses an algorithm Deficit Round Robin (DRR). This algorithm corrects a problem found in the original module developed in the NetFPGA platform. The second module is the classification engine. The main function of the MAC address classification engine is to forward Ethernet frames to their corresponding output ports. To accomplish this task, it stores the source MAC address from frames in a SRAM memory and associates it to one of the input ports. This classification engine uses a hashing scheme that has been proven to be effective in terms of performance and implementation cost. It can search effectively 62.5 million frames per second, which is enough to work at wire-speed rate in a 42-port Gigabit switch. The main challenge was to achieve wire-speed rate during the “learning” process using external SRAM memory. The third module is the frame marker. This module is part of the quality of service mechanism (QoS). With this module is possible to define a maximum transmission rate for each port of the switch. The fourth module (Output Queues) implements the output queues of the switch. This module is part of the NetFPGA platform, but some errors were found and corrected during the verification process. These module were designed using Verilog HDL, targeting the NetFPGA prototype board and an ASIC based on a 180 nm process from TSMC with the Semi-custom methodology based on standard cells. For the functional verification stage is used the SystemVerilog language. A constrained-random stimulus approach is used in a layered-testbench environment with self-checking capability. The results from the functional verification indicate that it was reached a high percentage of functional and code coverage. These indicators evaluate the quality and reliability of the functional verification. The results from the ASIC implementation show that the four modules developed achieve the operation frequency (125 MHz) defined for the overall switch operation. The area and power results demonstrate that the Output Queues module has the largest area and power consumption. This module represents the 92% of area (115 K equivalent logic gates) and the 70% of power (542 mW) from the User Data Path.

Les travaux précédemment réalises au sein du LPICM ont mis en évidence que le silicium microcristallin est un semi-conducteur a faible cout, possédant une mobilité importante avec malgré tout une très bonne stabilité. Ce qui en fait un matériau particulièrement intéressant pour les transistors TFTs des écrans plats OLED 2. Il nous a donc paru logique de nous intéresser, dans le cadre de cette thèse, a la conception et a la réalisation expérimentalement des structures de pixel OLED à base de transistors TFTs en silicium microcristallin. Pour ce faire, il est indispensable de posséder des modèles comportementaux performants des composants. Ainsi, notre objectif primordial a été de concevoir des modèles Spice de transistors c-Si TFT mais aussi d'OLED. D'un point de vue technologique, nous nous sommes attaches à maitriser l'ensemble de la chaine de fabrication (conception de masques et lithographie en salle blanche). La caractérisation de nos transistors a révèle des mobilités de l'ordre de 1 cm2V−1s−1, des tensions de seuil de 4 V et a montre une bonne stabilité, sous stress, de la tension de seuil et de la mobilité. La faisabilité de ces transistors sur substrats flexibles comme le polyimide a aussi été démontre dans le cadre du Projet Intégré FlexiDis. Du point de vue de la modélisation, un modèle statique et dynamique Spice de transistor en silicium microcristallin est propose. L'écriture de ce modèle dans le langage Verilog-A nous permet de garantir une bonne portabilité et de pouvoir ainsi utiliser facilement des simulateurs professionnels comme Spectre de chez Cadence. De manière complémentaire, un modèle Spice efficient de diode OLED est également propose. Grace à ces outils, nous avons pu simuler des circuits utilisant les TFTs en silicium microcristallin. Ces simulations nous permettent de prédire que ces composants sont pertinents pour la conception de pixel OLED, de drivers de lignes, mais aussi de portes logiques NMOS simples comme l'inverseur et l'oscillateur en anneau.

<p>The aim of this thesis was to configure an FPGA with high speed ports to capture data from a prototype 4 bit ΣΔ analogue-to-digital converter sending data at a rate of 2.4 Gbps in four channels and to develop a protocol for transferring the data to a PC for analysis. Data arriving in the four channels should be sorted into 4 bit words with one bit taken successively from each of the channels. A requirement on the data transfer was that the data in the four channels should arrive synchronously to the FPGA. A Virtex-5 FPGA on a LT110X platform was used with <em>Rocket^TMIO</em> GPT transceivers tightly integrated with the FPGA logic. Since the actual DUT (Device Under Test) was not in place during the work, the transceivers of the FPGA were used for both sending and receiving data. The transmission was shown to be successful for both eight and ten bit data widths. At this stage a small skew between the data in the four channels was observed. This was solved by storing the information in separate memories, one for each of the channels, to make possible to later form the 4 bit words in the PC (MatLab). The memories were two port FIFOs writing in data at 240 MHz (10 bit data width) or 300 MHz (8 bit data width) and read out at 50 MHz.</p> / <p>Syftet med examensarbetet var att konfigurera en FPGA med höghastighetsportar så att data från en prototyp av en 4 bitars ΣΔ analog-till-digital omvandlare kan samlas in med en hastighet av 2.4 Gbps i var och en av fyra kanaler och att utveckla ett protokoll för överföring av dessa data från FPGAn till en PC för analys. Insamlade data ska sorteras i 4 bitars ord med en bit successivt tagen från var och en av kanalerna. Ett krav på dataöverföringen var att data i de fyra kanalerna skulle anlända synkront till FPGAn. En Virtex-5 FPGA på en LT110X plattfrom användes med <em></em>GTP transceivrar tätt integrerade med FPGA logiken. Då utrustningen som skulle testas inte var tillgänglig under tiden arbetet utfördes användes FPGAns transceivrar till att både sända och ta emot data. Överföring av data med både 8 och 10 bitars datavidd uppnåddes framgångsrikt. Data i de fyra kanalerna visade sig dock inte anlända synkront till mottagaren. Detta problem löstes genom att lagra informationen i separata minnen, ett för varje kanal, överföra data från minnena till PCn och där med hjälp av MatLab sortera dem till 4 bitars ord. Som minnen användes tvåportars FIFOn där data skrivs in med en hastighet av 240 MHz (10 bitars datavidd) eller 300 MHZ (8 bitars datavidd) och läses ut med en hastighet av 50 MHz.</p>

The aim of this thesis was to configure an FPGA with high speed ports to capture data from a prototype 4 bit ΣΔ analogue-to-digital converter sending data at a rate of 2.4 Gbps in four channels and to develop a protocol for transferring the data to a PC for analysis. Data arriving in the four channels should be sorted into 4 bit words with one bit taken successively from each of the channels. A requirement on the data transfer was that the data in the four channels should arrive synchronously to the FPGA. A Virtex-5 FPGA on a LT110X platform was used with RocketTMIO GPT transceivers tightly integrated with the FPGA logic. Since the actual DUT (Device Under Test) was not in place during the work, the transceivers of the FPGA were used for both sending and receiving data. The transmission was shown to be successful for both eight and ten bit data widths. At this stage a small skew between the data in the four channels was observed. This was solved by storing the information in separate memories, one for each of the channels, to make possible to later form the 4 bit words in the PC (MatLab). The memories were two port FIFOs writing in data at 240 MHz (10 bit data width) or 300 MHz (8 bit data width) and read out at 50 MHz. / Syftet med examensarbetet var att konfigurera en FPGA med höghastighetsportar så att data från en prototyp av en 4 bitars ΣΔ analog-till-digital omvandlare kan samlas in med en hastighet av 2.4 Gbps i var och en av fyra kanaler och att utveckla ett protokoll för överföring av dessa data från FPGAn till en PC för analys. Insamlade data ska sorteras i 4 bitars ord med en bit successivt tagen från var och en av kanalerna. Ett krav på dataöverföringen var att data i de fyra kanalerna skulle anlända synkront till FPGAn. En Virtex-5 FPGA på en LT110X plattfrom användes med GTP transceivrar tätt integrerade med FPGA logiken. Då utrustningen som skulle testas inte var tillgänglig under tiden arbetet utfördes användes FPGAns transceivrar till att både sända och ta emot data. Överföring av data med både 8 och 10 bitars datavidd uppnåddes framgångsrikt. Data i de fyra kanalerna visade sig dock inte anlända synkront till mottagaren. Detta problem löstes genom att lagra informationen i separata minnen, ett för varje kanal, överföra data från minnena till PCn och där med hjälp av MatLab sortera dem till 4 bitars ord. Som minnen användes tvåportars FIFOn där data skrivs in med en hastighet av 240 MHz (10 bitars datavidd) eller 300 MHZ (8 bitars datavidd) och läses ut med en hastighet av 50 MHz.

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Many new fabrication technologies, from nanotechnology and MEMS to printed organic semiconductors, center on constructing arrays of large numbers of sensors, actuators, or other devices on a single substrate. The utility of such an array could be greatly enhanced if each device could be managed by a programmable controller and all of these controllers could coordinate their actions as a massively-parallel computer. Kentucky Architecture nanocontroller array with very low per controller circuit complexity can provide efficient control of nanotechnology devices. This thesis provides a detailed description of the control hierarchy of a digital system needed to build "nanocontrollers" suitable for controlling millions of devices on a single chip. A Verilog design and FPGA prototype of a nanocontroller system is provided to meet the constraints associated with a massively-parallel programmable controller system.

Digital halftoning is a crucial technique used in digital printers to convert a continuoustone image into a pattern of black and white dots. Halftoning is used since printers have a limited availability of inks and cannot reproduce all the color intensities in a continuous image. Error Diffusion is an algorithm in halftoning that iteratively quantizes pixels in a neighborhood dependent fashion. This thesis focuses on the development and design of a parallel scalable hardware architecture for high performance implementation of a high quality Stacked Error Diffusion algorithm. The algorithm is described in ‘C’ and requires a significant processing time when implemented on a conventional CPU. Thus, a new hardware processor architecture is developed to implement the algorithm and is implemented to and tested on a Xilinx Virtex 5 FPGA chip. There is an extraordinary decrease in the run time of the algorithm when run on the newly proposed parallel architecture implemented to FPGA technology compared to execution on a single CPU. The new parallel architecture is described using the Verilog Hardware Description Language. Post-synthesis and post-implementation, performance based Hardware Description Language (HDL), simulation validation of the new parallel architecture is achieved via use of the ModelSim CAD simulation tool.

In this thesis a microcontroller core is developed in an FPGA. Its instruction set is compatible with the microcontroller PIC16XX series by Microchip Technology. The microcontroller employs a RISC architecture with separate busses for instructions and data. Our goal in this research is to implement and evaluate the design in the FPGA. Increasing performance and gate capacity of recent FPGA devices permits complex logic systems to be implemented on a single programmable device. Such a growing complexity demands design approaches, which can lead to designs containing millions of logic gates, memories, high-speed interfaces, and other high-performance components. In recent years, the continuous development in the area of highly integrated circuits has lead to a change in the design methods used, making it possible to economically utilize FPGAs in many designs. A test demo board from the Digilent Inc is used to fit our testing requirements of the RISC microcontroller. The test demo board also had the capability of communicating with a personal computer (PC) so that we can load the program from PC. Based on the modern design methods the microcontroller core is developed using the Verilog hardware description language. Xilinx ISE Foundation 6.3i software is used for its synthesis and implementation. An embedded test program code using MPLAB is also developed, and then loaded into the designed microcontroller residing in the FPGA. In order to perform a functional test of the microcontroller core a special test program downloader application is designed by using Borland C++ Builder. First, the specification from the PIC16XX datasheet is transferred into an abstract behavioral description. Based on that, the next step is to develop a description of the microcontroller core with some minor modifications which can be synthesizable into a FPGA. Finally, the resulting gate level netlist is evaluated and tested using a demo board.

Thesis(M.S.)--Auburn University, 2006. / Abstract. Vita. Includes bibliographic references.

Thesis (M.S.)--University of Texas at El Paso, 2008. / Title from title screen. Vita. CD-ROM. Includes bibliographical references. Also available online.