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With the rapid growth of Internet-of-Things (IoT), billions of devices are expected to be interconnected to provide various services appealing to users. Many devices will get an access to valuable information which is likely to increase the number of malicious attacks on these devices in the future. Therefore, security is considered as one of the most critical challenges in the development of IoT. In order to secure resource-constrained devices such as sensors or radio frequency identification (RFID) tags which form the backbone of IoT, lightweight cryptographic algorithms are required. This thesis focuses on the problem of message authentication. To authenticate a message means to verify that the message: (1) comes from the right sender (i.e. its authenticity), and (2) has not been modified (i.e. its integrity). It is challenging to use traditional message authentication methods in resource-constrained devices because typically they can allocate only a few hundred gates for implementing security due to their limited computing, storage and energy resources. To address these needs, a new message authentication algorithm based on a Cryptographic Cyclic Redundancy Check (C-CRC) was developed by KTH in collaboration with Ericsson. In this thesis, we implemented C-CRC and compared it with KECCAK Message Authentication Code (KMAC) standardized by the National Institute of Standards and Technology (NIST) in 2016. First, MATLAB and Verilog versions were developed for both algorithms. The comparison of these two versions allowed us to verify the correctness of algorithms functionality. After that, the Verilog descriptions were simulated in ModelSim and synthesized using Synopsys design compiler. Finally, placement and routing was performed using Cadence SoC Encounter. The evaluation results show that C-CRC outperforms KMAC in terms of area, power, throughput per area, and energy per bit. However, C-CRC is worse than KMAC in terms of latency. We have also investigated several different options of implementing C-CRC, including producing more than one bit of output per clock cycle. We found that such a technique improves throughput of C-CRC with the minimal penalty in area and power consumption

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This thesis focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers, which were introduced by Wang and Leduc. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. / This thesis focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers, which were introduced by Wang and Leduc. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. We first introduce the sampled-data setting from Wang, and then define the sampled-data properties he identified, including the SD controllability property. We then introduce Wang's formal representation of an SD controller as a Moore synchronous finite state machine (FSM). We then discuss Wang's modular and centralized translation method. We next introduced new modular results for the SD controllability point 3.1, SD controllability point 3.2, SD controllability point 4, activity loop free and S-singular prohibitable behaviour that allow one to verify the properties using only a portion of the system, instead of having to construct the entire system model. This should allow faster verification times as well as allow larger systems to be verified. We then introduce for the first time algorithms to verify Wang's CS Deterministic and non self-loop ALF properties. The remainder of the thesis focuses on developing algorithms and software to automatically convert a TDES first into an FSM, and then into a VERILOG module. VERILOG is a hardware description language which allows our FSM to be compiled and implemented on digital logic devices such as an FPGA. We then tested our method by modelling a simple door locking system as TDES, checking that the system satisfies the required sampled-data properties, and then translating the result into VERILOG. The above algorithms and methods have all been implemented as a part of the graphical DES research tool, DESpot. / Thesis / Master of Computer Science (MCS)

Field programmable gate arrays (FPGAs) have been emerging as a promising bedrock to provide opportunities for several types of accelerators that spans across various domains such as finance, web-search, and data center networking, among others. Research interests facilitating the development of accelerators on FPGAs are increasing significantly, in particular, because of their effectiveness with a variety of applications, flexibility, and high performance per watt. However, several key challenges remain that hinder their large-scale deployment. Overcoming these challenges would enable them to match the pervasiveness of graphics processor units (GPUs), their principal competitors in this arena. One of the primary reasons responsible for the slow adaptation by programmers has been the programming model, which uses a low-level hardware description language (HDL). Using HDLs require a detailed understanding of logic design and significant effort to implement and verify the behavioral models, with the latter growing with its complexity. Recent advancements in high-level language synthesis (HLS) tools have addressed this challenge to a considerable extent by allowing the programmers to write their applications in a high-level language named OpenCL. These applications are then compiled and synthesized to create a bitstream that configures the FPGA. This thesis characterizes the efficacy of HLS compiler optimizations that can be employed to improve the performance of these applications. The synthesized hardware from OpenCL kernels is fundamentally different from traditional hardware such as CPUs and GPUs, which exploit instruction level parallelism (ILP) thread level parallelism (TLP), or data level parallelism (DLP) for performance gains. FPGAs typically use deep pipelining (i.e., ILP) for performance. A stall in this pipeline may severely undermine the performance of applications. Thus, it is imperative to identify and remove any such bottlenecks. To this end, this thesis presents and discusses a software-centric framework to debug and profile the synthesized designs generated using HLS tools. This thesis proposes basic code patterns, including a timestamp and a scalable framework, which can be plugged easily into OpenCL kernels, to collect and process run-time information dynamically. This scalable framework has a small overhead for area utilization and frequency but provides fine-grained information about the bottlenecks and latencies in design. Additionally, although HLS tools have improved programmability, this may come at the cost of performance or area utilization. This thesis addresses this design trade-off via a comparative study of a hand-coded design in HDL and an architecturally similar, tool-generated design using an OpenCL compiler in the application area of 3D-stencil (i.e., structured grid) computation. Experiments in this thesis show that the performance of an OpenCL approach can achieve 95% of the peak attainable performance of a microkernel for multiple problem sizes. In comparison to the OpenCL approach, an HDL approach results in approximately 50% less memory usage and only 2% better performance on average. / MS / A hardware chip consists of switches or transistors, and a modern chip can have a few billions of them. Specifying the interconnection among these transistors and their placement on a chip is a complex problem. To simplify this, the chip-design flow uses automated tools and abstraction at the different levels of the flow, such as architecture, design, synthesis, placement, among others. During design, an engineer specifies the behavioral model in a hardware description language (HDL), which is later used by the automated tools for further processing. Using the HDL requires a detailed understanding of logic design and significant effort to implement and verify the behavioral models, with the latter growing with its complexity. Recent advancements in high-level language synthesis tools have addressed this challenge to a considerable extent by allowing the programmers to write their applications in a high-level language. This thesis characterizes the efficacy of such a tool and available optimizations that can be employed to improve the performance of these applications. Additionally, this thesis presents and discusses a framework to debug and profile the designs generated using high-level synthesis tools, which can be plugged easily into an application, to collect and process run-time information dynamically. This scalable framework has a small overhead but provides fine-grained information about the bottlenecks in the design. Furthermore, the experiments in this work show that a design generated from a high-level synthesis tool has similar performance when compared to a manual design in HDL, at the expense of area utilization.

Une des principales solutions technologiques liées à la réduction d’échelle de la technologie CMOS est aujourd’hui clairement orientée vers les transistors MOSFET faiblement dopés à multiples grilles. Ceux-ci proposent une meilleure immunité contre les effets canaux courts comparés aux transistors MOSFET bulk planaires (cf. ITRS 2011). Parmi les MOSFETs à multiples grilles, le transistor FinFET SOI est un candidat intéressant de par la similarité de son processus de fabrication avec la technologie des transistors planaires. En parallèle, il existe une réelle attente de la part des concepteurs et des fonderies à disposer de modèles compacts efficaces numériquement, précis et proches de la physique, insérés dans les « design tools » permettant alors d’étudier et d’élaborer des circuits ambitieux en technologie FinFET. Cette thèse porte sur l’élaboration d’un modèle compact orienté conception du transistor FinFET valide aux dimensions nanométriques. Ce modèle prend en compte les effets canaux courts, la modulation de longueur de canal, la dégradation de la mobilité, leseffets de mécanique quantique et les transcapacités. Une validation de ce modèle est réalisée par des comparaisons avec des simulations TCAD 3D. Le modèle compact est implémenté en langage Verilog-A afin de simuler des circuits innovants à base de transistors FinFET. Une modélisation niveau-porte est développée pour la simulation de circuits numériques complexes. Cette thèse présente également un modèle compact générique de transistors MOSFET SOI canaux long faiblement dopés à multiple grilles. La dépendance à la température est prise en compte. Selon un concept de transformation géométrique, notre modèle compact du transistor MOSFET double grille planaire est étendu pour s’appliquer à tout autre type de transistor MOSFET à multiple grille (MuGFET). Une validation expérimentale du modèle MuGFET sur un transistor triple grille est proposée. Cette thèse apporte enfin des solutions pour la modélisation des transistors MOSFET double grille sans jonction. / One of the main technological solutions related to downscaling of CMOS technology is now clearly oriented to lightly doped multigate MOSFETs. They offer better immunity against short channel effects compared to planar bulk MOSFETs (see ITRS 2011). Among the multigate MOSFETs, the SOI FinFET transistor is an interesting candidate because of the similarity of its manufacturing process with the planar transistor technology. In parallel, there is a real expectation on the part of designers and foundries to have compact models numerically efficient, accurate and close to the physics, and then inserted in to the design tools in order to study and develop ambitious circuits in FinFET technology. This thesis focuses on the development of a design-oriented compact model of FinFET transistor valid to nanoscale dimensions. This model takes into account the short channel effects, the channel length modulation, the mobility degradation, the quantum mechanic effects and the transcapacitances. A validation of this model is carried out by comparisons with 3DTCAD simulations. The compact model is implemented in Verilog-A to simulate innovative FinFET-based circuits. A gate-level modeling is developed for the simulation of complex digital circuits. This thesis also presents a generic compact modeling of multigate SOI MOSFETs with lightly doped channels and temperature dependent. According to a concept of geometric transformation, our compact model of the planar double-gate MOSFET is extended to be applied to any other type of multigate MOSFETs (MuGFET). An experimental validation of the MuGFET compact model with a triple gate transistor is proposed. This thesis finally brings solutions for the modeling of junction less double-gate MOSFET.

Cette thèse porte sur le thème général de la fiabilité des circuits microélectroniques. Le but de notre travail fut de développer un outil de simulation multi-physiques pour la conception des circuits intégrés fiables qui possède les caractéristiques innovatrices suivantes : • (i) L’intégration dans un environnement de conception microélectronique standard, tel que l’environnement Cadence® ; • (ii) La possibilité de simulation, sur de longues durées, du comportement des circuits CMOS analogiques en tenant compte du phénomène de vieillissement ; • (iii) La simulation de plusieurs physiques (électrique-thermique-mécanique) couplées dans ce même environnement de CAO en utilisant la méthode de simulation directe. Ce travail de thèse a été réalisé en passant par trois grandes étapes traduites par les trois parties de ce manuscrit. / This thesis was carried out under the theme of the microelectronics Integrated Circuits Reliability. The aim of our work was to develop a multi-physics simulation tool for the design of reliable integrated circuits. This tool has the following innovative features : • (i) The integration in a standard microelectronics design environment, such as the Cadence® environment ;• (ii) The possibility of efficient simulation, over long periods, of analog CMOS circuits taking into account the aging henomenon ; • (iii) The simulation of multiple physical behaviours of ICs (electrical-thermalmechanical) coupled in the same environment using the direct simulation method. This work was carried out through three main stages detailed in the three parts of this Manuscript.

Spintronics is an attractive field that combines magnetism and electronics to realize new devices. Spin based oscillators (SBOs) have gained significant interest in recent years due to their attractive characteristics, including high operating frequency, low power, small area and integration compatibility with CMOS circuitry. SBOs have shown potential in the fields of wireless communication systems, magnetic field sensing and neuromorphic computing. A relatively new and promising SBO architecture is the three-terminal Spin Hall Nano Oscillator (SHNO). To accelerate the design of next generation spintronic devices, co-design and simulation of three-terminal SHNOs with CMOS technology are of great importance. To realize this, a comprehensive analytical model is needed. In this thesis, an extensive survey of SBO theory is performed and a set of compact equations are proposed to describe the SBO characteristics. From these equations a compact model is realized in Verilog-A and verified against experimental measurements. The model shows good agreement with experimental results and opens up the possibility of designing CMOS circuits for three-terminal SHNOs. / Spintronics kombinerar magnetism och elektronik med syftet att utveckla nya komponenter. Spin baserade oscillatorer (SBO) har fått ökad intresse de senaste åren på grund av deras attraktiva egenskaper, inklusive hög frekvens, låg kraft, liten yta och integrations kompatibilitet med CMOS-kretsar. SBO har visat potential i kommunikationssystem, avkänning av magnetfält och neuromorfisk databehandling. En ny och förhoppningsfull SBO-arkitektur är den tre-terminala Spin Hall Nano Oscillator (SHNO). För att påskynda design av nästa generations spintronic-komponenter är co-design och simulering av tre-terminala SHNOs med CMOS-teknik av en stor betydelse. En modell krävs för att göra detta. I denna avhandling utförs en omfattande undersökning av SBO teori samt ekvationer för beskrivning av SBO egenskaper är föreslagen. Från dessa ekvationer är en kompakt modell i Verilog-A utvecklad och verifieras mot experimentella mätningar. Modellen visar god överensstämmelse med experimentella resultat och öppnar möjligheten att designa CMOS-kretsar för tre-terminal SHNOs.

Several technologies are being made available for the blind and the visually impaired with the use of infrared and sonar sensors, Radio Frequency Identification, GPS, Wi-Fi among others. Current technologies utilizing microprocessors increase the device's power consumption. In this project, a Verilog Hardware Language (VHDL) designed handheld device that autonomously guides a visually impaired user through an obstacle free path is proposed. The goal is to minimize power consumption by not using the usual microcontroller and replacing it with components that can increase its speed. Utilizing six infrared sensors, the handheld device is modeled after current technologies which use IR and sonar sensors which are reviewed in this project. By using behavioral modeling, an algorithm for obstacle avoidance and the generation of the obstacle free path is reduced using a K-map and implemented using a multiplexer. / by Ernesto Cividanes. / Thesis (M.S.C.S.)--Florida Atlantic University, 2010. / Includes bibliography. / Electronic reproduction. Boca Raton, Fla., 2010. Mode of access: World Wide Web.

This diploma thesis focuses on the design and implementation of an emulator of RFID protocols in a software defined radio. The designed emulator operates in the UHF band (860 MHz – 960 MHz). The main goal of this design is a very fast measurement of power characteristic of tag. The proposed solution is based on implementing the transmitter controls directly into the SDR. Thanks to this solution a reduction of delay between measurements occur compared to the conventional concept, when the transmitter parameters are controlled by the hosted PC. In this thesis, suitable platform based on research is chosen for implementation and also a concept of design is proposed and described herein, which is based on implementation of time critical algorithms directlyinto the software defined radio’s FPGA. The proposed solution was implemented into selected platforms and its functionality was experimentally verified.