Experimental research on high-power converters, particularly in an academic environment, faces severe infrastructural constraints. Usually, power source and loads of required ratings are not available. Further, more importantly, the energy consumption is huge. One possibility is to establish an experimental research platform, comprising of a network of high-power converters, through which power is circulated and which draws only the losses from the mains. This work deals with the establishment of a circulating power test set-up, comprising of two line-side PWM converters, inclusive of control and modulation methods for the two converters. Two types of circulating power test setups are developed. In the first setup, the converters are connected in parallel, on ac as well as dc sides, such that real and/or reactive power is circulated between them. In the second test setup, the dc buses of the converters are separated; hence, only reactive power circulation is possible. These setups are used to conduct heat-run tests with low energy expenditure on the PWM converters at various operating conditions up to power levels of 150 kVA. Further, these are used to validate analytically-evaluated thermal characteristics of high-power PWM converters. A safe thermal limit is derived for such converters in terms of apparent power (kVA) handled, power factor and switching frequency. The effects of voltage sag and of unequal current sharing between parallel IGBT modules on the safe thermal limit are studied. While the power drawn by the circulating-power setup from the grid is much lower than the ratings of the individual converters, the harmonic injection into the mains by the setup could be significant since the harmonics drawn by both converters tend to add up. This thesis investigates carrier interleaving to improve the waveform quality of grid current, drawn by the circulating-power test setup. The study of carrier interleaving is quite general and covers various applications of parallel-connected converters such as unity power factor rectification, static reactive power compensation and grid-connected renewable energy systems. In literature, carrier interleaving has been employed mainly for unity power factor rectifiers, sharing a common dc load equally. In such case, the fundamental components of the terminal voltages of the parallel converters are equal. However, when the power sharing between the two converters is unequal, or when power is circulated between the two converters, the terminal voltages of the two converters are not equal. A method to estimate rms grid current ripple, drawn by parallel-connected converters with equal and/or unequal terminal voltages, in a synchronous reference frame is presented. Further, the influence of carrier interleaving on the rms grid current ripple is studied. The optimum interleaving angle, which minimizes the rms grid current ripple under various applications, is investigated. This angle is found to be a function of modulation index of the converters in the equal terminal voltages case. In the unequal terminal voltages case, the optimum interleaving angle is shown to be a function of the average modulation index of the two parallel converters. The effect of carrier interleaving is experimentally studied on the reactive power circulation setup at different values of kVA and different dc bus voltages. The grid current ripple is measured for different values of interleaving angle. It is found experimentally that the optimum interleaving angle reduces the rms grid current ripple by between 37% and 48%, as compared without interleaving, at various operating conditions. Further, the reactive power circulation test set-up is used to evaluate and compare power conversion losses corresponding to different PWM techniques such as conventional space-vector PWM (CSVPWM), bus-clamping PWM (BCPWM) and advanced bus-clamping PWM methods for static reactive power compensator (STATCOM) application at high power levels. It is demonstrated theoretically as well as experimentally that an advanced bus-clamping PWM method, termed minimum switching loss PWM (MSLPWM), leads to significantly lower power conversion loss than CSVPWM and BCPWM techniques at a given average switching frequency.

MULTILEVEL inverters are the preferred choice of converters for electronic power conversion for high power applications. They are gaining popularity in variety of industrial applications including electric motor drives, transportation, energy management, transmission and distribution of power. A large portion of energy conversion systems comprises of multilevel inverter fed induction motor drives. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low. In conventional two level inverters, to get nearly sinusoidal phase current waveform, the switching frequency of the inverter is increased and the harmonics in the currents are pushed higher in the frequency spectrum to reduce the size and cost of the filters. But higher switching frequency has its own drawbacks – in particular for medium voltage, high power applications. They cause large dv_/ dt stresses on the motor terminals and the switching devices, leading to increased electromagnetic interference (EMI) problems and higher switching losses. Harmonics in the motor currents can further be minimized by adopting dodecagonal voltage space vector (SV) switching (12-sided polygon). In case of dodecagonal SV switching, the fifth and seventh order (6n , 1, n = odd) harmonics are completely eliminated for the full modulation range including over modulation and twelve step operation in the motor phase voltages and currents. In addition to low order harmonic current suppression, the linear modulation range for dodecagonal SV switching is also more by 6% when compared to that of the conventional hexagonal SV switching. The dodecagonal voltage SV structure is made possible by connecting two inverters with DC-link voltages Vd and 0:366Vd on either side of an open-end winding induction motor. The dodecagonal space vector switching can be used to produce better quality phase voltage and current waveforms and overcome the problem of low order fifth and seventh harmonic currents and to improve the range for linear modulation while reducing the switching frequency of the inverters when compared to that of the conventional hexagonal space vector based inverters. This thesis focuses on three aspects of multilevel dodecagonal space vector structures (i) Two new power circuit topologies that generate a multilevel dodecagonal voltage space vector structure with symmetric triangles, (ii) A multilevel dodecagonal SV structure with nineteen concentric dodecagons, (iii) Pulse width modulation (PWM) timing calculation methods for a general N-level dodecagonal SV structure. (i) Two new power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles with minimum number of DC link power supplies and floating capacitor H-bridges are proposed. The first power topology is composed of two hybrid cascaded five level inverters connected to either side of an open end winding induction machine. Each inverter consists of a three level neutral point clamped (NPC) inverter, cascaded with an isolated capacitor fed H-bridge making it a five level inverter. The second topology is a hybrid topology for a normal induction motor (star or delta connected), where the power is fed to the motor only from one side. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of the dodecagonal voltage space vector structure. Both topologies have inherent capacitor balancing for floating H-bridges for all modulation indices including transient operations. The proposed topologies do not require any pre-charging circuitry for startup. PWM timing calculation method for space vector modulation is also explored in this chapter. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any iterative searching, off-line computation, look-up tables or angle estimation. Experimental results for steady state operation and transient operation are also presented to validate the proposed concept. (ii) A multilevel dodecagonal voltage space vector structure with nineteen concentric do-decagons is proposed for the first time. This space vector structure is achieved by connecting two sets of asymmetric hybrid five level inverters on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of DC-link voltages and switching states of the inverters. In addition to that, a generic and simple method for calculation of PWM timings using only sampled reference values (v and v ) is proposed. This enables the scheme to be used for any closed loop application like vector control. Also, a new switching technique is proposed which ensures minimum switching while eliminating the fifth and seventh order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady state operation, transient operation including start-up have been presented and the results of Fast Fourier Transform (FFT) analysis is also presented for validating the proposed concept. (iii) A method to obtain PWM timings for a general N-level dodecagonal voltage space vector structure using only sampled reference values is proposed. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle, to get the timings T1 and T2 using trigonometric calculations. This method requires look-up tables and is difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle. The proposed method is generic and can be extended to any number of levels with symmetric structures and does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. The algorithm outputs the triangle number and the PWM timing values of T0, T1 and T2 which can be set as the compare values for any carrier based PWM module to obtain space vector PWM like switching sequences. Simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method. A 3.7 kW, 415 V, 50 Hz, 4-pole open-end winding induction motor was used for the experimental studies. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V insulated-gate bipolar transistor (IGBT) half-bridge modules (SKM75GB12T4). Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz was used. For modulation frequencies 10 Hz and below, a constant sampling frequency of 1 kHz was used as the frequency modulation ratio is high. For modulation frequencies above 10 Hz, synchronous PWM strategy was used. The time duration Ts is the sampling interval for which the timings T1 , T2 and T0 are calculated. As in the case of any synchronous PWM method, the duration of sampling time (Ts) is a function of the fundamental frequency of the modulating signal. In this case, Ts = 1_.fm • 12n) sec. where fm is fundamental frequency in Hertz and ‘n’ is the number of samples per 30ý dodecagonal sector. The PWM timings and the triangle data (from the DSP) is fed to field programmable gate array (FPGA) (SPARTAN XC3S200) clocked at 50 MHz where the actual gating pulses are generated. The capacitor balancing algorithm and the dead-time modules were implemented within FPGA. No external hardware was used for generation of dead-time. The dead-time block generates a constant dead-time of 2 s for all the switches. Extensive testing was done for steady state operations and transient operations including quick acceleration and start-up to validate the proposed concepts. With the advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range, suppression of eleventh and thirteenth harmonics in phase voltages and currents, reduced device voltage ratings, lesser dv_dt stresses on devices and motor phase windings, lower switching frequency, inherent cascaded H-bridge (CHB) capacitor balancing, the proposed space vector structures, the inverter power circuit topologies, the switching techniques and the PWM timing calculation methods can be considered as viable schemes for medium voltage, high power motor drive applications.

Three-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis. The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter. Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments. The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method. A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.