The necessity to incorporate renewable energy systems into existing electric power grid and need of efficient utilization of electrical energy are growing every day. A shunt connected Voltage Source Inverter(VSI) capable of bidirectional power flow and fast control has become one of the building block to address such requirements. However with growing number of grid connected VSI, new requirements related to harmonic injection, higher overall efficiency and better performances during short term grid disturbances have emerged as challenges. For this purpose a grid connected three phase four wire VSI with LCL filter can be considered as a general module to study different control approaches and system behavior under ideal and non-ideal grid conditions. This work focuses on achieving enhanced performance by analyzing effect of non-ideal conditions on system level and relating it to individual control blocks. In this work a phase locked loop structure has been proposed which is capable of extracting positive sequence fundamental phase information under non-ideal grid conditions. It can also be used in a single phase system without any structural modification. The current control for the three phase four wire VSI system has been implemented using Proportional Resonant (PR) controller in a per phase basis in stationary reference frame. A simplified controller design procedure based on asymptotic representation of the system transfer function is proposed. Using this method expressions for controller gains can be derived. A common mode model of the inverter system has been derived for low frequencies. Using this model a controller is designed to mitigate DC bus imbalance caused by sensor and ADC channel offsets. A multi-rate approach for digital implementation of PR controller with low resource consumption, that is suitable for an FPGA like digital controller ,is proposed. This multi-rate method can maintain resonance frequency accuracy even at low sampling frequency and can easily be frequency adaptive. Anti-wind up methods for PI controller have been studied to find suitable anti-wind up methods for PR controller. The tracking anti-wind up method is shown to be suitable for use with a PR controller. The effectiveness of this method under sudden disconnection and reconnection of VSI from grid is experimentally verified. A resonant integrator based second order filter is shown to be useful for active damping of LCL filter resonance with a wide range of grid inductance variation. The proposed method utilizes the LCL filter capacitor voltage to estimate resonance frequency current. Suitability of fundamental current PR controller for active damping alone, and with the proposed method show the superiority of the proposed method especially for low switching frequencies. Design oriented analysis of the above topics are included in the thesis. The theoretical understandings developed have been verified through experiments in the laboratory and can be readily implemented in industrial power electronic systems.

Η διπλωματική εργασία που ακολουθεί περιγράφει την διαδικασία που εφαρμόσθηκε ώστε να κατασταθεί δυνατή η τροφοδοσία ενός RL φορτίου με τάση σταθερή σε μέτρο και σε συχνότητα, από μια συστοιχία κυττάρων καυσίμου. Η πειραματική διάταξη, που κατασκευάσθηκε ώστε να πραγματοποιηθεί αυτός ο στόχος, εκτός από την πηγή (κύτταρο καυσίμου) και το φορτίο αποτελείται και από έναν ΣΡ/ΣΡ (dc/dc) μετατροπέα ανύψωσης τάσης, έναν αντιστροφέα πηγής τάσης, έναν τριφασικό μετασχηματιστή, ένα φίλτρο LC, μια συσκευή επιλογής φορτίου και τέλος την ψηφιακή κάρτα με την οποία εκτελούνται οι απαραίτητοι έλεγχοι. Όταν αναφερόμαστε σε τεχνικές ελέγχου εννοούμε αρχικά τόσο την παραγωγή παλμών με την τεχνική της ημιτονοειδούς διαμόρφωσης εύρους παλμών (Sinusoidal Pulse Width Modulation-SPWM) για την τροφοδότηση του αντιστροφέα πηγής τάσης όσο και παλμών με την τεχνική της διαμόρφωσης εύρους παλμών (Pulse Width Modulation – PWM) για τον έλεγχο του ΣΡ/ΣΡ (dc/dc) μετατροπέα ανύψωσης τάσης. Οι παλμοί αυτοί παράγονται μέσω προγράμματος που αναπτύχθηκε στην πλατφόρμα του Labview. Σε δεύτερο επίπεδο εφαρμόζεται με την βοήθεια της ψηφιακής κάρτας και του μοντέλου ο ασαφής έλεγχος που έχει ως σκοπό την σταθεροποίηση της τάσης στο φορτίο. Για να διαπιστώσουμε ότι έχουμε εξασφαλίσει απρόσκοπτη τροφοδοσία του τριφασικού φορτίου από την ενέργεια του κυττάρου καυσίμου με μια τάση με μειωμένο αρμονικό περιεχόμενο και σταθερό πλάτος και συχνότητα, πραγματοποιήσαμε βηματική αλλαγή της τιμής του φορτίου και αλλαγή της τάσης εξόδου του κυττάρου καυσίμου ώστε να διαπιστώσουμε αν όντως ο ασαφής έλεγχος αναλαμβάνει να επαναφέρει τις επιθυμητές τιμές της τάσης στο φορτίο. Η διπλωματική εργασία διαρθρώνεται με τον εξής τρόπο: Στο κεφάλαιο 1 επιχειρούμε μια σύντομη περιγραφή των ανανεώσιμων πηγών ενέργειας που κυριαρχούν στον Ελλαδικό χώρο (ηλιακή, αιολική, υδροηλεκτρική, γεωθερμική και ενέργεια από βιομάζα) ενώ αναφερόμαστε εκτενώς στην τεχνολογία των κυττάρων καυσίμου. Στο κεφάλαιο 2 γίνεται εκτενής περιγραφή των συσκευών που αποτελούν το κύκλωμα ισχύος της πειραματικής διάταξης. Το κύκλωμα ισχύος αποτελείται αρχικά από το κύτταρο καυσίμου που αποτελεί την πηγή ενέργειας, τον ΣΡ/ΣΡ (dc/dc) μετατροπέα ανύψωσης τάσης και τον αντιστροφέα πηγής τάσης. Σε δεύτερο επίπεδο υπάρχει το LC φίλτρο προς περιορισμό των αρμονικών και ο τριφασικός μετασχηματιστής που ανυψώνει το επίπεδο τάσης στο επιθυμητό επίπεδο. Τέλος, υπάρχει ο τριφασικός ζυγός στον οποίο συνδέεται το φορτίο που αποτελεί και την τερματική συσκευή της πειραματικής διάταξης. Στο κεφάλαιο 3 γίνεται μια σύγκριση των διαθέσιμων ψηφιακών μεθόδων για την υλοποίηση των απαραίτητων ελέγχων ενώ έπειτα παρουσιάζονται θεωρητικά αυτοί οι έλεγχοι. Οι διαθέσιμες ψηφιακές μέθοδοι για την πραγματοποίηση των ελέγχων είναι ο μικροεπεξεργαστής ψηφιακού σήματος (Digital Signal Processor-DSP) και οι ψηφιακές κάρτες της εταιρίας Νational Ιnstruments οι οποίες και τελικά επιλέχθηκαν. Οι απαιτούμενοι έλεγχοι που πρέπει να εφαρμοσθούν στην πειραματική μας διάταξη είναι όπως ήδη αναφέραμε η παραγωγή παλμών με τις τεχνικές της ημιτονοειδούς διαμόρφωσης εύρους παλμών (SPWM) και διαμόρφωσης εύρους παλμών (PWM) όπως και ο ασαφής έλεγχος. Στο κεφάλαιο 4 παρουσιάζονται αναλυτικά όλες οι συσκευές της πειραματικής μας διάταξης με ιδιαίτερη αναφορά σε όσες κατασκευάστηκαν στο εργαστήριο (όπως ο ΣΡ/ΣΡ (dc/dc) μετατροπέας ανύψωσης τάσης ) ενώ γίνεται και επεξήγηση διάφορων πρακτικών προβλημάτων που ανέκυψαν κατά την χρησιμοποίηση τους (για παράδειγμα με τον τριφασικό μετασχηματιστή). Στο κεφάλαιο 5 παρουσιάζεται η διαδικασία ανάπτυξης στην πλατφόρμα του Labview του προγράμματος που υλοποιεί τους απαιτούμενους ελέγχους. Πραγματοποιείται λοιπόν μια αναλυτική παρουσίαση όλων των εργαλείων και των ρυθμίσεων τους που μας επέτρεψαν να φθάσουμε στο επιθυμητό αποτέλεσμα. Τέλος, στο κεφάλαιο 6 παρουσιάζονται τα πειραματικά αποτελέσματα και παραθέτουμε τα συμπεράσματα που προέκυψαν. Πιο αναλυτικά υπάρχει παράθεση γραφημάτων και μετρήσεων για το σύνολο της πειραματικής διάταξης ενώ δίνεται ιδιαίτερη προσοχή στην ανάδειξη της λειτουργίας του ελέγχου και του τρόπου που επιδρά στην διάταξη μας. Τέλος, γίνεται μια καταγραφή πιθανών επεκτάσεων αυτής της διπλωματικής εργασίας. / The thesis that follows, describes the procedure which we followed in order to be able to supply a RL load with the power produced by a fuel cell. The load’s voltage should have constant value and frequency. The experimental configuration which was constructed to help us fulfill our goal further from the fuel cell and the RL load, includes a dc dc boost converter, a voltage source inverter, a 3phase transformer, a LC filter, a device that electronically chooses the value of the load and finally the digital card which executes all the necessary controls. When we talk about controls, we refer firstly to the production of SPWM pulses which are used in order to control the voltage source inverter and to the production of PWM pulses which are needed by the dc dc boost converter. These pulses are produced with the aid of a model developed with Labview. In addition, with the use of our digital card and the model which we developed, we are capable of applying the fuzzy logic to our experimental configuration in order to stabilize the load’s voltage. To be certain that we have ensured the smooth supply of the RL load with the power produced by the fuel cell and a voltage signal of constant value and frequency and low harmonic content, we made step changes to the load’s value and alterations to the fuel cell’s output, in order to assure that the fuzzy logic takes charge of the duty to restore the desired voltage signal to the load. The thesis is organized in the following way: In chapter 1 we make a brief description of the renewable energy sources which dominate Greece (solar, wind, hydroelectric, geothermal and biomass energy) and we present extensively the applications of fuel cells. In chapter 2 we describe on a great scale all the devices which consist the power circuit of the experimental configuration . So, the power circuit consists of the fuel cell, which is our energy source, the dc dc boost converter and the voltage source inverter. Furthermore, we have a LC filter in order to limit the total harmonic distortion and a 3 phase transformer which increase the voltage to the desired level. Finally, we have a 3 phase load which is the terminal device of the experimental configuration. In chapter 3 we compare the available digital methods for performing the desired controls and afterwards we present them theoretically. The available digital methods, in order to accomplish the controls, are the Digital Signal Processor (DSP) and the digital cards constructed by National Instruments (is our final choice). The required controls that must be performed include, as we have already mentioned, the SPWM and PWM pulses and of course the fuzzy control. In chapter 4 we present extensively all the devices of our experimental configuration with a special reference to all the devices which were constructed in our lab (like the dc dc boost converter). We make also special reference to some practical problems that we encountered when we used the previous devices (par example with the 3 phase transformer). In chapter 5 we present the procedure in order to develop the Labview model which contains all the necessary controls. Thus, we make a detailed presentation of all the tools and the settings which allowed to us to fulfill our goal. In chapter 6 we present all the experimental results and the conclusions we drew. More specifically, we present graphs and measurements for every part of the experimental configuration and we give special attention in order to give prominence to the fuzzy controller’s impact. Finally, some possible extensions of this thesis are underlined.

Neutral-point-clamped (NPC) three-level inverter is capable of handling higher dc bus voltage and producing output waveform of better quality than a conventional two-level inverter. The main objective of the present work is to analyze the existing PWM schemes for two-level and three-level inverters in terms of line current ripple, and to design new PWM techniques for the NPC inverter to reduce line current distortion. Various discontinuous PWM or bus-clamping PWM (BCPWM) methods for a two-level voltage source inverter are analyzed in terms of rms line current ripple, which is evaluated by integrating the error voltage (i.e. error between the applied and reference voltages). The BCPWM schemes can be broadly classified into continual-clamp PWM (CCPWM) and split-clamp PWM (SCPWM). It is shown that split-clamp PWM scheme leads to lower harmonic distortion than CCPWM scheme. Further, advanced bus-clamping PWM (ABCPWM) methods for a two-level inverter are also studied. These methods clamp each phase to the positive and negative DC terminals over certain intervals as in BCPWM schemes, and also switch each phase at double the nominal frequency in certain other intervals unlike in BCPWM. Analytical closed-form expressions are derived for the total rms harmonic distortion due to SCPWM, CCPWM and ABCPWM schemes. Existing sinusoidal and bus-clamping PWM schemes for three-level NPC inverters are also analyzed in the space vector domain. These methods are compared in terms of line current ripple analytically as well as experimentally. As earlier, closed-form expressions are derived for the harmonic distortion factors corresponding to centered space vector PWM (CSVPWM) and the various BCPWM methods. A three-level inverter can be viewed as an equivalent two-level inverter in each sixth of the fundamental cycle or hextant. This is widely used to simplify the control of an NPC inverter. Further, this approach makes it simple to extend the BCPWM and ABCPWM methods for two-level inverters to three-level inverters. Furthermore, the method of analysis of line current ripple for the two-level inverter can also be easily extended to the three-level case. The pivot vector, which is half the length of the longest voltage vectors produced by the NPC inverter, acts as an equivalent null vector for the conceptual two-level inverter. Each pivot vector can be produced by two inverter states termed as “pivot states”. Typically, in continuous modulation methods for NPC inverter such as sinusoidal PWM and centered space vector PWM, the switching sequence (i.e. the sequence in which the voltage vectors are applied) begins and ends with the same pivot vector in each subcycle, which is equivalent to a half-carrier cycle. To be more precise, the switching sequence starts with one pivot state and ends with the other in each subcycle. However, in case of BCPWM schemes, only one pivot state is used in a subcycle. The choice of pivot state results in a variety of BCPWM schemes for an NPC inverter. Different BCPWM schemes are evaluated in terms of rms line current ripple. The optimal BCPWM, which minimizes the rms current ripple, is determined for an NPC inverter, controlled as an equivalent two-level inverter. Further, four new switching sequences are proposed here for a three-level inverter, controlled as a conceptual two-level inverter. These sequences apply the pivot vector only once, but employ one of the other two vectors twice within the subcycle. These four switching sequences are termed as “ABCPWM sequences” for three-level inverter. These sequences exploit the flexibility available in the space vector approach to PWM to switch a phase more than once in a subcycle, which results in the application of an active vector twice within the subcycle. Influence of the proposed ABCPWM sequences on the line current ripple over a subcycle is studied. The various sequences are compared in terms of rms line current ripple over a subcycle. An analytical closed-form expression for rms line current ripple over a subcycle is derived in terms of reference magnitude, angle of reference voltage vector, and subcycle duration for each of the sequences. Further, closed-form expressions are also derived for the rms current ripple over a line cycle in terms of modulation index and subcycle duration, corresponding to the various sequences. The four proposed ABCPWM sequences for the NPC inverter can be grouped into two pairs of sequences. Each pair of sequences is shown to perform better than the individual sequences, if the two sequences are employed in appropriate spatial regions. Hence, with these two pairs of sequences, two hybrid PWM schemes are proposed. Finally, a hybrid PWM technique is proposed which employs all five sequences (conventional and proposed four sequences) in spatial regions where each performs the best. This is termed as “five-zone hybrid PWM”. The total harmonic distortion (THD) in the motor current, pertaining to all the proposed schemes, is studied theoretically over the entire range of linear modulation. The theoretical investigations are validated experimentally on a 2.2 kW, 415V, 4.9A, 50 Hz induction motor drive. The no-load current THD is measured over a range of fundamental frequency from 10 Hz to 50 Hz in steps of 2 Hz for the various PWM methods. Theoretical and experimental results bring out the reduction in current THD due to the proposed BCPWM schemes at fundamental frequencies of 45 Hz and above, compared to CSVPWM. The ABCPWM methods improve the performance at higher as well as lower modulation indices. Further improvement is achieved with the proposed five-zone hybrid PWM. At the rated frequency (50 Hz) of the drive, the improvement in line current distortion is around 36% with this hybrid PWM scheme over CSVPWM. The reduction in THD is also experimentally verified at different loads on the motor. The difference between the top and bottom capacitor voltages is measured at various operating conditions, corresponding to CSVPWM and the proposed schemes. No significant difference is observed in the dc neutral voltage shifts with the different proposed schemes and CSVPWM method. Thus, the proposed methods improve the THD at low and high speed ranges without appreciable worsening of the dc voltage unbalance.

The inverter dead-time is integral to the safety of a voltage source inverter (VSI). Dead-time is introduced between the complementary gating signals of the top and bottom switches in each VSI leg to prevent shoot-through fault. This thesis reports and investigates dead-time induced sub-harmonic oscillations in open-loop induction motor drives of different power levels, under light-load conditions. The thesis develops mathematical models that help understand and predict the oscillatory behaviour of such motor drives due to dead-time act. Models are also developed to study the impact of under-compensation and over-compensation of dead-time act on stability. The various models are validated through extensive simulations and experimental results. The thesis also proposes and validates active damping schemes for mitigation of such sub-harmonic oscillations. The thesis reports high-amplitude sub-harmonic oscillations in the stator current, torque and speed of a 100-kW open-loop induction motor drive in the laboratory, operating under no-load. Experimental studies, carried out on 22-kW, 11-kW, 7.5-kW and 3.7-kW open-loop induction motor drives, establish the prevalence of dead-time induced sub-harmonic oscillations in open-loop motor drives of different power levels. An experimental procedure is established for systematic study of this phenomenon in industrial drives. This procedure yields the operating region, if any, where the motor drive is oscillatory. As a first step towards understanding the oscillatory behaviour of the motor drive, a mathematical model of the VSI is derived in a synchronously revolving reference frame (SRF), incorporating the of dead-time on the inverter output voltage. This leads to a modified dynamic model of the inverter-fed induction motor in the SRF, inclusive of the dead-time act. While the rotor dynamic equations are already non-linear, dead-time is found to introduce nonlinearities in the stator dynamic equations as well. The nonlinearities in the modified dynamic model make even the steady solution non-trivial. Under steady conditions, the dead-time can be modelled as the drop across an equivalent resistance (Req0) in the stator circuit. A precise method to evaluate the equivalent resistance Req0 and a simple method to arrive at the steady solution are proposed and validated. For the purpose of stability analysis, a small-signal model of the drive is then derived by linearizing the non-linear dynamic equations of the motor drive, about a steady-state operating point. The proposed small-signal model shows that dead-time contributes to different values of equivalent resistances along the q-axis and d-axis and also to equivalent cross-coupling reactance’s that appear in series with the stator windings. Stability analysis performed using the proposed model brings out the region of oscillatory behaviour (or region of small-signal instability) of the 100-kW motor drive on the voltage versus frequency (V- f) plane, considering no-load. The oscillatory region predicted by the small-signal analysis is in good agreement with simulations and practical observations for the 100-kW motor drive. The small-signal analysis is also able to predict the region of oscillatory behaviour of an 11-kW motor drive, which is con consumed by simulations and experiments. The analysis also predicts the frequencies of sub-harmonic oscillations at different operating points quite well for both the drives. Having the validity of the small-signal analysis at different power levels, this analytical procedure is used to predict the regions of oscillatory behaviour of 2-pole, 4-pole, 6-pole and 8-pole induction motors rated 55 kW and 110 kW. The impact of dead-time on inverter output voltage has been studied widely in literature. This thesis studies the influence of dead-time on the inverter input current as well. Based on this study, the dynamic model of the inverter fed induction motor is extended to include the dc-link dynamics as well. Simulation results based on this extended model tally well with the experimentally measured dc-link voltage and stator current waveforms in the 100-kW drive. Dead-time compensation may be employed to mitigate the dead-time and oscillatory behaviour of the drive. However, accurate dead-time compensation is challenging to achieve due to various factors such as delays in gate drivers, device switching characteristics, etc. Effects of under-compensation and over-compensation of dead time are investigated in this thesis. Under-compensation is shown to result in the same kind of oscillatory behaviour as observed with dead-time, but the fundamental frequency range over which such oscillations occur is reduced. On the other hand, over-compensation of dead-time effect is shown to result in a different kind of oscillatory behaviour. These two types of oscillatory behaviour due to under- and over-compensation, respectively, are distinguished and demonstrated by analyses, simulations and experiments on the 100-kW drive. To mitigate the oscillatory behaviour of the drive, an active damping scheme is proposed. This scheme emulates the effect of an external inductor in series with the stator winding. A small-signal model is proposed for an induction motor drive with the proposed active damping scheme. Simulations and experiments on the 100-kW drive demonstrate effective mitigation of light-load instability with this active damping scheme. In the above inductance emulation scheme, the emulated inductance is seen by the sub-harmonic components, fundamental component as well as low-order harmonic components of the motor current. Since the emulated inductance is also seen by the fundamental component, there is a fundamental voltage drop across the emulated inductance, leading to reduced co-operation of the induction motor. Hence, an improved active damping scheme is proposed wherein the emulated inductance is seen only by the sub-harmonic and low-order harmonic components. This is achieved through appropriate altering in the synchronously revolving domain. The proposed improved active damping scheme is shown to mitigate the sub-harmonic oscillation effectively without any reduction in flux.

In the past two decades the core aircraft technology is going through a drastic change. The traditional technologies that is almost half a century old, is going through a complete revamp. In the new “More Electric Aircraft” technology many mechanical, pneumatic and hydraulic systems are being replaced by electrical and power electronic systems. Airbus-A380, Boeing B-787 are the pioneers in the family of these new breed of aircrafts. As the aircraft technology is moving towards “More Electric”, more and more electric motors and motor controllers are being used in new aircrafts. Number of electric motor drive systems has increased by about ten times in more electric aircrafts compared to traditional aircrafts. Weight of any electric component that goes into aircraft needs to be low to reduce the overall weight of aircraft so as to improve the fuel efficiency of the aircraft. Hence there is an increased need to reduce weight of motors and motor controllers in commercial aircraft. High speed ironless axial flux permanent magnet brushless dc motors are becoming popular in the new more-electric aircrafts because of their ability to meet the demand of light weight, high power density, high efficiency and high reliability. However, these motors come with very low inductance, which poses a big challenge to the motor controllers in controlling the ripple current in motor windings. Multilevel inverters can solve this problem. Three-level inverters are proposed in this thesis for driving axial flux BLDC motors in aircraft. Majority of the motors in new more electric aircrafts are in the power range of 2kW to 20kW, while a few motor applications being in the range of 100kW to 150kW. Motor controllers in these applications run from 270Vdc or 540Vdc bus which is the standard in new more electric aircraft architecture. Multilevel Inverter is popular in the industry for high power and high voltage applications, where high-voltage power switching devices like IGBT, GTO are popularly used. However multilevel inverters have not been tried in the low power range which is appropriate for aircraft applications. A detail analysis of practical feasibility of constructing three-level inverter in lower power and voltage level is presented in this thesis. Analysis is presented that verify the advantages of driving low voltage and low power (300Vdc to 600Vdc and less than 100kW) motors with multilevel inverters. Practical considerations for design of MOSFET based three-level inverter are investigated and topological modifications are suggested. The effect of clamping diodes in the diode clamped multilevel inverters play an important role in determining its efficiency. SiC diodes are proposed to be used as clamping diodes. Further, it is realised that power loss introduced by reverse recovery of MOSFET body diode prohibits use of MOSFET in hard switched inverter legs. Hence, a technique of avoiding the reverse recovery losses of MOSFET body diode in three-level NPC inverter is conceived. The use of proposed multilevel inverter topology enables operation at high switching frequency without sacrificing efficiency. High switching frequency of operation reduces the output filter requirement, which in turn helps reducing size of the inverter. In this research work elaborate trade-off analysis is done to quantify the suitability of multilevel inverters in the low power applications. For successful operation of three-level NPC inverter in aircraft electrical system, it is important for the DC bus structure in aircraft electric primary distribution system to be compatible to drive NPC inverters. Hence a detail study of AC to DC power conversion system as applied to commercial aircraft electrical system is done. Multi-pulse rectifiers using autotransformers are used in aircrafts. Investigation is done to improve these rectifiers for future aircrafts, such that they can support new technologies of future generation motor controllers. A new 24-pulse isolated transformer rectifier topology is proposed. From two 15º displaced 6-phase systems feeding two 12-pulse rectifiers that are series connected, a 24-pulse rectifier topology is obtained. Though, windings of each 12-pulse rectifiers are isolated from primary, the 6-phase generation is done without any isolation of the transformer windings. The new 24-pulse transformer topology has lower VA rating compared to standard 12-pulse rectifiers. Though the new 24-pulse transformer-rectifier solution is robust and simple, it adds to the weight of the overall system, as compared to the present architecture as the proposed topology uses isolated transformer. Non-isolated autotransformer cannot provide split voltage at the dc-link that creates a stable mid-point voltage as required by the three-level NPC inverter. Hence, a new front-end AC-DC power conversion system with switched capacitor is conceived that can support motor controllers driven by three-level inverters. Laboratory experimental results are presented to validate the new proposed topology. In this proposed topology, the inverter dc-link voltage is double the input dc-link voltage. An intense research work is performed to understand the operation of Trapezoidal Back EMF BLDC motor driven by three-Level NPC inverter. Operation of BLDC motor from three-Level inverter is primarily advantageous for low inductance motors, like ironless axial flux motors. For low inductance BLDC motor, very high switching frequency is required to limit the magnitude of ripple current in motor winding. Three-level inverters help limiting the magnitude of motor ripple current without increasing the switching frequency to very high value. Further, it is analysed that dc link mid-point current in three-level NPC inverter for driving trapezoidal BLDC motor has a zero average current with fundamental frequency same as switching frequency. Because of this, trapezoidal BLDC motors can easily be operated from three-level NPC inverter without any special attention given to mid-point voltage unbalance. One non-ideal condition arrives in practical implementation of the inverter that leads to non-zero average mid point current. Unequal gate drive dead time delays from one leg to other leg of inverter introduce dc-link mid-point voltage unbalance. For the motoring mode operation of trapezoidal BLDC motor drive, simple gate drive logic is researched that eliminates need of the gate drive dead-time, and hence solves the mid-point voltage unbalance issue. Simple closed loop control scheme for mid-point voltage balancing also is also proposed. This control scheme may be used in applications where very precise control of speed and torque ripple is warranted. All the investigations reported in this thesis are simulated extensively on MATHCAD and MATLAB platform using SIMULINK toolbox. A laboratory experimental set-up of three-Level inverter driving axial flux BLDC motor is built. The three-level inverter, operating from 300Vdc bus is built using 500V MOSFETs and 600V SiC diodes. All the control schemes are implemented digitally on digital signal processor TMS320F2812 DSP platform and GAL22V10B platforms. Experimental results are collected to validate the theoretical propositions made in the present research work. At the end, in chapter 5, some future works are proposed. A new external voltage balance circuit is proposed where the inverter dc-link voltage is same as the input dc-link voltage. This topology is based on the resonant converter principle and uses a lighter resonant inductor than prior arts available in literature. Detail simulation and experimentation of this topology may be carried out to validate the industrial benefits of this circuit. It is also thought that current source inverters may work as an alternative to voltage source inverters for driving BLDC motors. Current source inverters eliminate use of bulky DC-link capacitors. Long term reliability of current source inverters is higher than voltage source inverters due to the absence of possibility of shoot-through. Further, in voltage source inverters, the voltage at the motor terminal is limited by the source voltage (dc-link voltage). This issue is eliminated in current source inverters. An interface circuit is conceived to reduce the size of dc-link inductors in current source inverters, pending detail analysis and experimental verification. The interface circuit bases its fundamentals on the principles of operation of multilevel inverters for BLDC motors that is presented in this thesis.

Multilevel converters have become the direct accepted solution for high power converter applications. They are used in wide variety of power electronic applications like power transmission and distribution, electric motor drives, battery management and renewable energy management to name a few. For medium and high voltage motor drives, especially induction motor drives, the use of multilevel voltage source inverters have become indispensible. A high voltage multilevel inverter could be realized using low voltage switching devices which are easily available and are of low cost. A multilevel inverter generates voltage waveforms of very low harmonic distortion by switching between voltage levels of reasonably small amplitude differences. Thus the dv/dt of the output voltage waveform is small and hence the electromagnetic interference generated is less. Because of better quality output generation, the switching frequency of the multilevel inverters could be reduced to control the losses. Thus, a multilevel converter stands definitely a class apart in terms of performance from a conventional two-level inverter. Many multilevel inverter topologies for induction motor drives are available in the literature. The basic multilevel topologies are the neutral point clamped (NPC) inverter, flying capacitor (FC) inverter and the cascaded H-bridge (CHB) inverter. Various other hybrid multilevel topologies have been proposed by using the basic multilevel inverter topologies. It is also possible to obtain multilevel output by using conventional two-level inverters feeding an open-end winding induction motor from both sides. All the conventional multilevel voltage source inverters generate hexagonal (6 sided polygons) voltage space vector structures. When an inverter with hexagonal space vector structure is operated in the over modulation range, significant low order harmonics are generated in the phase voltage output. Over modulation operation is required for the full utilization of the available DC-link voltage and hence maximum power generation. Among the harmonics generated, the fifth and seventh harmonics are of significant magnitudes. These harmonics generate torque ripple in the motor output and are undesirable in high performance motor drive applications. The presence of these harmonics further creates problems in the closed loop current control of a motor, affecting the dynamic performance. Again, the harmonic currents generate losses in the stator windings. Therefore, in short, the presence of harmonic voltages in the inverter output is undesirable. Many methods have been proposed to eliminate or mitigate the effect of the harmonics. One solution is to operate the inverter at high switching frequency and thereby push the harmonics generated to high frequencies. The stator leakage inductance offers high impedance to the high frequency harmonics and thus the harmonic currents generated are negligible. But, high switching frequency brings switching losses and high electromagnetic interference generation in the drive system. And also, high switching frequency operation is effective only in the linear modulation range. Another solution is to use passive harmonic filters at the inverter output. For low order harmonics, the filter components would be bulky and costly. The loss created by the filters degrades the efficiency of the drive system as well. The presence of a filter also affects the dynamic performance of the drive system during closed loop operation. Special pulse width modulation (PWM) techniques like selective harmonic elimination (SHE) PWM can prevent the generation of a particular harmonic from the phase voltage output. The disadvantages of such schemes are limited modulation index, poor dynamic performance and extensive offline computations. An elegant harmonic elimination method is to generate a voltage space vector structure having more number of sides like a dodecagon (12 sided polygons) or an octadecagon (18 sided polygons) rather than a hexagon. Inverter topologies generating dodecagonal voltage space vector structure eliminate fifth and seventh order harmonics, represented as 6n 1; n = odd harmonics, from the phase voltages and hence from the motor phase currents, throughout the entire modulation range. The first harmonics appearing the phase voltage are the 11th and 13th harmonics. Another advantage is the increased linear modulation range of operation for a given DC-link voltage, because geometrically dodecagon is closer to circle than a hexagon. An octadecagonal structure eliminates the 11th and 13th harmonics as well from the phase voltage output. The harmonics present in the phase voltage are of the order 18n 1; n = 1; 2; 3; :::. Thus the total harmonics distortion (THD) of the phase voltage is further improved. The linear modulation range also gets enhanced compared to hexagonal and dodecagonal structures. Multilevel dodecagonal and octadecagonal space vector structures combines the advantages of both multilevel structure and dodecagonal and octadecagonal structure and hence are very attractive solutions for high performance induction motor drive schemes. Chapter 1 of this thesis introduces the multilevel in-verter topologies generating hexagonal, dodecagonal and octadecagonal voltage space vector structures. Inverter topologies generating multilevel dodecagonal and octadecago-nal voltage space vector structures have been proposed before but using multiple DC sources delivering active power. The presence of more than one DC source in the inverter topology makes the back to back operation (four-quadrant operation) of the drive system difficult. And also the drive system becomes more costly and bulky. This thesis proposes induction motor drive schemes generating multilevel dodecagonal and octadecagonal volt-age space vector structures using a single DC source. In Chapter 2, an induction motor drive scheme generating a six-concentric multilevel dodecagonal voltage space vector structure using a single DC source is proposed for an open-end winding induction motor. In the topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a DC source (Vdc) which delivers the entire active power, whereas the secondary inverter DC-link is maintained by a capacitor at a voltage of 0:289Vdc, which is self-balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small DC-link voltage. Hence, switching losses are small for both primary and secondary inverters. An open-loop V/f scheme was used to test the topology and modulation scheme. In the work proposed in Chapter 3, the topology and modulation scheme used in the first work is modified for a star connected induction motor. Again, the scheme uses only a single DC source and generates a six-concentric multilevel space vector struc-ture. The power circuit topology is realized using a three-level flying capacitor (FC) inverter cascaded with an H-bridge (CHB). The capacitors in the CHB inverter are maintained at a voltage level of 0:1445Vdc. The FC inverter switches between volt-age levels of [Vdc; 0:5Vdc; 0] and the CHB inverter switches between voltage levels of [+01445Vdc; 0; 0:1445Vdc]. The PWM scheme generates a quasi-square waveform output from the FC inverter. This results in very few switchings of the FC inverter in a funda-mental cycle and hence the switching losses are controlled. The CHB inverter switches Ch. 0: at high frequency compared to the FC inverter and cancels the low order harmonics (6n 1; n = odd) generated by the FC inverter. Even though the CHB operates at higher switching frequency, the switchings are at low voltage thereby controlling the losses. The linear modulation range of operation is extended to 48:8Hz for a base frequency of 50Hz. An open-loop V/f scheme was used to test the topology and modulation scheme. In Chapter 4, a nine-concentric multilevel octadecagonal space vector structure is proposed for the first time, again using a single DC source. The circuit topology remains same as the work in Chapter 3, except that the CHB capacitor voltage is maintained at 0:1895Vdc. The 5th; 7th; 11th and 13th harmonics are eliminated from the phase voltage output. The linear modulation range is enhanced to 49:5Hz for a base speed of 50Hz. An open-loop V/f scheme and rotor field oriented control scheme were used to test the proposed drive system. All the proposed drive schemes have been extensively simulated and tested in hard-ware. Simulation was performed in MATLAB-SIMULINK environment. For implement-ing the inverter topology, SKM75GB12T4 IGBT modules were used. The control al-gorithms were implemented using a DSP (TI’s TMS320F28334) and an FPGA (Xilinx Spartan XC3S200). A 1kW , 415V , 4-pole induction motor was used for the experiment purpose. The above mentioned induction motor drive schemes generate phase voltage outputs in which the low order harmonics are absent. The linear modulation range is extended near to the base frequency of operation compared to hexagonal space vector structure. In the inverter topologies, the secondary inverters or the CHB inverters functions as harmonic filters and delivers zero active power. The primary inverter in the topologies switches at low frequency, reducing the power loss. Single DC source requirement brings down the cost of the system as well as permitting easy four-quadrant operation. This is also advantageous in battery operated systems like EV applications. With these features and advantages, the proposed drive schemes are suitable for high performance, medium voltage induction motor drive applications.

In DC to AC power conversion, voltage source inverters (VSI) based current controllers are usually preferred for today’s high performance AC drive which requires excellent dynamic and steady state performances at different transient and load conditions, with the additional advantages like inherent short circuit and over current protection. Out of different types of current controllers, hysteresis controllers are widely used due to their simplicity and ability to meet the requirements for a high performance AC drives. But the conventional hysteresis controllers suffers from wide variation of PWM switching frequency, overshoot in current errors, sub-harmonic components in the current waveform and non-optimum switching at different operating point of the drive system. To mitigate these problems, particularly to control the switching frequency variation, which is the root cause of all other problems, several methodologies like ramp comparison based controller, predictive current controller, etc. were proposed in the literature. But amplitude and phase offset error in the ramp comparison based controllers and complexities involved in the predictive controllers have limited the use of these controllers. Moreover, these type of controllers, which uses three separate and independently controlled tolerance band (sinusoidal type or adaptive) to control the 3-phase currents, shows limited dynamic responses and they are not simple to implement. To tackle the problem of controlling 3-phase currents simultaneously, space vector based hysteresis current controller is very effective as it combines the current errors of all the three phases as a single entity called current error space vector. It has a single controller’s logic with a hysteresis boundary for controlling this current error space vector. Several papers on space vector based hysteresis controllers for 2-level inverter with constant switching frequency have been published, but the application of the constant switching frequency based hysteresis current controllers for multi¬level inverter fed drive system, has not been addressed properly. Use of multi-level inverter in modern high performance drive for medium and high voltage levels is more prominent because of multi-level’s inherent advantages like good power quality, good electromagnetic compatibility (EMC), better DC link voltage utilization, reduced device voltage rating, so on. Even though some of the earlier works describe three-level space vector based hysteresis current controller techniques, they are specific to the particular level of inverters and does not demonstrate constant switching frequency of operation. This thesis proposes a novel approach where nearly constant switching frequency based hysteresis controller can be implemented for any general n-level inverter and it is also independent of inverter topology. In this work, varying parabolic boundary is used as the hysteresis current error boundary for controlling the current in a multi-level space vector structure. The computation of the parabolic boundary is accomplished offline and all the necessary boundary parameters at different operating points are stored in the look-up tables. The varying parabolic boundary for the multi-level space vector structure depends on the sampled reference phase voltage values which are estimated from stator current error information and then using the equivalent circuit model of induction motors. Here, a mapping technique is adopted to bring down all the three phase references to the inner- most carrier region, which results in mapping any outer triangular structure where tip of the voltage space vector is located, to one of the sectors of the inner most hexagon of the multi-level space vector structure. In this way, the required mapped sector information is easily found out to fix the correct orientation of the parabolic boundary in the space vector plane. This mapping technique simplifies the controller’s logic similar to that of a 2-level inverter. For online identification of the inverter switching voltage vectors constructing the present outer triangle of the multi-level space vector structure, the proposed controller utilizes the sampled phase voltage references. This identification technique is novel and also generic for any n-level inverter structure. This controller is having all the advantages of a space vector based hysteresis current controller and that of a multi-level inverter apart from having a nearly constant switching frequency spectrum similar to that of a voltage controlled space vector PWM (VC-SVPWM). Using the proposed controller, simulation study of a five-level inverter fed induction motor (IM) drive scheme, was carried out using Matlab-Simulink. Simulation study showed that the switching frequency variations in a fundamental cycle and over the entire speed range of the linear modulation region, is similar to that of a VC-SVPWM based multi-level VSI. The proposed hysteresis controller is experimentally verified on a 7.5 kW IM vector control drive fed with a five-level VSI. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency is implemented on a TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the controller is tested with the drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and quick transient results of the proposed drive are presented in this thesis. This thesis also proposes another type of hysteresis controller, firstly for 2-level inverter and then for general n-level multi-level inverter, which eliminates the parabolic boundary and replaces it with a boundary which is computed online and does not use any look up table for boundary selection. The current error boundary for the proposed hysteresis controller is computed online in a very simple way, using the information of estimated fundamental stator voltages along α and β axes of space vector plane. The method adopted for the proposed controller to compute the boundary does not involve any complicated computations and it selects the optimal vector for switching when current error space vector crosses the boundary. This way adjacent voltage vector switching similar to VC-SVPWM can be ensured. For 2-level inverter, it precisely determines the sector, in which reference voltage vector is present. In multi-level inverter, this controller also finds out the mapped sector information using the same mapping techniques as explained in the first part of this thesis. In both 2-level and multi-level inverter, the proposed controller does not use any look up table for finding individual voltage vector switching times from the estimated voltage references. These switching times are used for the computation of hysteresis boundary for individual vectors. Thus the hysteresis boundary for individual vectors is exactly calculated and the boundary is similar to that of VC-SVPWM scheme for the respective levels of inverter. In the present scheme, the phase voltage harmonic spectrum is very close to that of a constant switching frequency VC-SVPWM inverter. In this thesis, at first, the proposed on line boundary computation scheme is implemented for a 2-level inverter based controller for the initial study, so that it can be executed as fast as 10 µs in a DSP platform, which is required for accurate current control. Then the same algorithm of 2-level inverter is extended for multi-level inverter with the additional logic for online identification of nearest switching voltage vectors (also used in the parabolic boundary case) for the present sampling interval. Previously mentioned mapping technique for multi-level inverter, is also implemented here to bring down the phase voltage references to the inner-most carrier region to realize the multi-level current control strategy equivalent to that of a 2-level inverter PWM current control. Simulation study to verify the steady state as well as transient performance of the proposed controller for both 2-level as well as five-level VSI fed IM drive is carried out using Simulink tool box of MATLAB Simulation Software. The proposed hysteresis controllers are experimentally verified on a 7.5 kW IM vector control drive fed with a two-level VSI and five-level VSI separately. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency profile for phase voltage is implemented on the TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the proposed hysteresis controllers are tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are also presented for different operating conditions, through the simulation study followed by experimental verifications. Even though the simulation and experimental verifications are done on a 5-level inverter to explain the proposed hysteresis controller, it can be easily implemented for any general n-level inverter, as described in this thesis.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.

For medium and high-voltage drive applications, multilevel inverters are very popular. It is due to their superior performance compared to 2-level inverters such as reduced harmonic content in the output voltage and current, lower common mode voltage and dv=dt, and lesser voltage stress on power switches. The popular circuit topologies for multilevel inverters are neutral point clamped, cascaded H-bridge and flying capacitor based circuits. There exist different combinations of these basic topologies to realize multilevel inverters with modularity, better fault tolerance, and reliability. Due to these advantages, multilevel converters are getting good acceptance from the industry, and researchers all over the world are continuously trying to improve the performance of these converters. To meet such demands, three multilevel inverter topologies are proposed in this thesis. These topologies can be used for high-power induction motor drives, and the concepts presented are also applicable for synchronous motor drives, grid-connected inverters, etc. To get nearly sinusoidal phase current waveforms, the switching frequency of the conventional inverter has to be increased. It will lead to higher switching losses and electromagnetic interference. The problem with lower switching frequency is the intro- duction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching, and it is possible to eliminate these harmonics by dodecagonal switching. Further improvement in the waveform quality is possible by octadecagonal voltage space-vectors. In this case, the complete elimination of 11th and 13th harmonic is possible for the entire modulation range. The concepts of dodecagonal and octadecagonal voltage space-vectors are used in the proposed inverter topologies. The first topology proposed in this thesis consists of cascaded connection of two H-bridge cells. The two cells are fed from unequal DC voltage sources having a ratio of 1 : 0:366, and this inverter can produce six concentric dodecagonal voltage space- vectors. This ratio of voltages can be obtained easily from a combination of star-delta transformers, since 1 : 0:366 = ( p 3 + 1) : 1. The cascaded connection of two H-bridge cells can generate nine asymmetric pole voltage levels, and the combined three-phase inverter can produce 729 voltage space-vectors (9 9 9). From this large number of combinations, only certain voltage space-vectors are selected, which forms dodecagonal pattern. In the case of conventional multilevel inverters, the voltage space-vector diagram consists of equilateral triangles of equal size, but for the proposed inverter, the triangular regions are isosceles and are having different sizes. By properly placing the voltage space-vectors in a sampling period, it is possible to achieve lower switching frequency for the individual cells, with substantial improvement in the harmonic spectrum of the output voltage. During the experimental veri cation, the motor is operated at di erent speeds using open loop v=f control method. The samples taken are always synchronised with the start of the sector to get synchronised PWM. The number of samples per sector is decreased with increase in the fundamental frequency to limit the switching frequency. Even though many topologies are available in literature, the most preferred topology for drives application such as traction drives is the 3-level NPC structure. This implies that the industry is still looking for viable alternatives to construct multilevel inverter topologies based on available power circuits. The second work focuses on the development of a multilevel inverter for variable speed medium-voltage drive application with dodecagonal voltage space-vectors, using lesser number of switches and power sources compared to earlier implementations. It can generate three concentric 12-sided polygonal voltage space-vectors and it is based on commonly available 2-level and 3-level inverters. A simple PWM timing computation method based on the hexagonal space-vector PWM is developed. The sampled values of the three-phase reference voltages are initially converted to the timings of a two-level inverter. These timings are mapped to the dodecagonal timings using a change of basis transformation. The voltage space- vector diagram of the proposed drive consists of sixty isosceles triangular regions, and the dodecagonal timings calculated are converted to the timings of the inner triangles. A searching algorithm is used to identify the triangular region in which the reference vector is located. A front-end recti er that may be easily implemented using standard star-delta transformers is also developed, to provide near-unity power factor. To test the performance of the inverter drive, an open-loop v=f control is used on a three-phase induction motor under no-load condition. The harmonic spectra of the phase voltages were computed in order to analyse the harmonic distortion of the waveforms. The carrier frequency was kept around 1.2 KHz for the entire range of operation. If the switching frequency is decreased, the conventional hexagonal space-vector based switching introduce signifi cant 5th, 7th, 11th and 13th harmonics in the phase currents. Out of these dominant harmonics, the 5th and 7th harmonics can be completely suppressed using dodecagonal voltage space-vector based switching as observed in the first and second work. It is also possible to remove the 11th and the 13th harmonics by using voltage space-vectors with 18 sides. The last topology is based on multilevel octadecagonal (18-sided polygon) voltage space-vectors, and it has better harmonic performance than the previously mentioned topologies. Here, a multilevel inverter system capable of producing three octadecagonal voltage space-vectors is proposed for the fi rst time, along with a simple timing calculation method. The conventional three-level inverters are only required to construct the proposed drive. Four asymmetric power supply voltages with 0:3054Vdc, 0:3473Vdc, 0:2266Vdc and 0:1207Vdc are required for the operation of the drive, and it is the main drawback of the circuit. Generally front-end isolation transformer is essential for high-power drives and these asymmetric voltages can be easily obtained from the multiple windings of the isolation transformer. The total harmonic distortion of the phase current is improved due to the 18-sided voltage space-vector switching. The ratio of the radius of the largest polygon and its inscribing circle is cos10 = 0:985. This ratio in the case of hexagonal voltage space-vector modulation is cos30 = 0:866, which means that the range of the linear modulation for the proposed scheme is signifi cantly higher. The drive is designed for open-end winding induction motors and it has better fault tolerance. It any of the inverter fails, it can be easily bypassed and the drive will be still functional with reduced speed. Open loop v=f control and rotor flux oriented vector control schemes were used during the experimental verifi cation. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the entire range of operation, the carrier was synchronized with the fundamental. For the synchronization, the sampling period is varied dynamically so that the number of samples in a triangular region is fi xed, keeping the switching frequency around 1.2 KHz. The average execution time for the v=f code was found to be 20 S, where as for vector control it took nearly 100 S. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. To convert the triangle number and the timings to IGBT gate drive logic, an FPGA (XC3S200) was used. A constant dead-time of 1.5 S is also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. Hall-effect sensors were used to measure the phase currents and DC bus voltages. An incremental shaft position encoder with 2500 pulse per revolution is also connected to the motor shaft, to measure the angular velocity. 1200 V, 75 A IGBT half-bridge module is used to realize the switches. The concepts were initially simulated and experimentally verifi ed using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control techniques presented shall still remain applicable.

For medium and high-voltage drive applications, multilevel inverters are very popular. It is due to their superior performance compared to 2-level inverters such as reduced harmonic content in the output voltage and current, lower common mode voltage and dv=dt, and lesser voltage stress on power switches. The popular circuit topologies for multilevel inverters are neutral point clamped, cascaded H-bridge and flying capacitor based circuits. There exist different combinations of these basic topologies to realize multilevel inverters with modularity, better fault tolerance, and reliability. Due to these advantages, multilevel converters are getting good acceptance from the industry, and researchers all over the world are continuously trying to improve the performance of these converters. To meet such demands, three multilevel inverter topologies are proposed in this thesis. These topologies can be used for high-power induction motor drives, and the concepts presented are also applicable for synchronous motor drives, grid-connected inverters, etc. To get nearly sinusoidal phase current waveforms, the switching frequency of the conventional inverter has to be increased. It will lead to higher switching losses and electromagnetic interference. The problem with lower switching frequency is the intro- duction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching, and it is possible to eliminate these harmonics by dodecagonal switching. Further improvement in the waveform quality is possible by octadecagonal voltage space-vectors. In this case, the complete elimination of 11th and 13th harmonic is possible for the entire modulation range. The concepts of dodecagonal and octadecagonal voltage space-vectors are used in the proposed inverter topologies. The first topology proposed in this thesis consists of cascaded connection of two H-bridge cells. The two cells are fed from unequal DC voltage sources having a ratio of 1 : 0:366, and this inverter can produce six concentric dodecagonal voltage space- vectors. This ratio of voltages can be obtained easily from a combination of star-delta transformers, since 1 : 0:366 = ( p 3 + 1) : 1. The cascaded connection of two H-bridge cells can generate nine asymmetric pole voltage levels, and the combined three-phase inverter can produce 729 voltage space-vectors (9 9 9). From this large number of combinations, only certain voltage space-vectors are selected, which forms dodecagonal pattern. In the case of conventional multilevel inverters, the voltage space-vector diagram consists of equilateral triangles of equal size, but for the proposed inverter, the triangular regions are isosceles and are having different sizes. By properly placing the voltage space-vectors in a sampling period, it is possible to achieve lower switching frequency for the individual cells, with substantial improvement in the harmonic spectrum of the output voltage. During the experimental veri cation, the motor is operated at di erent speeds using open loop v=f control method. The samples taken are always synchronised with the start of the sector to get synchronised PWM. The number of samples per sector is decreased with increase in the fundamental frequency to limit the switching frequency. Even though many topologies are available in literature, the most preferred topology for drives application such as traction drives is the 3-level NPC structure. This implies that the industry is still looking for viable alternatives to construct multilevel inverter topologies based on available power circuits. The second work focuses on the development of a multilevel inverter for variable speed medium-voltage drive application with dodecagonal voltage space-vectors, using lesser number of switches and power sources compared to earlier implementations. It can generate three concentric 12-sided polygonal voltage space-vectors and it is based on commonly available 2-level and 3-level inverters. A simple PWM timing computation method based on the hexagonal space-vector PWM is developed. The sampled values of the three-phase reference voltages are initially converted to the timings of a two-level inverter. These timings are mapped to the dodecagonal timings using a change of basis transformation. The voltage space- vector diagram of the proposed drive consists of sixty isosceles triangular regions, and the dodecagonal timings calculated are converted to the timings of the inner triangles. A searching algorithm is used to identify the triangular region in which the reference vector is located. A front-end recti er that may be easily implemented using standard star-delta transformers is also developed, to provide near-unity power factor. To test the performance of the inverter drive, an open-loop v=f control is used on a three-phase induction motor under no-load condition. The harmonic spectra of the phase voltages were computed in order to analyse the harmonic distortion of the waveforms. The carrier frequency was kept around 1.2 KHz for the entire range of operation. If the switching frequency is decreased, the conventional hexagonal space-vector based switching introduce signifi cant 5th, 7th, 11th and 13th harmonics in the phase currents. Out of these dominant harmonics, the 5th and 7th harmonics can be completely suppressed using dodecagonal voltage space-vector based switching as observed in the first and second work. It is also possible to remove the 11th and the 13th harmonics by using voltage space-vectors with 18 sides. The last topology is based on multilevel octadecagonal (18-sided polygon) voltage space-vectors, and it has better harmonic performance than the previously mentioned topologies. Here, a multilevel inverter system capable of producing three octadecagonal voltage space-vectors is proposed for the fi rst time, along with a simple timing calculation method. The conventional three-level inverters are only required to construct the proposed drive. Four asymmetric power supply voltages with 0:3054Vdc, 0:3473Vdc, 0:2266Vdc and 0:1207Vdc are required for the operation of the drive, and it is the main drawback of the circuit. Generally front-end isolation transformer is essential for high-power drives and these asymmetric voltages can be easily obtained from the multiple windings of the isolation transformer. The total harmonic distortion of the phase current is improved due to the 18-sided voltage space-vector switching. The ratio of the radius of the largest polygon and its inscribing circle is cos10 = 0:985. This ratio in the case of hexagonal voltage space-vector modulation is cos30 = 0:866, which means that the range of the linear modulation for the proposed scheme is signifi cantly higher. The drive is designed for open-end winding induction motors and it has better fault tolerance. It any of the inverter fails, it can be easily bypassed and the drive will be still functional with reduced speed. Open loop v=f control and rotor flux oriented vector control schemes were used during the experimental verifi cation. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the entire range of operation, the carrier was synchronized with the fundamental. For the synchronization, the sampling period is varied dynamically so that the number of samples in a triangular region is fi xed, keeping the switching frequency around 1.2 KHz. The average execution time for the v=f code was found to be 20 S, where as for vector control it took nearly 100 S. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. To convert the triangle number and the timings to IGBT gate drive logic, an FPGA (XC3S200) was used. A constant dead-time of 1.5 S is also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. Hall-effect sensors were used to measure the phase currents and DC bus voltages. An incremental shaft position encoder with 2500 pulse per revolution is also connected to the motor shaft, to measure the angular velocity. 1200 V, 75 A IGBT half-bridge module is used to realize the switches. The concepts were initially simulated and experimentally verifi ed using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control techniques presented shall still remain applicable.