This dissertation reports, for the first time, on the design and implementation of tunable micromachined bandpass filters in the ultra high frequency (UHF) range that are fully integrated on CMOS-grade (resistivity=10-20 ohm.cm) silicon. Filters, which are designed in the Elliptic and coupled-resonator configuration, are electrostatically tuned using tunable microelectromechanical (MEM) capacitors with laterally movable interdigitated fingers. Tunable filters and high-quality factor (Q) integrated passives are made in silver (Ag), which has the highest conductivity of all materials in nature, to reduce the ohmic loss. The loss of the silicon substrate is eliminated by using micromachining techniques. The combination of the highest-conductivity metal and a low-loss substrate significantly improves the performance of lumped components at radio frequencies (RF), resulting in an insertion loss of 6 dB for a tunable lumped bandpass filter at 1075 MHz with a 3 dB-bandwidth of 63 MHz and tuning range of 123 MHz. The bandpass filters are encapsulated at the wafer level using a low-temperature, thermally released, polymer packaging process. This thesis details the design, fabrication, and measurement results of the filters and provides strategies to improve their performance. The performance of filter components, including the tunable capacitors and inductors, is characterized and compared to the state-of-the-art micromachined passive components. The silver inductors reported in this thesis exhibit the record high Q, and the silver bandpass filters show the minimum insertion loss that has been achieved on a CMOS-grade silicon substrate, to the best of our knowledge. Alternatively, tunable capacitors can be made in the bulk of silicon using a modified version of the high-aspect-ratio polysilicon and single crystal silicon (HARPSS) fabrication technique to obtain a larger capacitance density at the expense of a higher conductive loss. Using this process, a 15 pF two-port tunable capacitor is fabricated and tuned by 240% with the application of 3.5 V to the isolated actuator. Silver inductors can be post integrated with HARPSS tunable capacitors to obtain tunable filters in the very high frequency (VHF) range. The reported bandpass filters can be monolithically integrated with CMOS and have the potential to replace several transmit and receive acoustic filters currently used in cellular phones.

Geometric quality variables of wafers, such as BOW and WARP, are critical in their applications. A large variation of these quality variables reduces the number of conforming products in the downstream production. Therefore, it is important to reduce the variation by variation modeling, analysis and control for multistage wafer manufacturing processes (MWMPs). First, an intermediate feedforward control strategy is developed to adjust and update the control actions based on the online measurements of intermediate wafer quality measurements. The control performance is evaluated in a MWMP to transform ingots into polished wafers. However, in a complex multistage manufacturing process, the quality variables may have nonlinear relationship with the parameters of the predictors. In this case, piecewise linear regression tree (PLRT) models are used to address nonlinear relationships in MWMP to improve the model prediction performance. The obtained PLRT model is further reconfigured to be complied with the physical layout of the MWMP for feedforward control purposes. The procedure and effectiveness of the proposed method is shown in a case study of a MWMP. Furthermore, as the geometric profiles and quality variables are important quality features for a wafer, fast and accurate measurements of those features are crucial for variation reduction and feedforward control. A sequential measurement strategy is proposed to reduce the number of samples measured in a wafer, yet provide adequate accuracy for the quality feature estimation. A Gaussian process model is used to estimate the true profile of a wafer with improved sensing efficiency. Finally, we study the multistage multimode process monitoring problem. We propose to use PLRTs to inter-relate the variables in a multistage multimode process. A unified charting system is developed. We further study the run length distribution, and optimize the control chart system by considering the modeling uncertainties. Finally, we compare the proposed method with the risk adjustment type of control chart systems based on global regression models, for both simulation study and a wafer manufacturing process.

This thesis investigates the potential of wafer-scale integration (WSI) for the implementation of low-cost fine-grain parallel processing computer systems. As WSI is a relatively new subject, there was little work on which to base investigations. Indeed, most WSI architectures existed only as untried and sometimes vague proposals. Accordingly, the research strategy approached this problem by identifying a representative WSI structure and architecture on which to base investigations. An analysis of architectural proposals identified associative memory to be general purpose parallel processing component used in a wide range of WSI architectures. Furthermore, this analysis provided a set of WSI-level design requirements to evaluate the sustainability of different architectures as research vehicles. The WSI-ASP (WASP) device, which has a large associative memory as its main component is shown to meet these requirements and hence was chosen as the research vehicle. Consequently, this thesis addresses WSI potential through an in-depth investigation into the feasibility of implementing a large associative memory for the WASP device that meets the demanding technological constraints of WSI. Overall, the thesis concludes that WSI offers significant potential for the implementation of low-cost fine-grain parallel processing computer systems. However, due to the dual constraints of thermal management and the area required for the power distribution network, power density is a major design constraint in WSI. Indeed, it is shown that WSI power densities need to be an order of magnitude lower than VLSI power densities. The thesis demonstrates that for associative memories at least, VLSI designs are unsuited to implementation in WSI. Rather, it is shown that WSI circuits must be closely matched to the operational environment to assure suitable power densities. These circuits are significantly larger than their VLSI equivalents. Nonetheless, the thesis demonstrates that by concentrating on the most power intensive circuits, it is possible to achieve acceptable power densities with only a modest increase in area overheads.

Beim Aufbau von konfigurierbaren wafer-scale Systemen für pulsgekoppelte neuronale Netze werden hohe Anforderungen an die Kommunikation zwischen einzelnen Komponenten gestellt. Zur Unterstützung des Hardwareentwurfs, aber auch um die parallele Entwicklung der Software zu ermöglichen, können Simulationsmodelle verwendet werden. Der Aufbau der Architektur und die Implementierung als SystemC-Modell werden beschrieben. Aus der Simulation sind Rückschlüsse auf die Architektur möglich, es ergeben sich aber auch Anforderungen an die zu entwickelnde Softwareumgebung.

This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. In this dissertation, a fine-pitch ball-grid array (FBGA) package, a multichip module (MCM)-L package, and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared to those of inductors monolithically integrated on Si and GaAs substrates. All the inductors are modeled with a physical, simple, equivalent two-port model for the VCO design as well as for phase noise analysis. The losses in an LC-tank are analyzed from the phase noise perspective. For the implementation of VCOs, the effects of the interconnection between the embedded inductor and the VCO circuit are investigated. The VCO using the on-chip inductors is designed as a reference. The performance of VCOs using the embedded inductor in a FBGA and a WLP is compared with that of a VCO using the on-chip inductor. The VCO design is optimized from the high-Q perspective to enhance performance. Through this optimization, less phase noise, lower power consumption, and a wider frequency tuning range are obtained simultaneously.

4H-SiC-based bipolar junction transistors (BJTs) are attractive devices for high-voltage and high-temperature operations due to their high current capability, low specific on-resistance, and process simplicity. To extend the potential of SiC BJTs to power electronic industrial applications, it is essential to realize high-efficient devices with high-current and low-loss by a reliable and wafer-scale fabrication process. In this thesis, we focus on the improvement of the 4H-SiC BJT performance, including the device optimization and process development. To optimize the 4H-SiC BJT design, a comprehensive study in terms of cell geometries, device scaling, and device layout is performed. The hexagon-cell geometry shows 42% higher current density and 21% lower specific on-resistance at a given maximum current gain compared to the interdigitated finger design. Also, a layout design, called intertwined, is used for 100% usage of the conducting area. A higher current is achieved by saving the inactive portion of the conducting area. Different multi-step etched edge termination techniques with an efficiency of &gt;92% are realized. Regarding the process development, an improved surface passivation is used to reduce the surface recombination and improve the maximum current gain of 4H-SiC BJTs. Moreover, wafer-scale lift-off-free processes for the n- and p-Ohmic contact technologies to 4H-SiC are successfully developed. Both Ohmic metal technologies are based on a self-aligned Ni-silicide (Ni-SALICIDE) process. Regarding the device characterization, a maximum current gain of 40, a specific on-resistance of 20 mΩ·cm2, and a maximum breakdown voltage of 5.85 kV for the 4H-SiC BJTs are measured. By employing the enhanced surface passivation, a maximum current gain of 139 and a specific on-resistance of 579 mΩ·cm2 at the current density of 89 A/cm2 for the 15-kV class BJTs are obtained. Moreover, low-voltage 4H-SiC lateral BJTs and Darlington pair with output current of 1−15 A for high-temperature operations up to 500 °C were fabricated. This thesis focuses on the improvement of the 4H-SiC BJT performance in terms of the device optimization and process development for high-voltage and high-temperature applications. The epilayer design and the device structure and topology are optimized to realize high-efficient BJTs. Also, wafer-scale fabrication process steps are developed to enable realization of high-current devices for the real applications. / <p>QC 20170810</p>