<p>Direct semiconductor wafer bonding has emerged as a technology to meet the demand foradditional flexibility in materials integration. The applications are found in microelectronics, optoelectronics and micromechanics. For instance, wafer bonding is used to produce silicon-on-insulator (SOI) wafers. Wafer bonding is also interesting to use for combining dissimilar semiconductors, such as Si and InP, with different dictated optical, electronic and mechanicalproperties. This enables a completely new freedom in the design of components and systems, e.g. for high performance optoelectronic integrated circuits (OEIC). Although wafer bonding has proved to be a useful and versatile tool, the high temperature annealing that is needed to achieve reliable properties sometimes hampers its applicability. Therefore, low temperature wafer bonding procedures may further qualify this technology.</p><p>In the present thesis, low temperature wafer bonding procedures using oxygen plasma surface activation have been studied. A specially designed fixture was adopted enabling <i>in situ </i>oxygen plasma wafer bonding. Oxygen plasma surface activation was seen to indeed yield high Si-Si bonding-strength at low temperatures. Here, the optimisation of the plasma parameters was shown to be the key to improved results. Furthermore, dependence of wafer bonded Si p-n junctions on the annealing temperature was investigated. InP-to-Si wafer bonding is also presented within this thesis. High temperature annealing was seen to induce severe material degradation. However, using oxygen plasma assisted wafer bonding reliable InP-to-Si integration was achieved already at low temperature, thereby circumventing the problems associated with the lattice and thermal mismatch that exist between these materials. As a result, low temperature InP-based epitaxial-layer transferring to Si could be presented. Finally, high-quality SiO2 insulator on InP and Si was realised at low temperatures.</p><p>It is concluded that low temperature oxygen plasma assisted wafer bonding is an interesting approach to integrate dissimilar materials, for a wide range of applications.</p>

Direct wafer bonding has been identified as an en-abling technology for microelectromechanical systems (MEMS). As the complexity of devices increase and the bonding of multiple patterned wafers is required, there is a need to understand the factors that lead to bonding failure. Bonding relies on short-ranged surface forces, thus flatness deviations of the wafers may prevent bonding. Bonding success is determined by whether or not the surface forces are sufficient to overcome the flatness deviations and deform the wafers to a common shape. A general bonding criterion based on this fact is developed by comparing the strain energy required to deform the wafers to the surface energy that is dissipated as the bond is formed. The bonding criterion is used to examine the case of bonding bowed wafers with etch patterns on the bonding surface. An analytical expression for the bonding criterion is developed using plate theory for the case of bowed wafers. Then, the criterion is implemented using finite element analysis, to demonstrate its use and to validate the analytical model. The results indicate that wafer thickness and curvature are important in determining bonding success and that the bonding criterion is independent of wafer diameter. Results also demonstrate that shallow etched patterns can make bonding more difficult while deep features, which penetrate through an appreciable thickness of the wafer, may facilitate bonding. Design implications of the model results are discussed in detail. Preliminary results from experiments designed to validate the model, agree with the trends seen in the model, but further work is required to achieve quantitative correlation. / Singapore-MIT Alliance (SMA)

A research synopsis is presented summarizing work with integration of Ge and III-V semiconductors and optical devices with Si. III-V GaAs/AlGaAs quantum well lasers and GaAs/AlGaAs optical circuit structures have been fabricated on Si using Ge/GeSi/Si virtual substrates. The lasers fabricated on bulk GaAs showed similar output characteristics as those on Si. The GaAs/AlGaAs lasers fabricated on Si emitted at 858nm and had room temperature cw lifetimes of ~4hours. Straight optical links integrating an LED emitter, waveguide and detector exhibited losses of approximately 144dB/cm. A process for fabrication of a novel CMOS-compatible platform that integrates III-V or Ge layers with Si is demonstrated. Thin Ge layers have been transferred from Ge/GeSi/Si virtual substrates to bulk Si utilizing wafer bonding and an epitaxial Si CMP layer to facilitate virtual substrate planarization. A unique CMP-less method for removal of Ge exfoliation damage induced by the SmartCut™ process is also presented. / Singapore-MIT Alliance (SMA)

Direct semiconductor wafer bonding has emerged as a technology to meet the demand foradditional flexibility in materials integration. The applications are found in microelectronics, optoelectronics and micromechanics. For instance, wafer bonding is used to produce silicon-on-insulator (SOI) wafers. Wafer bonding is also interesting to use for combining dissimilar semiconductors, such as Si and InP, with different dictated optical, electronic and mechanicalproperties. This enables a completely new freedom in the design of components and systems, e.g. for high performance optoelectronic integrated circuits (OEIC). Although wafer bonding has proved to be a useful and versatile tool, the high temperature annealing that is needed to achieve reliable properties sometimes hampers its applicability. Therefore, low temperature wafer bonding procedures may further qualify this technology. In the present thesis, low temperature wafer bonding procedures using oxygen plasma surface activation have been studied. A specially designed fixture was adopted enabling in situ oxygen plasma wafer bonding. Oxygen plasma surface activation was seen to indeed yield high Si-Si bonding-strength at low temperatures. Here, the optimisation of the plasma parameters was shown to be the key to improved results. Furthermore, dependence of wafer bonded Si p-n junctions on the annealing temperature was investigated. InP-to-Si wafer bonding is also presented within this thesis. High temperature annealing was seen to induce severe material degradation. However, using oxygen plasma assisted wafer bonding reliable InP-to-Si integration was achieved already at low temperature, thereby circumventing the problems associated with the lattice and thermal mismatch that exist between these materials. As a result, low temperature InP-based epitaxial-layer transferring to Si could be presented. Finally, high-quality SiO2 insulator on InP and Si was realised at low temperatures. It is concluded that low temperature oxygen plasma assisted wafer bonding is an interesting approach to integrate dissimilar materials, for a wide range of applications.

In recent years there has been a huge increase in the growth of communication systems such as mobile phones, wireless local area networks (WLAN), satellite navigation and various other forms of wireless data communication that have made analogue frequency control a key issue. The increase in frequency spectrum crowding and the increase of frequency into microwave region, along with the need for minimisation and capacity improvement, has shown the need for the development of high performance, miniature, on-chip filters operating in the low to medium GHz frequency range. This has hastened the need for alternatives to ceramic resonators due to their limits in device size and performance, which in turn, has led to development of the thin film electro-acoustics industry with surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters now fabricated in their millions. Further, this new technology opens the way for integrating the traditionally incompatible integrated circuit (IC) and electro-acoustic (EA) technologies, bringing about substantial economic and performance benefits. In this thesis the compatibility of aluminium nitride (AlN) to IC fabrication is explored as a means for furthering integration issues. Various issues have been explored where either tailoring thin film bulk acoustic resonator (FBAR) design, such as development of an improved solidly mounted resonator (SMR) technology, and use of IC technology, such as chemical mechanical polishing (CMP) or nickel silicide (NiSi), has made improvements beneficial for resonator fabrication or enabled IC integration. The former has resulted in major improvements to Quality factor, power handling and encapsulation respectively. The later has provided alternative methods to reduce electro- or acoustomigration, reduced device size, for plate waves, supplied novel low acoustic impedance material for high power applications and alternative electrodes for use in high temperature sensors. Another method to enhance integration by using the piezoelectric material, AlN, in the IC side has also been explored. Here methods for analysing AlN film contamination and stoichiometry have been used for analysis of AlN as a high-k dielectric material. This has even brought benefits in knowledge of film composition for use as a passivation material with SiC substrates, investigated in high power high frequency applications. Lastly AlN has been used as a buried insulator material for new silicon-on-insulator substrates (SOI) for increased heat conduction. These new substrates have been analysed with further development for improved performance indicated. / wisenet

<p>The visible light photon counter (VLPC) is a high quantum efficiency (QE), Si-based, single-photon detector with high gain, low-noise multiplication, low timing jitter, and photon number resolution. While the VLPC has high QE in the visible wavelengths, the QE in the ultraviolet and infrared is low due to minimal absorption within the active layers of the device. In the ultraviolet, the absorption coefficient of Si is high and most of the incident photons are absorbed within the top contact of the device, whereas, in the infrared, Si is practically transparent. A number of applications in quantum information science would benefit from use of the VLPC if the QE was improved in the ultraviolet (e.g., state detection of trapped ions) and the infrared (e.g., long-distance quantum cryptography). This thesis describes the development of the ultraviolet photon counter (UVPC) and the infrared photon counter (IRPC), which are modified versions of the VLPC with increased QE in the ultraviolet and infrared wavelengths, respectively. The UVPC has a transparent metal Schottky contact to reduce absorption within the top contact of the VLPC, resulting in an increase in the QE in the ultraviolet by several orders of magnitude. The IRPC is a proposed device that has an InGaAs absorption layer that is wafer-fusion bonded to the VLPC. The band alignment of the resulting InGaAs/Si heterojunction is measured and shows a large discontinuity in the valence band that impedes carrier transport at the interface. A ultra-high vacuum wafer-bonding system was developed to understand the impact of the surface chemistry of the bonded wafers on the band alignment of the InGaAs/Si heterojunction of the IRPC.</p> / Dissertation

In this thesis 10x10 reconfigurable reflectarray is designed at 26.5 GHz where the change in the progressive phase shift between elements is obtained with RF MEMS switches in the transmission lines of unit elements composed of aperture coupled microstrip patch antenna (ACMPA). The reflectarray is illuminated by a horn antenna, and the reflected beam is designed to switch between broadside and 40&deg / by considering the position of the horn antenna with respect to the reflectarray. In the design, the transmission line analysis is applied for matching the ACMPA to the free space. The full wave simulation techniques in HFSS are discussed to obtain the phase design curve which is used in determining two sets of transmission line lengths for each element, one for the broadside and the other for switching to the 40&deg / at 26.5 GHz. The switching between two sets of transmission line lengths is sustained by inserting RF MEMS switches into the transmission lines in each element. Two types of RF MEMS switches, series and shunt configurations, are designed for the switching purpose in the reflectarray. The phase errors due to nonideal phase design curve and type of the RF MEMS switch are reduced. The possible mutual coupling effects of the bias lines used to actuate the RF MEMS switches are also eliminated by the proper design. To show the validity of the design procedure, a prototype of 20x20 reflectarray composed of ACMPA elements is designed at 25GHz and produced using Printed Circuit Board (PCB) technology. The measurement results of the prototype reflectarray show that the main beam can be directed to the 40&deg / as desired. The process flow for the production of the reconfigurable reflectarray is suggested in terms of integration of the wafer bonding step with the in-house standard surface micromachined RF MEMS process.

With increasing amount of user data and applications in wireless communication technology, demands are growing on performance and fabrication costs. One way to decrease cost is to integrate the building blocks in an RF system where digital blocks and high power amplifiers then are combined on one chip. This thesis presents LDMOS transistors integrated in a 65 nm CMOS process without adding extra process steps or masks. High power performance of the LDMOS is demonstrated for an integrated WLAN-PA design at 2.45 GHz with 32.8 dBm output power and measurements also showed that high output power is achievable at 5.8 GHz. For the first time, this kind of device is moreover demonstrated at X-band with over 300 mW/mm output power, targeting communication and radar systems at 8 GHz. As SOI is increasing in popularity due to better device performance and RF benefits, the buried oxide can cause thermal problems, especially for high power devices. To deal with self-heating effects and decrease the RF substrate losses further, this thesis presents a hybrid substrate consisting of silicon on top of polycrystalline silicon carbide (Si-on-poly-SiC). This hybrid substrate utilizes the high thermal conductivity of poly-SiC to reduce device self-heating and the semi-insulating properties to reduce RF losses. Hybrid substrates were successfully fabricated for the first time in 150 mm wafer size by wafer bonding and evaluation was performed in terms of both electrical and thermal measurements and compared to a SOI reference. Successful LDMOS transistors were fabricated for the first time on this type of hybrid substrate where no degradation in electrical performance was seen comparing the LDMOS to identical transistors on the SOI reference. Measurements on calibrated resistors showed that the thermal conductivity was 2.5 times better for the hybrid substrate compared to the SOI substrate. Moreover, RF performance of the hybrid substrate was investigated and the semi-insulating property of poly-SiC showed to be beneficial in achieving a high equivalent substrate parallel resistance and thereby low substrate losses. In a transistor this would be equal to better efficiency and output power. In terms of integration, the hybrid substrate also opens up the possibility of heterogeneous integration where silicon devices and GaN devices can be fabricated on the same chip.

In this thesis, we are making a new approach to fabricate silicon on insulator (SOI). By replacing the buried silicon dioxide and the silicon handling wafer with silicon carbide through hydrophilic wafer bonding, we have achieved silicon on crystalline silicon carbide for the first time and silicon on polycrystalline silicon carbide substrates at 150 mm wafer size. The conditions for the wafer bonding are studied and the surface and bond interface are characterized. Stress free and interfacial defect free hybrid wafer bonding has been achieved. The thermally unfavourable interfacial oxide that originates from the hydrophilic treatment has been removed through high temperature annealing, denoted as Ox-away. Based on the experimental observations, a model to explain the dynamics of this process has been proposed. Ox-away together with spheroidization are found to be the responsible theories for the behaviour. The activation energy for this process is estimated as 6.4 eV. Wafer bonding of Si and polycrystalline SiC has been realised by an intermediate layer of amorphous Si. This layer recrystallizes to some extent during heat treatment. Electronic and thermal testing structures have been fabricated on the 150 mm silicon on polycrystalline silicon carbide hybrid substrate and on the SOI reference substrate. It is shown that our hybrid substrates have similar or improved electrical performance and 2.5 times better thermal conductivity than their SOI counterpart. 2D simulations together with the experimental measurements have been carried out to extract the thermal conductivity of polycrystalline silicon carbide as κpSiC = 2.7 WK-1cm-1. The realised Si-on-SiC hybrid wafer has been shown to be thermally and electrically superior to conventional SOI and opens up for hybrid integration of silicon and wide band gap material as SiC and GaN.

La microélectronique cherche à produire des composants toujours plus performants. Un axe d'amélioration est l'intégration de plus de fonctionnalités dans un volume toujours plus compact. L'approche planaire classiquement utilisée jusqu'à présent atteint ses limites. Une solution à ce défi technologique est l'intégration 3D permettant d'empiler verticalement plusieurs circuits. Les étapes d'assemblage sont cruciales dans ces schémas d'intégration. Parmi les différentes techniques d'assemblage, le collage direct de couches minces métalliques est une alternative très intéressante. En effet, elle offre simultanément un lien mécanique et électrique vertical entre les couches actives de composants.Les propriétés microstructurales, physiques et chimiques des couches minces métalliques déposées ont été largement rapportées dans l'état de l'art antérieur. Cependant, elles n'ont jamais été étudiées dans l'environnement particulier du collage. Le but de notre étude est d'évaluer l'impact de cet environnement sur les couches minces métalliques assemblées pendant et après le procédé d'assemblage.Le collage direct consiste en la mise en contact de surfaces lisses à température ambiante et sous atmosphère ambiant afin de créer une adhérence entre elles. Puisque le collage n'est pas réalisé sous vide, des espèces adsorbées sont piégées à l'interface et une couche d'oxyde natif limite l'obtention du contact métal-métal. L'environnement de collage nous pousse donc à considérer ces différentes espèces qui interfèrent avec le procédé de collage et l'établissement du contact électrique.Dans cette étude, nous avons assemblé différents métaux dans différentes configurations de couches minces. Ainsi, les couches d'oxyde surfaciques ont été désignées comme influentes sur le comportement en adhésion des assemblages. Dans le cas précis du collage direct Cu-Cu, la réaction de l'eau interfaciale est primordiale au renforcement de la tenue mécanique dès la température ambiante. À plus haute température, la dissolution de l'oxyde piégé et la croissance de grain verticale sont des moteurs du scellement dépendant de phénomènes diffusifs. Il est apparu que les joints de grains sont des chemins de diffusion privilégiés dont le rôle dans la microstructure est majeur. Il a également mis en évidence que les couches de métaux réfractaires ne pouvaient pas être assemblées en utilisant les mêmes forces motrices que les métaux de transition dans la gamme de température considérée. La compréhension des différents mécanismes apporte un éclairage nouveau dans l'utilisation du collage direct dans les schémas d'intégration des composants de demain. / The semiconductor industry is driven by an increasing need of computation speed and functionalities. In the development of next generation devices the integration of more functionalities in an ever smaller volume becomes paramount. So far, classical planar integration was privileged but it is currently reaching its limits. One solution to this technological challenge is to consider the 3D dimension as pathway of integration. To ensure the vertical stacking of circuits, the development and control of assembly processes becomes crucial. Among the different techniques under development, direct bonding of metal thin films is a promising solution. It is a straightforward option that offers both a mechanical and an electrical link between the active strata.Microstructural, physical and chemical properties of deposited metal thin films were widely reported in previous state of art. However, they have not yet been studied in the specific bonding environment. The main goal of our study is to pinpoint the impact of this environment during and after the process of assembly.Direct bonding process consists in putting into contact smooth surfaces at room temperature and ambient air which in appropriate conditions leads to the establishment of attractive forces. Since bonding is not operated under vacuum, adsorbed species are trapped at the interface and the metal bonding suffers from the formation of native oxide. The encapsulation of these species as well as the native metal oxide interfere with the bonding process and the establishment of an electrical contact.In this study, various bonded structures have been realized using an extended set of metals in different thin film configurations. Metal oxide layers impact is clearly highlighted via the monitoring of adhesion properties of the assemblies. In the Cu-Cu direct bonding case, the interfacial water reaction is primordial in the strengthening of bonding toughness at room temperature. At higher temperature, oxide dissolution and vertical grain growth are driving forces in the sealing of bonding interface. The microstructure play a role in all these phenomena since grain boundaries are favorite diffusion pathway in thin films. Considering the temperature limitation imposed by the integration, we also highlight that refractory metal thin films needs another bonding approach compared to the transient metals. The understanding of bonding mechanisms throws new light on the use of direct bonding process in the realization of future electrical components.