An curvature measurement technique was used to characterize the stress evolution during reaction of a Ni film and a silicon substrate to form nickel silicide. Stress changes were measured at each stage of the silicide growth. When the nickel films were subjected to long-time isothermal annealing, stresses that developed during silicide formation gradually relaxed. Fitting the experimental results with a kinetic model provides insight into the volumetric strain and relaxation behavior of the reacting film and the reaction product. / Singapore-MIT Alliance (SMA)

Este trabalho apresenta a fabricação e a caracterização elétrica de contatos Al/Ti/Ni(Pt)Si sobre junções rasas N+P com aproximadamente 0,2 ìm de profundidade, sendo que o monosiliceto de níquel foi formado a partir da estrutura Ni(30nm)/Pt(1,5nm)/Si. O comportamento elétrico dos diodos obtidos no melhor processo foi adequado, com as seguintes médias e desvios padrões: corrente reversa por unidade de área de 33,8nA/cm2 ±12,3 nA/cm2 e corrente reversa por unidade de perímetro de 654pA/cm ±229pA/cm para tensão reversa de -5V, a resistência reversa dos diodos quadrados de 268,9G? ±97,7G? e a resistência reversa dos diodos serpentinas de 35,5G? ±11,5G?, a tensão de início de condução resultou entre 0,55V e 0,56V, a resistência série em condução de 4,7? ±1,3?, fator de idealidade de 1,15 ±0,03, e corrente de saturação de 1,1x10-11A para diodos quadrados (300ìm x 300ìm). O menor valor de resistividade do filme de (Ni(Pt)Si) resultou 25ì?cm e a resistência de folha de 3,13 ?/? foram obtidas após a formação do mono-siliceto de níquel na temperatura de 600 ºC durante 120 segundos. As estruturas Kelvin apresentaram resistividade de contato de 15,0ì?.cm2 ±3,3ì?.cm2 e comportamento ôhmico estável para diversos níveis de corrente. Após uma extensa análise sobre modelagem de contato, foi elaborado um programa computacional desenvolvido em MATLAB, baseado em um método bem conhecido, isto é, uma malha de resistores tridimensional, que analisa os efeitos do fenômeno de concentração das linhas de corrente lateral no contato. Este programa foi aplicado em contatos com siliceto de níquel, onde foram observadas reduções de até 32% na resistividade real do contato. / This work presents the fabrication and electrical characterization of Al/Ti/Ni(Pt)Si contacts having the nickel monosilicide formed from Ni(30nm)/Pt(1.5nm)/Si structure on shallow N+P junctions with about 0.2 ìm of depth. The diodes? electrical behavior achieved at the best process was considered good, with the following average and standard deviations: area diode leakage current of 33.8nA/cm2 ±12.3nA/cm2 and periphery diode leakage current of 654pA/cm ±229pA/cm for reverse voltage of -5V, the square diode reverse resistance of 268.9G? ±97.7G? and serpentine diode reverse resistance of 35.5G? ±11.5G?, forwardbias voltage between 0.55V and 0.56V, forward series resistance of 4.7? ±1.3?, ideality factor of 1.15 ±0.03, and reverse saturation current of 1.1x10-11A for square diodes (300ìm x 300ìm). The lowest film resistivity value (Ni(Pt)Si) of 25ì?cm and sheet resistance of 3.13 ?/? were obtained for the formation of nickel monosilicide under temperature of 600ºC for 120 seconds. The cross-bridge Kelvin resistors presented contact resistivity of 15.0 ì?.cm2 ±3.3 ì?.cm2 and stable ohmic behavior for several electrical current levels. After extensive analysis about contact modeling, a computer program was elaborated in MATLAB, based on a well-known three-dimensional resistor network, which analyses the lateral current crowding effects on contact. This program was applied for contacts with nickel silicide, where a decrease up to 32% at the real contact resistivity was observed.

Este trabalho apresenta a fabricação e a caracterização elétrica de contatos Al/Ti/Ni(Pt)Si sobre junções rasas N+P com aproximadamente 0,2 ìm de profundidade, sendo que o monosiliceto de níquel foi formado a partir da estrutura Ni(30nm)/Pt(1,5nm)/Si. O comportamento elétrico dos diodos obtidos no melhor processo foi adequado, com as seguintes médias e desvios padrões: corrente reversa por unidade de área de 33,8nA/cm2 ±12,3 nA/cm2 e corrente reversa por unidade de perímetro de 654pA/cm ±229pA/cm para tensão reversa de -5V, a resistência reversa dos diodos quadrados de 268,9G? ±97,7G? e a resistência reversa dos diodos serpentinas de 35,5G? ±11,5G?, a tensão de início de condução resultou entre 0,55V e 0,56V, a resistência série em condução de 4,7? ±1,3?, fator de idealidade de 1,15 ±0,03, e corrente de saturação de 1,1x10-11A para diodos quadrados (300ìm x 300ìm). O menor valor de resistividade do filme de (Ni(Pt)Si) resultou 25ì?cm e a resistência de folha de 3,13 ?/? foram obtidas após a formação do mono-siliceto de níquel na temperatura de 600 ºC durante 120 segundos. As estruturas Kelvin apresentaram resistividade de contato de 15,0ì?.cm2 ±3,3ì?.cm2 e comportamento ôhmico estável para diversos níveis de corrente. Após uma extensa análise sobre modelagem de contato, foi elaborado um programa computacional desenvolvido em MATLAB, baseado em um método bem conhecido, isto é, uma malha de resistores tridimensional, que analisa os efeitos do fenômeno de concentração das linhas de corrente lateral no contato. Este programa foi aplicado em contatos com siliceto de níquel, onde foram observadas reduções de até 32% na resistividade real do contato. / This work presents the fabrication and electrical characterization of Al/Ti/Ni(Pt)Si contacts having the nickel monosilicide formed from Ni(30nm)/Pt(1.5nm)/Si structure on shallow N+P junctions with about 0.2 ìm of depth. The diodes? electrical behavior achieved at the best process was considered good, with the following average and standard deviations: area diode leakage current of 33.8nA/cm2 ±12.3nA/cm2 and periphery diode leakage current of 654pA/cm ±229pA/cm for reverse voltage of -5V, the square diode reverse resistance of 268.9G? ±97.7G? and serpentine diode reverse resistance of 35.5G? ±11.5G?, forwardbias voltage between 0.55V and 0.56V, forward series resistance of 4.7? ±1.3?, ideality factor of 1.15 ±0.03, and reverse saturation current of 1.1x10-11A for square diodes (300ìm x 300ìm). The lowest film resistivity value (Ni(Pt)Si) of 25ì?cm and sheet resistance of 3.13 ?/? were obtained for the formation of nickel monosilicide under temperature of 600ºC for 120 seconds. The cross-bridge Kelvin resistors presented contact resistivity of 15.0 ì?.cm2 ±3.3 ì?.cm2 and stable ohmic behavior for several electrical current levels. After extensive analysis about contact modeling, a computer program was elaborated in MATLAB, based on a well-known three-dimensional resistor network, which analyses the lateral current crowding effects on contact. This program was applied for contacts with nickel silicide, where a decrease up to 32% at the real contact resistivity was observed.

In recent years there has been a huge increase in the growth of communication systems such as mobile phones, wireless local area networks (WLAN), satellite navigation and various other forms of wireless data communication that have made analogue frequency control a key issue. The increase in frequency spectrum crowding and the increase of frequency into microwave region, along with the need for minimisation and capacity improvement, has shown the need for the development of high performance, miniature, on-chip filters operating in the low to medium GHz frequency range. This has hastened the need for alternatives to ceramic resonators due to their limits in device size and performance, which in turn, has led to development of the thin film electro-acoustics industry with surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters now fabricated in their millions. Further, this new technology opens the way for integrating the traditionally incompatible integrated circuit (IC) and electro-acoustic (EA) technologies, bringing about substantial economic and performance benefits. In this thesis the compatibility of aluminium nitride (AlN) to IC fabrication is explored as a means for furthering integration issues. Various issues have been explored where either tailoring thin film bulk acoustic resonator (FBAR) design, such as development of an improved solidly mounted resonator (SMR) technology, and use of IC technology, such as chemical mechanical polishing (CMP) or nickel silicide (NiSi), has made improvements beneficial for resonator fabrication or enabled IC integration. The former has resulted in major improvements to Quality factor, power handling and encapsulation respectively. The later has provided alternative methods to reduce electro- or acoustomigration, reduced device size, for plate waves, supplied novel low acoustic impedance material for high power applications and alternative electrodes for use in high temperature sensors. Another method to enhance integration by using the piezoelectric material, AlN, in the IC side has also been explored. Here methods for analysing AlN film contamination and stoichiometry have been used for analysis of AlN as a high-k dielectric material. This has even brought benefits in knowledge of film composition for use as a passivation material with SiC substrates, investigated in high power high frequency applications. Lastly AlN has been used as a buried insulator material for new silicon-on-insulator substrates (SOI) for increased heat conduction. These new substrates have been analysed with further development for improved performance indicated. / wisenet

abstract: Nickel-Copper metallization for silicon solar cells offers a cost effective alternative to traditional screen printed silver paste technology. The main objective of this work is to study the formation of nickel silicide contacts with and without native silicon dioxide SiO2. The effect of native SiO2 on the silicide formation has been studied using Raman spectroscopy, Rutherford backscattering spectrometry and sheet resistance measurements which shows that SiO 2 acts as a diffusion barrier for silicidation at low temperatures of 350°C. At 400°C the presence of SiO2 results in the increased formation of nickel mono-silicide phase with reduced thickness when compared to samples without any native oxide. Pre and post-anneal measurements of Suns Voc, photoluminescence and Illuminated lock in thermography show effect of annealing on electrical characteristics of the device. The presence of native oxide is found to prevent degradation of the solar cells when compared to cells without any native oxide. A process flow for fabricating silicon solar cells using light induced plating of nickel and copper with and without native oxide (SiO2) has been developed and cell results for devices fabricated on 156mm wafers have been discussed. / Dissertation/Thesis / Masters Thesis Materials Science and Engineering 2016

A highly resolving micro-light beam-induced current (µLBIC)-system is presented in this work. Based on the laser excitation via an optical microscope, current values can be measured with sub-micron precision. We show, that this non-destructive, light-based approach delivers superior results to a reference electron microscope based electron beam induced current method concerning contrast and robustness towards reflection differences, whereas no vacuum is needed, no charging effects can occur and equal resolution is achieved. µLBIC allows therefore mapping of pn-junctions at silicon solar cell cross sections. By combination of µLBIC with other measurement methods in the same setup, such as micro-Raman spectroscopy, complementary microscopic information about material stress or crystallinity and electronic properties at the same region of interest on the sample is revealed. By applying µLBIC for analyzing silicon solar cross sections, two characterization examples of current technological relevance are presented: enhanced dopant diffusion along grain boundaries between grains with different orientations is quantified and the impact of a nickel silicide spike on local charge collection quality is studied.

Our society demands for increasingly powerful and efficient microprocessors. However, the conventional method to achieve this, i.e. by reducing the device dimensions and operation voltage of field-effect transistors (FETs), is approaching physical limits. This state of things is driving science and industry to consider new approaches for the generation of efficient logic devices. An emerging solution is the use of reconfigurable FETs (RFETs) that – unlike conventional CMOS transistors – do not need doping but can be toggled between p- and n-type behavior in runtime. For this to be possible, it is necessary to employ an intrinsic channel with Schottky junctions at source and drain. A program gate then toggles the polarity of the device at the Schottky junction on the drain side while one or more additional control gates switch the transistor on or off. This allows to create compact and delay-efficient logic gates that can switch their functionality dynamically, e.g. to save area or to prevent the disclosure of the circuit functionality. Additionally, the ability to include multiple gates in a single transistor to implement a wired-AND functionality allows to create power- and delay-efficient circuits. This thesis demonstrates that such devices can be created by means of a lithographic top-down technology based on commercial silicon-on-insulator (SOI) wafers. In order to ensure a compatibility with future CMOS process lines, the channels are created from silicon nanosheets and nanowires, which will most likely substitute the current FinFET and FD-SOI technology in the future. Nano-dimensional channels allow for ideal electrostatic control by the gates especially if the gates surround them. For this purpose, a process employing multiple oxide etching and oxidation steps, nickel silicide formation and the structuring of conformal metal gates is developed to create shrank and omega-gated nanosheets and nanowires with atomically sharp source and drain Schottky junctions. The resulting RFETs feature high on-current densities, high on/off current ratios and up to four individual gates that realize a wired-AND functionality. More importantly, in contrast to top-down fabricated RFETs in earlier works, these RFETs provide symmetrical electrical characteristics for p- and n-configuration but only need a single supply voltage. These properties will allow to create circuits of cascaded, static logic gates with polarity-independent signal delay times and no need for interposed buffers to refresh the signals. Additionally, the use of ferroelectric materials to create RFETs with nonvolatile programming has been tested at a Schottky-barrier MOSFET. Unfortunately, contact fabrication by self-aligned silicidation can lead to some difficulties: The silicide intrusion length varies widely even between similar nanowires on the same chip, which makes the fabrication of short channels and the application of narrow gates particularly challenging. Detailed analyses in this work show that the variation is mainly caused by the variable amount of nickel supplied. Several material-, temperature- and geometry-based methods to gain a more homogeneous silicidation length are tested. One of these methods employs the layout freedom of the top-down technology to create novel structures of nanowires with local volume extensions. When using a single nickel source, these structures allow to study the impact of wire geometry on silicidation dynamics independently from the nickel contact quality. The gained findings have implications well beyond the application in RFETs, as nickel silicidation is widely used in state-of-the-art semiconductor technology.:Abstract Kurzzusammenfassung 1 Introduction 2 Fundamentals and state-of-the-art of reconfigurable field-effect transistors 2.1 Schottky junction 2.2 Schottky-barrier field-effect transistor 2.3 Current control by the gate voltage 2.4 Reconfigurable FETs 2.4.1 Working principle 2.4.2 Architectures and channel materials of RFETs in prior works 2.4.3 Applications 2.4.4 Requirements for the use in circuits 3 Transistor fabrication 3.1 Electron-beam lithography 3.2 Top-down nanowire fabrication 3.3 Nanowire oxidation and underetch 3.3.1 Oxidation of nanowires 3.3.2 Oxidation processes 3.4 Top-gate fabrication 3.4.1 Basic process for tri-gate 3.4.2 Advanced process for omega-gate 3.4.3 Integration of ferroelectric hafnium-zirconium oxide 3.5 Contact formation by nickel silicidation 3.5.1 Contact metal selection 3.5.2 Nickel deposition and silicide formation 3.5.3 Influences on nickel silicidation in nanowires 3.5.3.1 General 3.5.3.2 Silicide and void formation in different nanowire orientations 3.5.3.3 Influence of nanowire width on silicidation length 3.5.3.4 Importance of an oxide shell 3.5.3.5 Titanium interlayer and exhaustible nickel source 3.5.3.6 Influence of the contact to the nickel supply 3.5.3.7 Effect of temperature on silicidation length homogeneity 3.6 Gate-first and gate-last approach 3.7 RFET circuit realization 3.7.1 Logic gate layout 3.7.2 Mix-and-match technology 4 Nickel silicidation in extended wire geometries 4.1 Silicidation into areas 4.2 Control of silicide growth regime by extensions to nanowires 4.3 Polder extensions for controlled silicidation lengths 4.3.1 Concept and model 4.3.2 Experimental verification 5 Transistor characteristics 5.1 Measurement setup 5.2 Single gate Schottky-barrier MOSFET 5.2.1 Back-gate control 5.2.2 Single top-gate control 5.3 Double top-gate RFET 5.3.1 Tri-gate architecture by gate-last fabrication 5.3.2 Omega-gate architecture by gate-first fabrication 5.4 Multiple independent top-gate RFET 5.4.1 Value of multiple independent gates 5.4.2 Single channel MIG-RFET 5.4.3 Multiple channel MIG-RFET 5.5 Towards nonvolatile RFETs using ferroelectric gate dielectric 5.5.1 Fundamentals and applications of ferroelectric materials in FETs 5.5.2 Schottky-barrier MOSFET with ferroelectric gate 5.6 Performance comparison to state-of-the-art RFETs 6 Conclusion 7 Outlook 7.1 Enhanced understanding, performance and yield of RFETs 7.2 RFETs with split channels 7.3 Silicidation control 8 Appendix 8.1 Analysis of unsuccessful silicidation on circuit chips Bibliography Own publications List of constants and symbols List of abbreviations Acknowledgments Curriculum Vitae / Unsere Gesellschaft verlangt nach immer leistungsfähigeren und effizienteren Mikroprozessoren. Die herkömmlichen Methoden, d.h. das Reduzieren der Bauelementabmessungen und der Betriebsspannung von Feldeffekttransistoren (FETs), nähern sich jedoch physikalischen Grenzen. Diese Tatsache veranlasst Forschung und Industrie dazu, neue Ansätze bei der Erzeugung von effizienten logischen Schaltkreisen zu verfolgen. Auf großes Interesse stößt dabei die Verwendung von rekonfigurierbaren Feldeffekttransistoren (RFETs), die im Gegensatz zu herkömmlichen FETs keine Dotierung benötigen, sondern jederzeit zwischen p- und n-Typ Verhalten umgeschaltet werden können. Dazu wird ein intrinsischer Kanal mit Schottky-Kontakten an den Drain- und Source-Anschlüssen benötigt. Außerdem wird ein Programmier-Gate verwendet um die Polarität des Bauelements festzulegen, und ein oder mehrere weitere Kontroll-Gates schalten den Transistor ein oder aus. Dies ermöglicht es kompakte und laufzeiteffiziente Logikgatter zu konstruieren, die ihrer Funktionalität dynamisch verändern können, zum Beispiel um den Flächenverbrauch zu reduzieren oder um eine Enthüllung der Schaltkreisfunktionalität zu verhindern. Außerdem können in einem einzelnen Transistor mehrere Gates angelegt werden. Die sich ergebende nicht-komplementäre UND-Verkettung kann dazu genutzt werden, um energie- und laufzeit-sparende Schaltkreise zu generieren. Diese Arbeit weist nach, dass solche Bauelemente mit einem lithographischen Top-Down-Ansatz auf Basis von kommerziellen Silizium-auf-Isolator Substraten (sog. SOI-Wafern) realisierbar sind. Um eine Kompatibilität mit zukünftigen CMOS-Prozesslinien sicherzustellen, wurden die Kanäle aus nanometer-dünnen Silizium-Drähten oder -Bändern gebildet. Es wird erwartet, dass solche Kanalgeometrien bald die heutigen FinFET und FD-SOI Technologien ablösen werden, weil sie insbesondere mit umschließendem Gate eine optimale elektrostatische Gate-Kontrolle über den Kanal aufweisen. Der in dieser Arbeit entwickelte Prozess umfasst daher mehrfache Oxid-Ätzungen und Oxidationen zur Schrumpfung und teilweisen Unterätzung der Kanäle, die Bildung von abrupten Schottky-Kontakten aus Nickel-Silizid und die Strukturierung umschließender Metall-Gates. Die erzeugten RFETs weisen besonders hohe Stromdichten im An-Zustand und sehr hohe Verhältnisse von An- zu Aus-Strom auf. Außerdem besitzen sie bis zu vier unabhängige Gates, deren Eingänge somit quasi UND-verknüpft sind. Vor allem aber weisen diese RFETs im Gegensatz zu vorangegangenen Arbeiten symmetrische elektrische Charakteristiken für p- und n-Konfiguration auf, wozu sie sogar nicht mehr als eine Betriebsspannung benötigen. Diese Eigenschaften ermöglichen die Erzeugung von Schaltkreisen aus verkoppelten Logikgattern, bei denen die Signal-Laufzeit nicht von der Polarität der Transistoren abhängt und bei denen die Signale nicht durch zwischengeschaltete Pufferschaltungen aufgefrischt werden müssen. Darüber hinaus wurde in einem Schottky-Barrieren FET die Verwendung ferroelektrischer Materialien erprobt, mit denen zukünftig RFETs mit nichtflüchtiger Programmierung erzeugt werden könnten. Leider bereitet die Kontaktbildung durch die selbst-ausgerichtete Silizidierung häufig Probleme: Die Silizid-Eindringlänge schwankt stark, selbst zwischen ähnlichen Nanodrähten auf demselben Chip, was die Herstellung kurzer Kanäle und die Verwendung schmaler Gates besonders erschwert. Detaillierte Analysen in dieser Arbeit zeigen, dass insbesondere der ungleiche Nachschub von Nickel diese Varianz verursacht. Verschiedene material-, temperatur- und geometrie-basierte Ansätze wurden getestet um homogenere Silizid-Eindringlängen zu erreichen. Einer dieser Ansätze macht sich zunutze, dass mit der Top-Down-Technologie beliebige Strukturen definiert werden können, sodass Nanodrähte lokal erweitert werden können. Wenn solche Strukturen mit nur einer einzelnen Nickelquelle verbunden sind, kann der Einfluss der Drahtgeometrie auf den Silizidierungsprozess unabhängig von der Güte des Nickel-Kontakts beobachtet werden. Die auf diese Weise gewonnenen Erkenntnisse sind über die Arbeit an RFETs hinaus von Relevanz, da die Nickel-Silizidierung in vielen modernen Halbleiterprozessen zum Einsatz kommt.:Abstract Kurzzusammenfassung 1 Introduction 2 Fundamentals and state-of-the-art of reconfigurable field-effect transistors 2.1 Schottky junction 2.2 Schottky-barrier field-effect transistor 2.3 Current control by the gate voltage 2.4 Reconfigurable FETs 2.4.1 Working principle 2.4.2 Architectures and channel materials of RFETs in prior works 2.4.3 Applications 2.4.4 Requirements for the use in circuits 3 Transistor fabrication 3.1 Electron-beam lithography 3.2 Top-down nanowire fabrication 3.3 Nanowire oxidation and underetch 3.3.1 Oxidation of nanowires 3.3.2 Oxidation processes 3.4 Top-gate fabrication 3.4.1 Basic process for tri-gate 3.4.2 Advanced process for omega-gate 3.4.3 Integration of ferroelectric hafnium-zirconium oxide 3.5 Contact formation by nickel silicidation 3.5.1 Contact metal selection 3.5.2 Nickel deposition and silicide formation 3.5.3 Influences on nickel silicidation in nanowires 3.5.3.1 General 3.5.3.2 Silicide and void formation in different nanowire orientations 3.5.3.3 Influence of nanowire width on silicidation length 3.5.3.4 Importance of an oxide shell 3.5.3.5 Titanium interlayer and exhaustible nickel source 3.5.3.6 Influence of the contact to the nickel supply 3.5.3.7 Effect of temperature on silicidation length homogeneity 3.6 Gate-first and gate-last approach 3.7 RFET circuit realization 3.7.1 Logic gate layout 3.7.2 Mix-and-match technology 4 Nickel silicidation in extended wire geometries 4.1 Silicidation into areas 4.2 Control of silicide growth regime by extensions to nanowires 4.3 Polder extensions for controlled silicidation lengths 4.3.1 Concept and model 4.3.2 Experimental verification 5 Transistor characteristics 5.1 Measurement setup 5.2 Single gate Schottky-barrier MOSFET 5.2.1 Back-gate control 5.2.2 Single top-gate control 5.3 Double top-gate RFET 5.3.1 Tri-gate architecture by gate-last fabrication 5.3.2 Omega-gate architecture by gate-first fabrication 5.4 Multiple independent top-gate RFET 5.4.1 Value of multiple independent gates 5.4.2 Single channel MIG-RFET 5.4.3 Multiple channel MIG-RFET 5.5 Towards nonvolatile RFETs using ferroelectric gate dielectric 5.5.1 Fundamentals and applications of ferroelectric materials in FETs 5.5.2 Schottky-barrier MOSFET with ferroelectric gate 5.6 Performance comparison to state-of-the-art RFETs 6 Conclusion 7 Outlook 7.1 Enhanced understanding, performance and yield of RFETs 7.2 RFETs with split channels 7.3 Silicidation control 8 Appendix 8.1 Analysis of unsuccessful silicidation on circuit chips Bibliography Own publications List of constants and symbols List of abbreviations Acknowledgments Curriculum Vitae

SiGe is a significant enabling technology for therealization of integrated circuits used in high performanceoptical networks and radio frequency applications. In order tocontinue to fulfill the demands for these applications, newmaterials and device structures are needed. This thesis focuseson new materials and their integration into heterojunctionbipolar transistor (HBT) structures as well as using devicesimulations to optimize and better understand the deviceoperation. Specifically, a SiGeC HBT platform was designed,fabricated, and electrically characterized. The platformfeatures a non-selectively grown epitaxial SiGeC base,in situdoped polysilicon emitter, nickel silicide,LOCOS isolation, and a minimum emitter width of 0.4 μm.Alternately, a selective epitaxy growth in an oxide window wasused to form the collector and isolation regions. Thetransistors exhibited cutoff frequency (fT) and maximum frequency of oscillation (fMAX) of 40-80 GHz and 15-45 GHz, respectively.Lateral design rules allowed the investigation of behavior suchas transient enhanced diffusion, leakage current, and theinfluence of parasitics such as base resistance and CBC. The formation of nickel silicide on polysiliconSiGe and SiGeC films was also investigated. The formation ofthe low resistivity monosilicide phase was shown to occur athigher temperatures on SiGeC than on SiGe. The stability of themonosilicide was also shown to improve for SiGeC. Nickelsilicide was then integrated into a SiGeC HBT featuring aselectively grown collector. A novel, fully silicided extrinsicbase contact was demonstrated along with the simultaneousformation of NiSi on thein situdoped polysilicon emitter. High-resolution x-ray diffraction (HRXRD) was used toinvestigate the growth and stability of SiGeC base layers forHBT integration. HRXRD proved to be an effective, fast,non-destructive tool for monitoring carbon out-diffusion due tothe dopant activation anneal for different temperatures as wellas for inline process monitoring of epitaxial growth of SiGeClayers. The stability of the SiGe layer with 0.2-0.4 at% carbonwhen subjected to dopant activation anneals ranging from1020-1100&#176C was analyzed by reciprocal lattice mapping.It was found that as the substitutional carbon increases theformation of boron clusters due to diffusion is suppressed, buta higher density of carbon clusters is formed. Device simulations were performed to optimize the DC and HFperformance of an advanced SiGeC HBT structure with low baseresistance and small dimension emitter widths. The selectivelyimplanted collector (SIC) was studied using a design ofexperiments (DOE) method. For small dimensions the lateralimplantation straggle has a significant influence on the SICprofile (width). A significant influence of the SIC width onthe DC gain was observed. The optimized structure showedbalanced fT/fMAXvalues of 200+ GHz. Finally, SOI BJT transistorswith deep trench isolation were fabricated in a 0.25μmBiCMOS process and self-heating effects were characterized andcompared to transistors on bulk silicon featuring deep trenchand shallow trench isolation. Device simulations based on SEMcross-sections and SIMS data were performed and the resultscompared to the fabricated transistors. Key words:Silicon-Germanium(SiGe), SiGeC,heterojunction bipolar transistor(HBT), nickel silicide,selectively implanted collector(SIC), device simulation, SiGeClayer stability, high resolution x-ray diffraction(HRXRD),silicon-on-insulator(SOI), self-heating.

<p>SiGe is a significant enabling technology for therealization of integrated circuits used in high performanceoptical networks and radio frequency applications. In order tocontinue to fulfill the demands for these applications, newmaterials and device structures are needed. This thesis focuseson new materials and their integration into heterojunctionbipolar transistor (HBT) structures as well as using devicesimulations to optimize and better understand the deviceoperation. Specifically, a SiGeC HBT platform was designed,fabricated, and electrically characterized. The platformfeatures a non-selectively grown epitaxial SiGeC base,<i>in situ</i>doped polysilicon emitter, nickel silicide,LOCOS isolation, and a minimum emitter width of 0.4 μm.Alternately, a selective epitaxy growth in an oxide window wasused to form the collector and isolation regions. Thetransistors exhibited cutoff frequency (f_T) and maximum frequency of oscillation (f_MAX) of 40-80 GHz and 15-45 GHz, respectively.Lateral design rules allowed the investigation of behavior suchas transient enhanced diffusion, leakage current, and theinfluence of parasitics such as base resistance and C_BC. The formation of nickel silicide on polysiliconSiGe and SiGeC films was also investigated. The formation ofthe low resistivity monosilicide phase was shown to occur athigher temperatures on SiGeC than on SiGe. The stability of themonosilicide was also shown to improve for SiGeC. Nickelsilicide was then integrated into a SiGeC HBT featuring aselectively grown collector. A novel, fully silicided extrinsicbase contact was demonstrated along with the simultaneousformation of NiSi on the<i>in situ</i>doped polysilicon emitter.</p><p>High-resolution x-ray diffraction (HRXRD) was used toinvestigate the growth and stability of SiGeC base layers forHBT integration. HRXRD proved to be an effective, fast,non-destructive tool for monitoring carbon out-diffusion due tothe dopant activation anneal for different temperatures as wellas for inline process monitoring of epitaxial growth of SiGeClayers. The stability of the SiGe layer with 0.2-0.4 at% carbonwhen subjected to dopant activation anneals ranging from1020-1100&#176C was analyzed by reciprocal lattice mapping.It was found that as the substitutional carbon increases theformation of boron clusters due to diffusion is suppressed, buta higher density of carbon clusters is formed.</p><p>Device simulations were performed to optimize the DC and HFperformance of an advanced SiGeC HBT structure with low baseresistance and small dimension emitter widths. The selectivelyimplanted collector (SIC) was studied using a design ofexperiments (DOE) method. For small dimensions the lateralimplantation straggle has a significant influence on the SICprofile (width). A significant influence of the SIC width onthe DC gain was observed. The optimized structure showedbalanced f_T/f_MAXvalues of 200+ GHz. Finally, SOI BJT transistorswith deep trench isolation were fabricated in a 0.25μmBiCMOS process and self-heating effects were characterized andcompared to transistors on bulk silicon featuring deep trenchand shallow trench isolation. Device simulations based on SEMcross-sections and SIMS data were performed and the resultscompared to the fabricated transistors.</p><p><b>Key words:</b>Silicon-Germanium(SiGe), SiGeC,heterojunction bipolar transistor(HBT), nickel silicide,selectively implanted collector(SIC), device simulation, SiGeClayer stability, high resolution x-ray diffraction(HRXRD),silicon-on-insulator(SOI), self-heating.</p>

Die fortschreitenden Entwicklungen in der Mikro- und Nanotechnologie erfordern eine solide Unterstützung durch Simulationen. Numerische Bauelementesimulationen waren und sind dabei unerlässliche Werkzeuge, die jedoch zunehmend an ihre Grenzen kommen. So basieren sie auf Parametern, die für beliebige Atomanordnungen nicht verfügbar sind, und scheitern für stark verkleinerte Strukturen infolge zunehmender Relevanz von Quanteneffekten. Diese Arbeit behandelt den Transport in Siliziumnanodrähten sowie durch NiSi2-Si-Grenzflächen. Dichtefunktionaltheorie wird dabei verwendet, um die stabile Atomanordnung und alle für den elektronischen Transport relevanten quantenmechanischen Effekte zu beschreiben. Bei der Untersuchung der Nanodrähte liegt das Hauptaugenmerk auf der radialen Abhängigkeit der elektronischen Struktur sowie deren Änderung bei Variation des Durchmessers. Dabei zeigt sich, dass der Kern der Nanodrähte für den Ladungstransport bestimmend ist. Weiterhin kann ein Durchmesser von ungefähr 5 nm identifiziert werden, oberhalb dessen die Zustandsdichte im Nanodraht große Ähnlichkeiten mit jener des Silizium-Volumenkristalls aufweist und der Draht somit zunehmend mit Näherungen für den perfekt periodischen Kristall beschrieben werden kann. Der Fokus bei der Untersuchung der NiSi2-Si-Grenzflächen liegt auf der Symmetrie von Elektron- und Lochströmen im Tunnelregime, welche für die Entwicklung von rekonfigurierbaren Feldeffekttransistoren besondere Relevanz hat. Verschiedene NiSi2-Si-Grenzflächen und Verzerrungszustände werden dabei systematisch untersucht. Je nach Grenzfläche ist die Symmetrie dabei sehr unterschiedlich und zeigt auch ein sehr unterschiedliches Verhalten bei externer Verzerrung. Weiterhin werden grundlegende physikalische Größen mit Bezug zu NiSi2-Si-Grenzflächen betrachtet. So wird beispielsweise die Stabilität anhand von Grenzflächen-Energien ermittelt. Am stabilsten sind {111}-Grenzflächen, was deren bevorzugtes Auftreten in Experimenten erklärt. Weitere wichtige Größen, deren Verzerrungsabhängigkeit untersucht wird, sind die Schottky-Barrierenhöhe, die effektive Masse der Ladungsträger sowie die Austrittsarbeiten von NiSi2- und Si-Oberflächen. Ein Beitrag zur Modellentwicklung numerischer Bauelementesimulationen wird durch einen Vergleich zwischen den Ergebnissen von Dichtefunktionaltheorie-basierten Transportrechnungen und denen eines vereinfachten Models basierend auf der Wentzel-Kramers-Brillouin-Näherung geliefert. Diese Näherung ist Teil vieler numerischer Bauelementesimulatoren und erlaubt die Berechnung des Tunnelstroms basierend auf grundlegenden physikalischen Größen. Der Vergleich ermöglicht eine Evaluierung des vereinfachten Models, welches anschließend genutzt wird, um den Einfluss der grundlegenden physikalischen Größen auf den Tunneltransport zu untersuchen.:Index of Abbreviations 1. Introduction 2. Silicon Based Devices and Silicon Nanowires 2.1. Introduction 2.2. The Reconfigurable Field-effect Transistor 2.2.1. Design and Functionality 2.2.2. Fabrication 2.3. Overview Over Silicon Nanowires 2.3.1. Geometric Structure 2.3.2. Fabrication Techniques 2.3.3. Electronic Properties 3. Simulation Tools 3.1. Introduction 3.2. Electronic Structure Calculations 3.2.1. Introduction and Basis Functions 3.2.2. Density Functional Theory 3.2.3. Description of Exchange and Correlation Effects 3.2.4. Practical Aspects of Density Functional Theory 3.3. Electron Transport 3.3.1. Introduction 3.3.2. Scattering Theory 3.3.3. Wentzel-Kramers-Brillouin Approximation for a Triangular Barrier 3.3.4. Non-equilibrium Green’s Function Formalism A. Radially Resolved Electronic Structure and Charge Carrier Transport in Silicon Nanowires A.1. Introduction A.2. Model System A.3. Results and Discussion A.4. Summary and Conclusions A.5. Appendix A: Computational Details A.6. Appendix B: Supplementary Material A.6.1. Comparison of the Band Gap Between Relaxed and Unrelaxed SiNWs A.6.2. Band Structures for Some of the Calculated SiNWs A.6.3. Radially Resolved Density of States for Some of the Calculated SiNWs B. Electron Transport Through NiSi2-Si Contacts and Their Role in Reconfigurable Field-effect Transistors B.1. Introduction B.2. Model for Reconfigurable Field-effect Transistors B.2.1. Atomistic Quantum Transport Model to Describe Transport Across the Contact Interface B.2.2. Simplified Compact Model to Calculate the Device Characteristics B.3. Results and Discussion B.3.1. Characteristics of a Reconfigurable Field-effect Transistor B.3.2. Variation of the Crystal Orientations and Influence of the Schottky Barrier B.3.3. Comparison to Fabricated Reconfigurable Field-effect Transistors B.4. Summary and Conclusions B.5. Appendix: Supplementary Material B.5.1. Band Structure and Density of States of the Contact Metal B.5.2. Relaxation Procedure B.5.3. Total Transmission Through Multiple Barriers C. Formation and Crystallographic Orientation of NiSi2-Si Interfaces C.1. Introduction C.2. Fabrication and characterization methods C.3. Model System and Simulation Details C.4. Results and discussion C.4.1. Atomic structure of the interface C.4.2. Discussion of ways to modify the interface orientation C.5. Summary C.6. Appendix: Supplementary Material D. NiSi2-Si Interfaces Under Strain: From Bulk and Interface Properties to Tunneling Transport D.1. Introduction D.2. Model System and Simulation Approach D.3. Computational Details D.3.1. Electronic Structure Calculations (Geometry Relaxations) D.3.2. Electronic Structure Calculations (Electronic Structure) D.3.3. Device Calculations D.4. Tunneling Transport From First-principles Calculations D.4.1. Evaluation of the Current D.4.2. Isotropic Strain D.4.3. Anisotropic Strain D.5. Transport Related Properties and Effective Modeling Schemes D.5.1. Schottky Barrier Height D.5.2. Simplified Transport Model D.5.3. Models for the Schottky Barrier Height D.6. Summary and Conclusions D.7. Appendix: Supplementary Material D.7.1. Schottky Barriers of the {110} Interface Under Anisotropic Strain D.7.2. Silicon Band Structure, Electric Field, and Number of Transmission Channels D.7.3. k∥-resolved Material Properties D.7.4. Evaluation of the Work Functions and Electron Affinities D.7.5. Verification of the Work Function Calculation 4. Discussion 5. Ongoing Work and Possible Extensions 6. Summary Bibliography List of Figures List of Tables Acknowledgements Selbstständigkeitserklärung Curriculum Vitae Scientific Contributions / The ongoing developments in micro- and nanotechnologies require a profound support from simulations. Numerical device simulations were and still are essential tools to support the device development. However, they gradually reach their limits as they rely on parameters, which are not always available, and neglect quantum effects for small structures. This work addresses the transport in silicon nanowires and through NiSi2-Si interfaces. By using density functional theory, the atomic structure is considered, and all electron transport related quantum effects are taken into account. Silicon nanowires are investigated with special attention to their radially resolved electronic structure and the corresponding modifications when the silicon diameter is reduced. The charge transport occurs mostly in the nanowire core. A diameter of around 5 nm can be identified, above which the nanowire core exhibits a similar density of states as bulk silicon. Thus, bulk approximations become increasingly valid above this diameter. NiSi2-Si interfaces are studied with focus on the symmetry between electron and hole currents in the tunneling regime. The symmetry is especially relevant for the development of reconfigurable field-effect transistors. Different NiSi2-Si interfaces and strain states are studied systematically. The symmetry is found to be different between the interfaces. Changes of the symmetry upon external strain are also very interface dependent. Furthermore, fundamental physical properties related to NiSi2-Si interfaces are evaluated. The stability of the different interfaces is compared in terms of interface energies. {111} interfaces are most stable, which explains their preferred occurrence in experiments. Other properties, whose strain dependence is studied, include the Schottky barrier height, the effective mass of the carriers, and work functions. A contribution to the development of numerical device simulators will be given by comparing the results from density functional theory based transport calculations and a model based on the Wentzel-Kramers-Brillouin approximation. This approximation, which is often employed in numerical device simulators, offers a relation between interface properties and the tunneling transport. The comparison allows an evaluation of the simplified model, which is then used to investigate the relation between the fundamental physical properties and the tunneling transport.:Index of Abbreviations 1. Introduction 2. Silicon Based Devices and Silicon Nanowires 2.1. Introduction 2.2. The Reconfigurable Field-effect Transistor 2.2.1. Design and Functionality 2.2.2. Fabrication 2.3. Overview Over Silicon Nanowires 2.3.1. Geometric Structure 2.3.2. Fabrication Techniques 2.3.3. Electronic Properties 3. Simulation Tools 3.1. Introduction 3.2. Electronic Structure Calculations 3.2.1. Introduction and Basis Functions 3.2.2. Density Functional Theory 3.2.3. Description of Exchange and Correlation Effects 3.2.4. Practical Aspects of Density Functional Theory 3.3. Electron Transport 3.3.1. Introduction 3.3.2. Scattering Theory 3.3.3. Wentzel-Kramers-Brillouin Approximation for a Triangular Barrier 3.3.4. Non-equilibrium Green’s Function Formalism A. Radially Resolved Electronic Structure and Charge Carrier Transport in Silicon Nanowires A.1. Introduction A.2. Model System A.3. Results and Discussion A.4. Summary and Conclusions A.5. Appendix A: Computational Details A.6. Appendix B: Supplementary Material A.6.1. Comparison of the Band Gap Between Relaxed and Unrelaxed SiNWs A.6.2. Band Structures for Some of the Calculated SiNWs A.6.3. Radially Resolved Density of States for Some of the Calculated SiNWs B. Electron Transport Through NiSi2-Si Contacts and Their Role in Reconfigurable Field-effect Transistors B.1. Introduction B.2. Model for Reconfigurable Field-effect Transistors B.2.1. Atomistic Quantum Transport Model to Describe Transport Across the Contact Interface B.2.2. Simplified Compact Model to Calculate the Device Characteristics B.3. Results and Discussion B.3.1. Characteristics of a Reconfigurable Field-effect Transistor B.3.2. Variation of the Crystal Orientations and Influence of the Schottky Barrier B.3.3. Comparison to Fabricated Reconfigurable Field-effect Transistors B.4. Summary and Conclusions B.5. Appendix: Supplementary Material B.5.1. Band Structure and Density of States of the Contact Metal B.5.2. Relaxation Procedure B.5.3. Total Transmission Through Multiple Barriers C. Formation and Crystallographic Orientation of NiSi2-Si Interfaces C.1. Introduction C.2. Fabrication and characterization methods C.3. Model System and Simulation Details C.4. Results and discussion C.4.1. Atomic structure of the interface C.4.2. Discussion of ways to modify the interface orientation C.5. Summary C.6. Appendix: Supplementary Material D. NiSi2-Si Interfaces Under Strain: From Bulk and Interface Properties to Tunneling Transport D.1. Introduction D.2. Model System and Simulation Approach D.3. Computational Details D.3.1. Electronic Structure Calculations (Geometry Relaxations) D.3.2. Electronic Structure Calculations (Electronic Structure) D.3.3. Device Calculations D.4. Tunneling Transport From First-principles Calculations D.4.1. Evaluation of the Current D.4.2. Isotropic Strain D.4.3. Anisotropic Strain D.5. Transport Related Properties and Effective Modeling Schemes D.5.1. Schottky Barrier Height D.5.2. Simplified Transport Model D.5.3. Models for the Schottky Barrier Height D.6. Summary and Conclusions D.7. Appendix: Supplementary Material D.7.1. Schottky Barriers of the {110} Interface Under Anisotropic Strain D.7.2. Silicon Band Structure, Electric Field, and Number of Transmission Channels D.7.3. k∥-resolved Material Properties D.7.4. Evaluation of the Work Functions and Electron Affinities D.7.5. Verification of the Work Function Calculation 4. Discussion 5. Ongoing Work and Possible Extensions 6. Summary Bibliography List of Figures List of Tables Acknowledgements Selbstständigkeitserklärung Curriculum Vitae Scientific Contributions