Este trabalho apresenta a fabricação e a caracterização elétrica de contatos Al/Ti/Ni(Pt)Si sobre junções rasas N+P com aproximadamente 0,2 ìm de profundidade, sendo que o monosiliceto de níquel foi formado a partir da estrutura Ni(30nm)/Pt(1,5nm)/Si. O comportamento elétrico dos diodos obtidos no melhor processo foi adequado, com as seguintes médias e desvios padrões: corrente reversa por unidade de área de 33,8nA/cm2 ±12,3 nA/cm2 e corrente reversa por unidade de perímetro de 654pA/cm ±229pA/cm para tensão reversa de -5V, a resistência reversa dos diodos quadrados de 268,9G? ±97,7G? e a resistência reversa dos diodos serpentinas de 35,5G? ±11,5G?, a tensão de início de condução resultou entre 0,55V e 0,56V, a resistência série em condução de 4,7? ±1,3?, fator de idealidade de 1,15 ±0,03, e corrente de saturação de 1,1x10-11A para diodos quadrados (300ìm x 300ìm). O menor valor de resistividade do filme de (Ni(Pt)Si) resultou 25ì?cm e a resistência de folha de 3,13 ?/? foram obtidas após a formação do mono-siliceto de níquel na temperatura de 600 ºC durante 120 segundos. As estruturas Kelvin apresentaram resistividade de contato de 15,0ì?.cm2 ±3,3ì?.cm2 e comportamento ôhmico estável para diversos níveis de corrente. Após uma extensa análise sobre modelagem de contato, foi elaborado um programa computacional desenvolvido em MATLAB, baseado em um método bem conhecido, isto é, uma malha de resistores tridimensional, que analisa os efeitos do fenômeno de concentração das linhas de corrente lateral no contato. Este programa foi aplicado em contatos com siliceto de níquel, onde foram observadas reduções de até 32% na resistividade real do contato. / This work presents the fabrication and electrical characterization of Al/Ti/Ni(Pt)Si contacts having the nickel monosilicide formed from Ni(30nm)/Pt(1.5nm)/Si structure on shallow N+P junctions with about 0.2 ìm of depth. The diodes? electrical behavior achieved at the best process was considered good, with the following average and standard deviations: area diode leakage current of 33.8nA/cm2 ±12.3nA/cm2 and periphery diode leakage current of 654pA/cm ±229pA/cm for reverse voltage of -5V, the square diode reverse resistance of 268.9G? ±97.7G? and serpentine diode reverse resistance of 35.5G? ±11.5G?, forwardbias voltage between 0.55V and 0.56V, forward series resistance of 4.7? ±1.3?, ideality factor of 1.15 ±0.03, and reverse saturation current of 1.1x10-11A for square diodes (300ìm x 300ìm). The lowest film resistivity value (Ni(Pt)Si) of 25ì?cm and sheet resistance of 3.13 ?/? were obtained for the formation of nickel monosilicide under temperature of 600ºC for 120 seconds. The cross-bridge Kelvin resistors presented contact resistivity of 15.0 ì?.cm2 ±3.3 ì?.cm2 and stable ohmic behavior for several electrical current levels. After extensive analysis about contact modeling, a computer program was elaborated in MATLAB, based on a well-known three-dimensional resistor network, which analyses the lateral current crowding effects on contact. This program was applied for contacts with nickel silicide, where a decrease up to 32% at the real contact resistivity was observed.

Este trabalho apresenta a fabricação e a caracterização elétrica de contatos Al/Ti/Ni(Pt)Si sobre junções rasas N+P com aproximadamente 0,2 ìm de profundidade, sendo que o monosiliceto de níquel foi formado a partir da estrutura Ni(30nm)/Pt(1,5nm)/Si. O comportamento elétrico dos diodos obtidos no melhor processo foi adequado, com as seguintes médias e desvios padrões: corrente reversa por unidade de área de 33,8nA/cm2 ±12,3 nA/cm2 e corrente reversa por unidade de perímetro de 654pA/cm ±229pA/cm para tensão reversa de -5V, a resistência reversa dos diodos quadrados de 268,9G? ±97,7G? e a resistência reversa dos diodos serpentinas de 35,5G? ±11,5G?, a tensão de início de condução resultou entre 0,55V e 0,56V, a resistência série em condução de 4,7? ±1,3?, fator de idealidade de 1,15 ±0,03, e corrente de saturação de 1,1x10-11A para diodos quadrados (300ìm x 300ìm). O menor valor de resistividade do filme de (Ni(Pt)Si) resultou 25ì?cm e a resistência de folha de 3,13 ?/? foram obtidas após a formação do mono-siliceto de níquel na temperatura de 600 ºC durante 120 segundos. As estruturas Kelvin apresentaram resistividade de contato de 15,0ì?.cm2 ±3,3ì?.cm2 e comportamento ôhmico estável para diversos níveis de corrente. Após uma extensa análise sobre modelagem de contato, foi elaborado um programa computacional desenvolvido em MATLAB, baseado em um método bem conhecido, isto é, uma malha de resistores tridimensional, que analisa os efeitos do fenômeno de concentração das linhas de corrente lateral no contato. Este programa foi aplicado em contatos com siliceto de níquel, onde foram observadas reduções de até 32% na resistividade real do contato. / This work presents the fabrication and electrical characterization of Al/Ti/Ni(Pt)Si contacts having the nickel monosilicide formed from Ni(30nm)/Pt(1.5nm)/Si structure on shallow N+P junctions with about 0.2 ìm of depth. The diodes? electrical behavior achieved at the best process was considered good, with the following average and standard deviations: area diode leakage current of 33.8nA/cm2 ±12.3nA/cm2 and periphery diode leakage current of 654pA/cm ±229pA/cm for reverse voltage of -5V, the square diode reverse resistance of 268.9G? ±97.7G? and serpentine diode reverse resistance of 35.5G? ±11.5G?, forwardbias voltage between 0.55V and 0.56V, forward series resistance of 4.7? ±1.3?, ideality factor of 1.15 ±0.03, and reverse saturation current of 1.1x10-11A for square diodes (300ìm x 300ìm). The lowest film resistivity value (Ni(Pt)Si) of 25ì?cm and sheet resistance of 3.13 ?/? were obtained for the formation of nickel monosilicide under temperature of 600ºC for 120 seconds. The cross-bridge Kelvin resistors presented contact resistivity of 15.0 ì?.cm2 ±3.3 ì?.cm2 and stable ohmic behavior for several electrical current levels. After extensive analysis about contact modeling, a computer program was elaborated in MATLAB, based on a well-known three-dimensional resistor network, which analyses the lateral current crowding effects on contact. This program was applied for contacts with nickel silicide, where a decrease up to 32% at the real contact resistivity was observed.

Electrical contacts to devices which pose low resistance continue to be of interest as the dimensions of devices decrease and nanotechnology demands better means of creating electrical access. Continued improvement in the performance of ohmic contacts requires techniques to better characterise and quantify the performance of such contacts. In order to study and estimate the resistance of such contacts or the resistance posed by the interface(s) in such contacts, accurate test structures and evaluation techniques need to be used. The resistance posed by an interface is quantified using its specific contact resistivity (SCR), which is denoted using ƒâc (units: £[cm2). Cross Kelvin resistor (CKR) test structures have been used for the measurement of low values of SCR. A simplified approach to this problem of SCR evaluation (developed previously at RMIT University) using the CKR test structures with varying contact sizes was used and during this work was shown to be accurate for the estimation of low values (less than10-8 £[cm2) of SCR. The silicides of interest in this study were titanium silicide (TiSi2) and nickel silicide (NiSi). These thin films are known for their low resistivity and low barrier heights to both n-type and p-type silicon. The research involved thin film formation and substantial materials characterisation of these thin films. The silicide thin films were formed by vacuum annealing metal thin films on silicon substrates. Silicide thin films formed from metal films deposited by DC magnetron sputtering and electron beam evaporation were compared. The composition, crystallographic orientation, and morphology of these thin films were studied using spectroscopy (AES, SIMS, RBS, in situ Raman spectroscopy), diffraction (Bragg-Brentano and glancing angle XRD, RHEED), and microscopy techniques (TEM, SEM, and AFM). TiSi2 and NiSi thin films were also found to be suitable for microsystems fabrication due to their ability to withstand wet etching of silicon using potassium hydroxide. The SCR of aluminium-titanium silicide ohmic contacts was evaluated to be as low as 6 x 10-10 ƒÇcm2, which is the lowest reported for any two- layer single-interface contact. Characterisation of ohmic contacts comprising of aluminium, nickel silicide, and doped silicon (with shallow implants) were also carried out using the same technique. SCR values as low as 5.0 x 10-9 ƒÇcm2 for contacts to antimony-doped silicon and 3.5 x 10-9 £[cm2 to boron-doped silicon were evaluated.

Challenges with integrating high-κ gate dielectric,retrograde Si1-xGexchannel and silicided contacts in future CMOStechnologies are investigated experimentally and theoreticallyin this thesis. ρMOSFETs with either Si or strained Si1-xGex surface-channel and different high-κgate dielectric are examined. Si1-xGex ρMOSFETs with an Al2O3/HfAlOx/Al2O3nano-laminate gate dielectric prepared by means ofAtomic Layer Deposition (ALD) exhibit a great-than-30% increasein current drive and peak transconductance compared toreference Si ρMOSFETs with the same gate dielectric. Apoor high-κ/Si interface leading to carrier mobilitydegradation has often been reported in the literature, but thisdoes not seem to be the case for our Si ρMOSFETs whoseeffective mobility coincides with the universal hole mobilitycurve for Si. For the Si1-xGexρMOSFETs, however, a high density ofinterface states giving riseto reduced carrier mobility isobserved. A method to extract the correct mobility in thepresence of high-density traps is presented. Coulomb scatteringfrom the charged traps or trapped charges at the interface isfound to play a dominant role in the observed mobilitydegradation in the Si1-xGexρMOSFETs. Studying contacts with metal silicides constitutes a majorpart of this thesis. With the conventional device fabrication,the Si1-xGexincorporated for channel applications inevitablyextends to the source-drain areas. Measurement and modelingshow that the presence of Ge in the source/drain areaspositively affects the contact resistivity in such a way thatit is decreased by an order of magnitude for the contact of TiWto p-type Si1-xGex/Si when the Ge content is increased from 0 to 30at. %. Modeling and extraction of contact resistivity are firstcarried out for the traditional TiSi2-Si contact but with an emphasis on the influenceof a Nb interlayer for the silicide formation. Atwo-dimensional numerical model is employed to account foreffects due to current crowding. For more advanced contacts toultra-shallow junctions, Ni-based metallization scheme is used.NiSi1-xGex is found to form on selectively grown p-typeSi1-xGexused as low-resistivity source/drain. Since theformed NiSi1-xGex with a specific resistivity of 20 mWcmreplaces a significant fraction of the shallow junction, athree-dimensional numerical model is employed in order to takethe complex interface geometry and morphology into account. Thelowest contact resistivity obtained for our NiSi1-xGex/p-type Si1-xGexcontacts is 5´10-8Ωcm2, which satisfies the requirement for the 45-nmtechnology node in 2010. When the Si1-xGexchannel is incorporated in a MOSFET, it usuallyforms a retrograde channel with an undoped surface region on amoderately doped substrate. Charge sheet models are used tostudy the effects of a Si retrograde channel on surfacepotential, drain current, intrinsic charges and intrinsiccapacitances. Closed-form solutions are found for an abruptretrograde channel and results implicative for circuitdesigners are obtained. The model can be extended to include aSi1-xGexretrograde channel. Although the analytical modeldeveloped in this thesis is one-dimensional for long-channeltransistors with the retrograde channel profile varying alongthe depth of the transistor, it should also be applicable forshort-channel transistors provided that the short channeleffects are perfectly controlled. Key Words:MOSFET, SiGe, high-k dielectric, metal gate,mobility, charge sheet model, retrograde channel structure,intrinsic charge, intrinsic capacitance, contactresistivity.

The continuous and aggressive downscaling of conventional CMOS devices has been driving the vast growth of ICs over the last few decades. As the CMOS downscaling approaches the fundamental limits, novel device architectures such as metallic source/drain Schottky barrier MOSFET (SB-MOSFET) and SB-FinFET are probably needed to further push the ultimate downscaling. The ultimate goal of this thesis is to integrate metallic Ni1-xPtx silicide (x=0~1) source/drain into SB-MOSFET and SB-FinFET, with an emphasis on both material and processing issues related to the integration of Ni1-xPtx silicides towards competitive devices. First, the effects of both carbon (C) and nitrogen (N) on the formation and on the Schottky barrier height (SBH) of NiSi are studied. The presence of both C and N is found to improve the poor thermal stability of NiSi significantly. The present work also explores dopant segregation (DS) using B and As for the NiSi/Si contact system. The effects of C and N implantation into the Si substrate prior to the NiSi formation are examined, and it is found that the presence of C yields positive effects in helping reduce the effective SBH to 0.1-0.2 eV for both conduction polarities. In order to unveil the mechanism of SBH tuning by DS, the variation of specific contact resistivity between silicide and Si substrates by DS is monitored. The formation of a thin interfacial dipole layer at silicide/Si interface is confirmed to be the reason of SBH modification. Second, a systematic experimental study is performed for Ni1-xPtx silicide (x=0~1) films aiming at the integration into SB-MOSFET. A distinct behavior is found for the formation of Ni silicide films. Epitaxially aligned NiSi2-y films readily grow and exhibit extraordinary morphological stability up to 800 oC when the thickness of deposited Ni (tNi) <4 nm. Polycrystalline NiSi films form and tend to agglomerate at lower temperatures for thinner films for tNi≥4 nm. Such a distinct annealing behavior is absent for the formation of Pt silicide films with all thicknesses of deposited Pt. The addition of Pt into Ni supports the above observations. Surface energy is discussed as the cause responsible for the distinct behavior in phase formation and morphological stability. Finally, three different Ni-SALICIDE schemes towards a controllable NiSi-based metallic source/drain process without severe lateral encroachment of NiSi are carried out. All of them are found to be effective in controlling the lateral encroachment. Combined with DS technology, both n- and p-types of NiSi source/drain SB-MOSFETs with excellent performance are fabricated successfully. By using the reproducible sidewall transfer lithography (STL) technology developed at KTH, PtSi source/drain SB-FinFET is also realized in this thesis. With As DS, the characteristics of PtSi source/drain SB-FinFET are transformed from p-type to n-type. This thesis work places Ni1-xPtx (x=0~1) silicides SB-MOSFETs as a competitive candidate for future CMOS technology. / QC20100708 / NEMO, NANOSIL, SINANO

A new shallow junction formation process, based on selective silicon etching followed by selective growth of in situ B-doped SiGe, is presented. The approach is advantageous compared to conventional ion implantation followed by thermal activation, because perfectly abrupt, low resistivity junctions of arbitrary depth can be obtained. In B-doped SiGe layers, the active doping concentration can exceed the solid solubility in silicon because of strain compensation. In addition, the compressive strain induced in the Si channel can improve drivability through increased hole mobility. The process is integrated by performing the selective etching and the selective SiGe growth in the same reactor. The main advantage of this is that the delicate gate oxide is preserved. The silicon etching process (based on HCl) is shown to be highly selective over SiO2 and anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. It was found that the process temperature should be confined between 800 ºC, where etch pits occur, and 1000 ºC, where the masking oxide is attacked. B-doped SiGe layers with a resistivity of 5×10-4 Ωcm were obtained. Well-behaved pMOS transistors are presented, yet with low layer quality. Therefore integration issues related to the epitaxial growth, such as selectivity, loading effect, pile-up and defect generation, were investigated. Surface damage originating from reactive-ion etching of the sidewall spacer and nitride residues from LOCOS formation were found to degrade the quality of the SiGe layer. Various remedies are discussed. Nevertheless, high-quality selective epitaxial growth could not be achieved with a doping concentration in the 1021 cm-3 range. The maximum doping level resulting in a high-quality layer, with the loading effect taken into account, was 6×1020 cm-3. After this careful process optimization, a high-quality layer was obtained in the recessed areas. Finally, Ni mono-germanosilicide was investigated as a material for contact formation to the epitaxial SiGe layers in the recessed source and drain areas. The formation temperature is 550 ºC and it is stable up to 700 ºC. The observation of a recessed step and lateral growth of the silicide led to a detailed treatment of the contact resistivity of the NiSi0.8Ge0.2/Si0.8Ge0.2 interface using 2-D as well as 3-D modeling. Different values were obtained for square shaped and rounded contacts, 5.0x10-8 Ωcm2 and 1.4x10-7 Ωcm2, respectively. / QC 20101028

<p>Challenges with integrating high-κ gate dielectric,retrograde Si_1-xGe_xchannel and silicided contacts in future CMOStechnologies are investigated experimentally and theoreticallyin this thesis. ρMOSFETs with either Si or strained Si_1-xGex surface-channel and different high-κgate dielectric are examined. Si_1-xGex ρMOSFETs with an Al₂O₃/HfAlO_x/Al₂O₃nano-laminate gate dielectric prepared by means ofAtomic Layer Deposition (ALD) exhibit a great-than-30% increasein current drive and peak transconductance compared toreference Si ρMOSFETs with the same gate dielectric. Apoor high-κ/Si interface leading to carrier mobilitydegradation has often been reported in the literature, but thisdoes not seem to be the case for our Si ρMOSFETs whoseeffective mobility coincides with the universal hole mobilitycurve for Si. For the Si_1-xGe_xρMOSFETs, however, a high density ofinterface states giving riseto reduced carrier mobility isobserved. A method to extract the correct mobility in thepresence of high-density traps is presented. Coulomb scatteringfrom the charged traps or trapped charges at the interface isfound to play a dominant role in the observed mobilitydegradation in the Si_1-xGe_xρMOSFETs.</p><p>Studying contacts with metal silicides constitutes a majorpart of this thesis. With the conventional device fabrication,the Si_1-xGe_xincorporated for channel applications inevitablyextends to the source-drain areas. Measurement and modelingshow that the presence of Ge in the source/drain areaspositively affects the contact resistivity in such a way thatit is decreased by an order of magnitude for the contact of TiWto p-type Si_1-xGe_x/Si when the Ge content is increased from 0 to 30at. %. Modeling and extraction of contact resistivity are firstcarried out for the traditional TiSi₂-Si contact but with an emphasis on the influenceof a Nb interlayer for the silicide formation. Atwo-dimensional numerical model is employed to account foreffects due to current crowding. For more advanced contacts toultra-shallow junctions, Ni-based metallization scheme is used.NiSi_1-xGex is found to form on selectively grown p-typeSi_1-xGe_xused as low-resistivity source/drain. Since theformed NiSi1-xGex with a specific resistivity of 20 mWcmreplaces a significant fraction of the shallow junction, athree-dimensional numerical model is employed in order to takethe complex interface geometry and morphology into account. Thelowest contact resistivity obtained for our NiSi_1-xGe_x/p-type Si_1-xGe_xcontacts is 5´10^-8Ωcm², which satisfies the requirement for the 45-nmtechnology node in 2010.</p><p>When the Si_1-xGe_xchannel is incorporated in a MOSFET, it usuallyforms a retrograde channel with an undoped surface region on amoderately doped substrate. Charge sheet models are used tostudy the effects of a Si retrograde channel on surfacepotential, drain current, intrinsic charges and intrinsiccapacitances. Closed-form solutions are found for an abruptretrograde channel and results implicative for circuitdesigners are obtained. The model can be extended to include aSi_1-xGe_xretrograde channel. Although the analytical modeldeveloped in this thesis is one-dimensional for long-channeltransistors with the retrograde channel profile varying alongthe depth of the transistor, it should also be applicable forshort-channel transistors provided that the short channeleffects are perfectly controlled.</p><p><b>Key Words:</b>MOSFET, SiGe, high-k dielectric, metal gate,mobility, charge sheet model, retrograde channel structure,intrinsic charge, intrinsic capacitance, contactresistivity.</p>

<p>A new shallow junction formation process, based on selective silicon etching followed by selective growth of in situ B-doped SiGe, is presented. The approach is advantageous compared to conventional ion implantation followed by thermal activation, because perfectly abrupt, low resistivity junctions of arbitrary depth can be obtained. In B-doped SiGe layers, the active doping concentration can exceed the solid solubility in silicon because of strain compensation. In addition, the compressive strain induced in the Si channel can improve drivability through increased hole mobility. The process is integrated by performing the selective etching and the selective SiGe growth in the same reactor. The main advantage of this is that the delicate gate oxide is preserved. The silicon etching process (based on HCl) is shown to be highly selective over SiO₂ and anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. It was found that the process temperature should be confined between 800 ºC, where etch pits occur, and 1000 ºC, where the masking oxide is attacked. B-doped SiGe layers with a resistivity of 5×10-⁴ Ωcm were obtained. Well-behaved pMOS transistors are presented, yet with low layer quality. Therefore integration issues related to the epitaxial growth, such as selectivity, loading effect, pile-up and defect generation, were investigated. Surface damage originating from reactive-ion etching of the sidewall spacer and nitride residues from LOCOS formation were found to degrade the quality of the SiGe layer. Various remedies are discussed. Nevertheless, high-quality selective epitaxial growth could not be achieved with a doping concentration in the 1021 cm-3 range. The maximum doping level resulting in a high-quality layer, with the loading effect taken into account, was 6×10²⁰cm-³. After this careful process optimization, a high-quality layer was obtained in the recessed areas. Finally, Ni mono-germanosilicide was investigated as a material for contact formation to the epitaxial SiGe layers in the recessed source and drain areas. The formation temperature is 550 ºC and it is stable up to 700 ºC. The observation of a recessed step and lateral growth of the silicide led to a detailed treatment of the contact resistivity of the NiSi₀.₈Ge_0.2/Si_0.8Ge_0.2 interface using 2-D as well as 3-D modeling. Different values were obtained for square shaped and rounded contacts, 5.0x10^-8 Ωcm² and 1.4x10^-7 Ωcm², respectively.</p>

Avec l’avènement de l’internet des objets, la diversification des moyens de communication et l’augmentation de la puissance de calcul des processeurs, les besoins en termes d’échange de données n’ont cessé d’augmenter. Ces technologies nécessitent de combiner notamment sur un circuit intégré des fonctions optiques et RF réalisées à partir de matériaux III-V avec des fonctions logiques en silicium. Cependant en pré requis à la réalisation de ces dispositifs, il faut obtenir des couches de III-V sur des substrats de silicium avec une bonne qualité structurale et savoir former des contacts de type n et p avec une faible résistivité. L’objectif de cette thèse est d’intégrer sur silicium du GaAs car ce matériau est couramment employé dans fabrication d’émetteurs et de récepteurs pour les communications sans fils ainsi que dans la conception de LEDs et de lasers. Dans cette optique, ces travaux de thèse proposent donc d’étudier la croissance de GaAs sur des substrats de silicium de 300 mm par épitaxie en phase vapeur aux organométalliques et sur la formation de contacts n et p avec une faible résistivité sur ce même GaAs. En premier lieu, des études seront menées pour pouvoir s’affranchir des défauts générés durant la croissance du GaAs sur silicium (parois d’antiphase et dislocations émergentes). Par la suite, des caractérisations structurales (diffraction par rayons X, FIB STEM), morphologiques (AFM), électriques (effet hall) et optiques (photoluminescence) permettront de rendre compte de la qualité du matériau et de l’impact de ces défauts. Enfin, l’évolution des propriétés (optiques et de transport) du GaAs ainsi que la formation de contacts de type n et p avec une faible résistivité sera abordée. / With the emergence of Internet of Things (IoT), diversification of communication means and rise of processors’ computational power, the requirements in data exchange never stopped rising. These technologies need to combine on integrated circuits, optical and RF purposes fabricated from III-V compounds with silicon logical functions. However, as preliminary for the achievement of such devices, III-V semiconductors with good crystal quality have to be obtained on silicon substrates and formation of n & p type contacts with low resistivity is required. The purpose of this thesis is to integrate GaAs on silicon because this semiconductor is frequently used for the fabrication of emitters and receptors for wireless communication as well as in LEDs and lasers’ conception. With this is mind, this PhD work focuses on the growth of GaAs on 300 mm silicon substrates by metalorganic chemical vapour deposition and the formation of n & p type contacts with low contact resistivity on this GaAs. Firstly, efforts will put on the removal of the crystalline defects being the most prohibitive for the use of such materials: antiphase boundaries and threading dislocations. Then, structural (X-ray diffraction, FIB STEM), morphological (AFM), electrical (Hall Effect) and optical (photoluminescence) characterizations will highlight the quality of the epitaxial films. Finally, the evolution of GaAs properties (optical and transport) and the formation of n & p-type contacts with low resistivity will be discussed.

As scaling of CMOS technology continues, the control of parasitic source/drain (S/D) resistance (RSD) is becoming increasingly challenging. In order to control RSD, metallic source/drain MOSFETs have attracted significant attention, due to their low resistivity, abrupt junction and low temperature processing (≤700 °C). A key issue is reducing the contact resistance between metal and channel, since small Schottky barrier height (SBH) is needed to outperform doped S/D devices. A promising method to decrease the effective barrier height is dopant segregation (DS). In this work several relevant aspects of Schottky barrier (SB) contacts are investigated, both by simulation and experiment, with the goal of improving performance and understanding of SB-MOSFET technology:First, measurements of low contact resistivity are challenging, since systematic error correction is needed for extraction. In this thesis, a method is presented to determine the accuracy of extracted contact resistivity due to propagation of random measurement error.Second, using Schottky diodes, the effect of dopant segregation of beryllium (Be), bismuth (Bi), and tellurium (Te) on the SBH of NiSi is demonstrated. Further study of Be is used to analyze the mechanism of Schottky barrier lowering.Third, in order to fabricate short gate length MOSFETs, the sidewall transfer lithography process was optimized for achieving low sidewall roughness lines down to 15 nm. Ultra-thin-body (UTB) and tri-gate SB-MOSFET using PtSi S/D and As DS were demonstrated. A simulation study was conducted showing DS can be modeled by a combination of barrier lowering and doped Si extension.Finally, a new Schottky contact model was implemented in a multi-subband Monte Carlo simulator for the first time, and was used to compare doped-S/D to SB-S/D for a 17 nm gate length double gate MOSFET. The results show that a barrier of ≤ 0.15 eV is needed to comply with the specifications given by the International Technology Roadmap for Semiconductors (ITRS). / QC 20111206