abstract: In this work, a 12-bit ADC with three types of calibration is proposed for high speed security applications as well as a precision application. This converter performs for both applications because it satisfies all the necessary specifications such as minimal device mismatch and offset, programmability to decrease aging effects, high SNR for increased ENOB and fast conversion rate. The designed converter implements three types of calibration necessary for offset and gain error, including: a correlated double sampling integrator used in the first stage of the ADC, a power up auto zero technique implemented in the digital code to store any offset and subtract out if necessary, and an automatic startup and manual calibration to control the common mode voltages. The proposed ADC was designed in Intel’s 10nm technology. This ADC is designed to monitor DC voltages for the precision and high speed applications. The conversion rate of the analog to digital converter is programmable to 7µs or 910ns, depending on the precision or high speed application, respectively. The range of the input and reference supply is 0 to 1.25V. The ADC is designed in Intel 10nm technology using a 1.8V supply consuming an area of 0.0705mm2. This thesis explores challenges of designing a dual-purpose analog to digital converter, which include: 1.) increased offset in 10nm technology, 2.) dual application ADC that can be accurate and fast, 3.) reducing the parasitic capacitance of the ADC, and 4.) gain error that occurs in ADCs. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017

Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-de ned radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, o set mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an acceptable e ective-numberof- bits (ENOB) which can be degraded by jitter in the sample clock. The clock generation circuits presented in this work achieves sub-picosecond jitter performance in 180nm CMOS which is suitable for time-interleaved ADC. Two di erent test chips were fabricated in 180nm CMOS to investigate the low jitter design technique. The low jitter delay line in two chips were designed in two di erent ways, but both of them utilized the low jitter design technique. In rst test chip, the measured RMS jitter is 0.1061ps for each delay stage. The second chip uses the proposed low jitter Delay-Locked Loop can work from 80MHz to 120MHz, which means it can provide the time interleaved ADC with 2.4GHz to 3.6GHz low jitter sample clock, the measured delay stage jitter performance in second test chip is 0.1085ps.

CMOS technology scaling has enabled dramatic improvement for digital circuits both in terms of speed and power efficiency. However, most traditional analog-to-digital converter (ADC) architectures are challenged by ever-decreasing supply voltage. The improvement in time resolution enabled by increased digital speeds drives design towards time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The main challenge in VCO-based ADC design is mitigating the nonlinearity of VCO Voltage-to-frequency (V-to-f) characteristics. Achieving signal-to-noise ratio (SNR) performance better than 40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. This dissertation proposes a highly digital, reconfigurable VCO-based ADC with lookup-table (LUT) based background calibration based on "split ADC" architecture. Each of the two split channels, ADC "A" and "B", contains two VCOs in a differential configuration. This helps alleviate even-order distortions as well as increase the dynamic range. A digital controller on chip can reconfigure the ADCs' sampling rates and resolutions to adapt to various application scenarios. Different types of input signals can be used to train the ADC’s LUT parameters through the simple, anti-aliasing continuous-time input to achieve target resolution. The chip is fabricated in a 180 nm CMOS process, and the active area of analog and digital circuits is 0.09 and 0.16mm^2, respectively. Power consumption of the core ADC function is 25 mW. Measured results for this prototype design with 12-b resolution show ENOB improves from uncorrected 5-b to 11.5-b with calibration time within 200 ms (780K conversions at 5 MSps sample rate).

Chiral gold complexes have been applied in homogeneous catalytic reactions since 1986, in some cases with high enantioselectivity. Acyclic diaminocarbene (ADC) ligands are acyclic analogues of N-heterocyclic carbenes (NHCs) that have larger N-CCarbene-N angles and stronger donating ability. ADCs have been developed as alternatives to phosphine and NHC ligands in homogeneous gold catalysis. In 2012, a new series of chiral gold(I) ADCs were first developed by Slaughter's group and were shown to give remarkable enantioselectivities in some reactions. Because of the hindered rotation of the N-CCarbene bonds of ADC, chiral ADC substituents can easily get close to the metal center in some conformations, although two rotameric structures are formed if the chiral amine is nonsymmetric. The selective of specific ADC conformations was the initial focus of this study. Formational selectivity of one diastereomer of an ADC ligand during synthesis was examines by measuring the relative rates of diastereomer formation in a 1H NMR kinetic study. The potential for converting multiple conformational isomers of ADCs into a single conformation, or at least a simpler mixture, was examined. This study used the analogy that anti- isomer has electronic and structural similarity with urea/thiourea, raising the possibility that 1,8-naphthyridine can be used to favor certain conformations through a self-assembled hydrogen-bonding complex. Gold(I) is a soft carbophilic Lewis acid able to active C-C π bonds to nucleophilic attack, and ADC-gold complexes are potentially useful in this regard. Therefore, biaryl gold(I) ADC complexes were examine with silver salt additives in catalytic 1,6-enyne cyclization reaction. A detailed study found that the counteranion affects the regioselectivities of these reactions more than substituents on the ancillary ADC ligands.

This master's thesis is focused on the design of a highspeed aquizition system which is based on FPGA and a highspeed AD converter with modern JESD204B interface. Considering the requirements, such as high samplig rate, the current range of available devices is limited. Therefore the market overview of the modern IC and modules was made. The resulting design is based on available modules, so the rached sampling rate is up to 5 GSa/s with 12bits resolution. Data from measurement are send to PC via Ethernet which uses lwIp stack and TEMAC core on Microblaze proccessor.

This thesis deals with design and implementation of laboratory microcontroller system, based on ARM architecture. Purpose of this thesis is to teach programming. This system allows the user to work with the internal and external peripherals of the microcontroller, which are equipped with the system. This thesis includes creating a concept its peripheral solution and realization itself. A suitable development environment is determined for the system and the thesis includes sample solutions for the proposed tasks.

This work deals with the influence of MDAC (multiplying DAC) resolution on basic blocks of pipelined AD converter. The MDAC was designed with 1,5 and 2,5 bits resolution structure using switched capacitor technique (SC) utilizing CMOS 0,7 m technology. Basic stages of this pipelined ADC are analyzed and compared.

The goal of this project is to design a signal and data logger, which captures analog and digital signals with very long record time. The device supports multichannel complex triggering, a real-time oscilloscope-like mode and an offline mode for analyzing of previously sampled data. This project contains detailed analysis of the topic, description of hardware and software solutions and used methods. The thesis also contains verification tests and measurements. This device will be mainly used for hardware debugging of microprocessor based applications.

This paper presents the structure and basic elements of the Autosar software architecture. In addition, the configuration code generation options are presented for both MC-ISAR drivers and AURIX TriCore TC277 hardware modules using EB tresos Studio. For the purpose of possible integration of the electric motor control algorithms, configurations of the GTM and VADC hardware modules have been created and described to enable the generation of PWM signals along with synchronously triggered parallel analogue-to-digital conversions. For this purpose, an application interface including the PWM driver was also developed and described.

Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications. The proposed 8-bit, 10-GHz, 8× time-interleaved SAR ADC utilizes a constant-matching DAC with symmetrically grouped unit finger capacitors to maximize speed by reducing the total DAC capacitance to 32 fF and minimizing the bottom plate parasitic capacitance. The capacitance reduction also saves power as both the DAC size and the driving logic size are reduced. An optimized asynchronous comparator loop and smaller driver logic push the single channel speed of the SAR ADC to 1.25 GHz, thus minimizing the total number of timeinterleaved channels to 8 to reach 10 GHz. A dual-path bootstrapped switch improves the spurious-free dynamic range (SFDR) of the sampling by creating an auxiliary path to drive the non-linear N-well capacitance apart from the main signal path. Using these techniques, the ADC achieves a measured signal-to-noise-and-distortion ratio (SNDR) and SFDR of 36.9 dB and 59 dB, respectively with a Nyquist input while consuming 21 mW of power. The ADC demonstrates a record-breaking figure-of-merit of 37 fJ/conv.-step, which is more than 2× better than the next best published design, among reported ADCs of similar speeds and resolutions.