Acinetobacter baumannii is an emerging multiresistant pathogen increasingly known to cause infections in the immuno-compromised patients. Carbapenems and colistin are considered to be the last resorts in treatment of infections involving multidrug resistant strains of A. baumannii. Resistance to carbapenems is well known due to the presence of intrinsic carbapenemase gene blaOXA-51-like, which may be governed by insertion elements, or by acquired carbapenemases like blaOXA-23-like, blaOXA-58-like or blaOXA-40-like genes, most of which are frequently associated with insertion elements. The acquired carbapenemases can be integrated with the host chromosome making the bacterium strongly resistant to a range of antibiotics. Recent reports also suggest that the ubiquitous and intrinsic enzymes encoded by the blaOXA-51-like gene can be mobilized on a plasmid. In this thesis, the prevalence of antibiotic resistance was examined for 96 strains isolated from various parts of the world. The resistances to aminoglycosides, fluoroquinolones and cephalosporins were studied with a major focus on resistance to carbapenems. Section 1 shows the transposition of ISAba1 and its varied influence in controlling the blaOXA-51-like gene and the blaADC gene. It explains how ISAba1 being a strong factor in influencing antibiotic resistance genes contributes to the plasticity of the organism Section 2 is related with a novel insertion element ISAba125 controlling the blaADC gene and as an element providing high resistance to ceftazidime in comparison to ISAba1. Section 3 analyses the multi-drug resistant profile of strains isolated from Cochabamba, Bolivia. Besides the classification of carbapenem resistance for the clinical strains, the aminoglycoside resistance and ciprofloxacin mechanisms are examined in this project Section 4 relates with the pattern of resistance in strains isolated from the Aberdeen Royal Infirmary. It describes two novel variants of the blaOXA-51-like gene, namely blaOXA-216 and blaOXA-217 and also the acquisition of the blaOXA-23-like gene in two isolates from different years and deemed identical by their PFGE pattern. Section 5 describes the influence of ISAba825 in controlling the blaOXA-51-like gene and the blaOXA-58-like from clinical isolates Section 6 is related with the insertional inactivation of the blaOXA-132 gene and the carbapenem resistance caused by the activation of the blaOXA-58 gene in isolate Ab244 Section 7 describes the influence of insertion elements in strains having high ciprofloxacin resistance. This project is concerned with the role of efflux pump control system adeRS and how they influence the adeABC operon causing increased and decreased expression of the genes. Section 8 describes the multi drug resistant pattern of 36 strains each isolated from Europe and the United States In conclusion, there are various factors that influence the resistance profile of multidrug resistant A. baumannii isolates with insertion sequences such as ISAba1, ISAba2, ISAba3, ISAba825, IS1008, ISAba125, ISAba16 governing the expression or providing alternate mechanisms of resistance for the better fitness of the bacterium. Mutations in the genes identified in this study also have a crucial role in imparting resistance to this bacterium.

Time-Interleaved Analog to Digital Converters (TI ADC) consist of several individual sub-converters operating at a lower sampling rate, working in parallel, and in a circular loop. Thereby, they are increasing the sampling rate without compromising on the resolution during conversion, at high sampling rates. The latter is the main requirement in the area of radio frequency sampling. However, they suffer from mismatches caused by the different characteristics in each sub-converter and the TI structure. The output of the TI ADC under consideration contains a lot of harmonics and spurious tones due to the non-linearities mismatch between the sub-converters. Therefore, previously extensive frequency planning was performed to avoid the input signal from coinciding with these harmonic bins. More importance has been given to digital calibration in recent years where algorithms are developed and implemented outside ADC in a Digital signal processor (DSP), whereas the compensation is done in real time. In this work, we model the distortions and the harmonics present in the TI ADC output to get a clear understanding of the TI ADC. A post-correction block is developed for the cancellation of the characterized harmonics. The suggested method is tested on the TI ADCs working at radio frequencies, but is valid also for other types of ADCs, such as pipeline ADCs and sigma-delta ADCs.

The objective of this research is to optimize silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS analog circuit building blocks for operation in extreme environments utilizing design techniques. First, negative feedback effects on single-event transient (SET) in SiGe HBT analog circuits were investigated. In order to study the role of internal and external negative feedback effects on SET in circuits, two different types of current mirrors (a basic common-emitter current mirror and a Wilson current mirror) were fabricated using a SiGe HBT BiCMOS technology and exposed to laser-induced single events. The SET measurements were performed at the U.S. Naval Research Laboratory using a two-photon absorption (TPA) pulsed laser. The measured data showed that negative feedback improved SET response in the analog circuits; the highest peak output transient current was reduced by more than 50%, and the settling time of the output current upon a TPA laser strike was shortened with negative feedback. This proven negative feedback radiation hardening technique was applied later in the high-speed 5-bit flash analog-to-digital converter (ADC) for receiver chains of radar systems to improve SET response of the system.

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration.

Les convertisseurs analogique-numérique à entrelacement temporel (TIADC) semblent être une solution prometteuse dans le monde de la conversion analogique-numérique. Leur fréquence d’échantillonnage peut théoriquement être augmentée en augmentant le nombre de convertisseurs en parallèle. En réalité, des désappariements entre les convertisseurs peuvent fortement dégrader les performances, particulièrement à haute fréquence d’échantillonnage ou à haute résolution. Ces défauts d’appariement peuvent être réduits en utilisant des techniques de calibration en arrière-plan. La première partie de cette thèse est consacrée à l’étude des sources et effets des différents types de désappariements dans un TIADC. Des indicateurs de performance tels que le SNDR ou la SFDR sont exprimés en fonction du niveau des désappariements. Dans la deuxième partie, des nouvelles techniques de calibration sont proposées. Ces techniques permettent de réduire les effets des désappariements d’offset, de gain, d’instant d’échantillonnage et de bande passante. Les désappariements sont estimés en se basant sur des propriétés statistiques du signal et la reconstruction des échantillons de sortie se fait en utilisant des filtres numériques. La troisième partie démontre les performance d’un TIADC fonctionnant a une fréquence d’échantillonnage de 1.6 GE/s et comprenant les calibration d’offset, de gain et d’instant d’échantillonnage proposées. Les raies fréquentielles dues aux désappariements sont réduites à un niveau de -70dBc jusqu’à une fréquence d’entrée de 750 MHz. Ce circuit démontre une meilleure correction de désappariements que des circuits similaires récemment publiés, et ce avec une augmentation de puissance consommée et de surface relativement faible. / Time-interleaved analog-to-digital converters (TIADC) seem to be the holy grail of analog-to-digital conversion. Theoretically, their sampling speed can be increased, very simply, by duplicating the sub-converters. The real world is different because mismatches between the converters strongly reduce the TIADC performance, especially when trying to push forward the sampling speed, or the resolution of the converter. Using background digital mismatch calibration can alleviate this limitation. The first part of the thesis is dedicated to studying the sources and effects of mismatches in a TIADC. Performance metrics such as the SNDR and the SFDR are derived as a function of the mismatch levels. In the second part, new background digital mismatch calibration techniques are presented. They are able to reduce the offset, gain, skew and bandwidth mismatch errors. The mismatches are estimated by using the statistical properties of the input signal and digital filters are used to reconstruct the correct output samples. In the third part, a 1.6 GS/s TIADC circuit, implementing offset, gain and skew mismatch calibration, demonstrates a reduction of the mismatch spurs down to a level of -70 dBFS, up to an input frequency of 750 MHz. The circuit achieves the lowest level of mismatches among TIADCs in the same frequency range, with a reasonable power and area, in spite of the overhead caused by the calibration.

The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.

Com o aumento das aplicações e dispositivos para Internet das Coisas, muitos esforços para reduzir potência dissipada nos transceptores foram investidos. A maioria deles, entretanto, focam individualmente no rádio, nos conversores analógicos para digital e viceversa, e na arquitetura de banda base digital. Como consequência, há pouca margem para melhorias na potência dissipada nestes blocos isolados que compense o enorme esforço. Portanto, este trabalho propõe uma arquitetura adaptativa a nível de sistema focando em reduzir o consumo no conversor analógico para digital e no receptor digital. Ele utiliza um algoritmo robusto para o receptor banda base digital, um conversor analógico para digital topologia Sigma-Delta e um bloco de controle realimentado conforme a relação sinal ruído medida do pacote recebido. O sistema foi projetado para o protocolo IEEE 802.15.4. Para validação do sistema e estimar a potência consumida foi feito um modelo de sistema utilizando a ferramenta Matlab, uma descrição do hardware em linguagem Verilog e uma síntese lógica utilizando o processo da X-FAB XC018. As simulações mostram uma redução na potência consumida pelo sistema de até 13% e ainda atingindo os requisitos do protocolo. Os resultados deste trabalho foram publicados na conferência internacional em tecnologia de instrumentação e medidas de 2014 realizada na cidade de Montevidéu no Uruguai. / With the increase of Internet of Things applications and devices, many efforts to reduce power consumption in transceiver has been invested. Most of them targeted in RF frontend, converters, or in the digital baseband architecture individually. As result, there are few margins nowadays for power improvement in these blocks singly that compensates the huge hard work required. The next optimization step leads to a system level analysis seeking design space and new possibilities expansion. It is in this field that adaptive systems approaches are conquering ground recently. The solutions combines Radio Frequency (RF) and process variation techniques, Low Pass Filters (LPF) and Analog to Digital Converters (ADCs) adjustment for better performance, digital baseband bit width adaptive according to income packet SNR, configurable ADC resolution and topology, and others. In this scenario the current work proposes an adaptive system level architecture targeting ADC and digital receiver power reduction. It uses a robust algorithm for digital baseband receiver, a Sigma-Delta ADC, and suggests a feedback control block based on packet SNR measure. The system was designed for the IEEE 802.15.4 standard and required system modeling using Matlab tool, hardware description in Verilog language, and logic synthesis using X-FAB XC018 process for validation and power consumption estimation. Simulations show up to 15% of system power reduction and still meeting the standard requirements. The work results were published in the International Instrumentation and Measurement Technology Conference of 2014 occurred in Montevideo - Uruguay.

Les convertisseurs analogique-numérique à entrelacement temporel (TIADC) semblent être une solution prometteuse dans le monde de la conversion analogique-numérique. Leur fréquence d’échantillonnage peut théoriquement être augmentée en augmentant le nombre de convertisseurs en parallèle. En réalité, des désappariements entre les convertisseurs peuvent fortement dégrader les performances, particulièrement à haute fréquence d’échantillonnage ou à haute résolution. Ces défauts d’appariement peuvent être réduits en utilisant des techniques de calibration en arrière-plan. La première partie de cette thèse est consacrée à l’étude des sources et effets des différents types de désappariements dans un TIADC. Des indicateurs de performance tels que le SNDR ou la SFDR sont exprimés en fonction du niveau des désappariements. Dans la deuxième partie, des nouvelles techniques de calibration sont proposées. Ces techniques permettent de réduire les effets des désappariements d’offset, de gain, d’instant d’échantillonnage et de bande passante. Les désappariements sont estimés en se basant sur des propriétés statistiques du signal et la reconstruction des échantillons de sortie se fait en utilisant des filtres numériques. La troisième partie démontre les performance d’un TIADC fonctionnant a une fréquence d’échantillonnage de 1.6 GE/s et comprenant les calibration d’offset, de gain et d’instant d’échantillonnage proposées. Les raies fréquentielles dues aux désappariements sont réduites à un niveau de -70dBc jusqu’à une fréquence d’entrée de 750 MHz. Ce circuit démontre une meilleure correction de désappariements que des circuits similaires récemment publiés, et ce avec une augmentation de puissance consommée et de surface relativement faible. / Time-interleaved analog-to-digital converters (TIADC) seem to be the holy grail of analog-to-digital conversion. Theoretically, their sampling speed can be increased, very simply, by duplicating the sub-converters. The real world is different because mismatches between the converters strongly reduce the TIADC performance, especially when trying to push forward the sampling speed, or the resolution of the converter. Using background digital mismatch calibration can alleviate this limitation. The first part of the thesis is dedicated to studying the sources and effects of mismatches in a TIADC. Performance metrics such as the SNDR and the SFDR are derived as a function of the mismatch levels. In the second part, new background digital mismatch calibration techniques are presented. They are able to reduce the offset, gain, skew and bandwidth mismatch errors. The mismatches are estimated by using the statistical properties of the input signal and digital filters are used to reconstruct the correct output samples. In the third part, a 1.6 GS/s TIADC circuit, implementing offset, gain and skew mismatch calibration, demonstrates a reduction of the mismatch spurs down to a level of -70 dBFS, up to an input frequency of 750 MHz. The circuit achieves the lowest level of mismatches among TIADCs in the same frequency range, with a reasonable power and area, in spite of the overhead caused by the calibration.

Ce travail de thèse s'inscrit dans une collaboration entre le groupe Application et Valorisation des Interactions Rayonnement-Matière et l'entreprise Hamamatsu pour l'étude d'une électronique dédiée et fortement intégrée destinée à équiper un photomultiplicateur multianodes de type H8500. De par leur faible zone morte et leur configuration multianodes, ces photomultiplicateurs permettent d'améliorer les performances des gamma-caméras utilisées en particulier pour le dépistage du cancer du sein (scintimammographie). Après avoir élaboré un cahier des charges à partir des tests effectués sur ces tubes photomultiplicateurs, une électronique d'acquisition spécifique est proposée. Elle est composée d'un préamplificateur de courant multigain, d'un intégrateur commuté et d'un convertisseur analogique-numérique à rampe. L'ensemble est autodéclenché sur le signal. Cette électronique à fait l'objet de plusieurs prototypes multivoies dont la conception et les résultats de tests sont présentés.

<p>During test flights SAAB uses the data acquisition system COMET 16. The part of the system that receives the signals from the sensors and converts them is called KSM 15. The purpose of this thesis is to develop a data acquisition module on stacked PC/104 modules with a lower production cost. </p><p>Our work has been divided into one part about analog signal conditioning and a second part with digital filtering and memory management of the sampled data. The analog part, designed of regular components like instrument amplifiers, voltage references, operational amplifiers and multiplexers, adjusts the sensors signal levels for the ADC’s that converts the signals. In the digital part the sampling frequency is decimated by digital FIR filters in several stages down to 16 Hz. All the resulting data is temporarily stored in a SDRAM memory before being recovered by the HL-11 board that handles the communication with the other parts of the COMET system. </p><p>We have made a design proposal that needs some additional work and testing before a prototype can be made. It’s primarily the C code in the digital part that needs further development. </p><p>Our result and conclusions should be a great help in the future when developing a small,cheap data acquisition system.</p>