<p>High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.</p><p>To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.</p><p>The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.</p><p>The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.</p><p>A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.</p> / Report code: LiU-Tek-Lic-2005:68.

In today’s world the multi-standard wireless receivers are gaining more and more popularity. End-users want to access voice, data and streaming media from a single wireless terminal. An ideal approach for multi-standard receiver front-end is to digitize a wide band RF signal available from the antenna. All radio functions such as downconversion, demodulation and channel selection can be then performed in the digital domain. Analog to Digital Converter in such a case should guarantee very high linearity, speed and bandwidth specifications while consuming a lot of power. Unfortunately an ADC with such stringent requirements cannot be realized in today’s CMOS technology. In a typical receiver a mixer is used to downconvert the RF signal to baseband (or IF) before digitization is performed. A passive mixer is often used in this case to mitigate the effect of the low frequency flicker noise. Specially it can be a sampling mixer which also serves as a S/H circuit usually required for A/D conversion. In this thesis a lowpass sigma-delta converter with RF sampling is presented. The ΣΔ modulator is SC passive circuit plus comparator, so an operational amplifier usually needed to realize the integrator is avoided. To reduce the complexity, the sampling mixer in front of the modulator is merged with the passive loop filter. As a result the sampling mixer is closed in the modulator loop, so the overall linearity of the frontend is improved to some extent. Downconversion is combined with digitization that reduces the circuit complexity as well.The challenges while digitizing high frequency RF signal are discussed in details. Switches required to realize the loop filter are very critical and tend to be nonlinear. Parasitic effects associated with MOS transistors strongly show up at GHz frequencies. Optimized transistor sizes are obtained through simulation while addressing the speed and linearity trade-off. Another major challenge is the kT/C noise that is the real bottleneck in high frequency SC circuit design. A thermal noise model for ΣΔ-modulator with second-order loop filter is presented and it is shown that a passive ΣΔ-modulator is  in fact thermal noise limited rather than quantization noise limited. It is because the capacitor values are limited by the very high sampling frequency used in this case.The downconverting lowpass ΣΔ modulator with second order SC passive loop filter and 1-bit quantizer is simulated at transistor level in 90nm CMOS process. This modulator can operate at very high sampling frequency upto 4GHz and can sample RF signal with carrier of upto 4GHz as well. The designed ΣΔ modulator is flexible and supports sub-sampling by 2 to 8 (fs = 500MHz, ... 2GHz). Besides, the presented design is very power efficient as it does not use OpAmps – which consume most of the power in the typical ΣΔ modulators. From schematic simulation on average, signal-to-noise and distortion ratio (SNDR) of 52 dB is obtained (ENOB = 8.3). SNDR results does not vary much for three different cases of baseband digitalization, RF sampling and RF sub-sampling. This SNDR value seems to be a good number for a passive sigma-delta modulator. The detailed simulation results for the three cases discussed in the thesis work shown that, the modulator performs equally well for a wide range of sampling and RF signal frequencies.

Analog-to-digital converters (ADCs) are key design blocks in state-of-art image, capacitive, and biomedical sensing applications. In these sensing applications, algorithmic ADCs are the preferred choice due to their high resolution and low area advantages. Algorithmic ADCs are based on the same operating principle as that of pipelined ADCs. Unlike pipelined ADCs where the residue is transferred to the next stage, an N-bit algorithmic ADC utilizes the same hardware N-times for each bit of resolution. Due to the cyclic nature of algorithmic ADCs, many of the low power techniques applicable to pipelined ADCs cannot be directly applied to algorithmic ADCs. Consequently, compared to those of pipelined ADCs, the traditional implementations of algorithmic ADCs are power inefficient. This thesis presents two novel energy efficient techniques for algorithmic ADCs. The first technique modifies the capacitors' arrangement of a conventional flip-around configuration and amplifier sharing technique, resulting in a low power and low area design solution. The other technique is based on the unit multiplying-digital-to-analog-converter approach. The proposed approach exploits the power saving advantages of capacitor-shared technique and capacitor-scaled technique. It is shown that, compared to conventional techniques, the proposed techniques reduce the power consumption of algorithmic ADCs by more than 85\%. To verify the effectiveness of such approaches, two prototype chips, a 10-bit 5 MS/s and a 12-bit 10 MS/s ADCs, are implemented in a 130-nm CMOS process. Detailed design considerations are discussed as well as the simulation and measurement results. According to the simulation results, both designs achieve figures-of-merit of approximately 60 fJ/step, making them some of the most power efficient ADCs to date.

Analog-to-digital converters (ADCs) are key design blocks in state-of-art image, capacitive, and biomedical sensing applications. In these sensing applications, algorithmic ADCs are the preferred choice due to their high resolution and low area advantages. Algorithmic ADCs are based on the same operating principle as that of pipelined ADCs. Unlike pipelined ADCs where the residue is transferred to the next stage, an N-bit algorithmic ADC utilizes the same hardware N-times for each bit of resolution. Due to the cyclic nature of algorithmic ADCs, many of the low power techniques applicable to pipelined ADCs cannot be directly applied to algorithmic ADCs. Consequently, compared to those of pipelined ADCs, the traditional implementations of algorithmic ADCs are power inefficient. This thesis presents two novel energy efficient techniques for algorithmic ADCs. The first technique modifies the capacitors' arrangement of a conventional flip-around configuration and amplifier sharing technique, resulting in a low power and low area design solution. The other technique is based on the unit multiplying-digital-to-analog-converter approach. The proposed approach exploits the power saving advantages of capacitor-shared technique and capacitor-scaled technique. It is shown that, compared to conventional techniques, the proposed techniques reduce the power consumption of algorithmic ADCs by more than 85\%. To verify the effectiveness of such approaches, two prototype chips, a 10-bit 5 MS/s and a 12-bit 10 MS/s ADCs, are implemented in a 130-nm CMOS process. Detailed design considerations are discussed as well as the simulation and measurement results. According to the simulation results, both designs achieve figures-of-merit of approximately 60 fJ/step, making them some of the most power efficient ADCs to date.

Le domaine de l'instrumentation des capteurs est en constante évolution. Ce travail propose la conception des éléments clefs qui constituent les chaines d'instrumentations de capteurs d'aujourd'hui au travers de 3 applications concrètes. La première application est la mesure de vitesse et de position, par exemple dans un roulement. Nous présentons la conception et la réalisation d'un circuit analogique pour le conditionnement d'un capteur de type magnétorésistif. Ce capteur mesure le champ magnétique généré par les pôles magnétiques d'une roue codeuse. Le circuit est optimisé en bruit, en consommation et travaille sur une bande passante de plusieurs kHz. Pour compenser la dispersion des capteurs, le circuit permet des réglages d'offset et une calibration de gains. Il contient également une mémoire de type OTP (One Time Programmable Memory) qui sauvegarde les réglages associés au capteur. La deuxième application est la mesure de signaux de type EcoG afin d'interfacer le cerveau humain. Nous décrivons la conception et la réalisation d'un convertisseur Analogique/Numérique de type SAR. Il possède un convertisseur numérique analogique capacitif avec une capacité d'atténuation afin de réduire le nombre total de condensateur et ainsi la consommation. Le comparateur possède une entrée rail-to-rail et un système de préamplification avec auto zéro pour diminuer l'offset. Sa consommation est de 86µW pour une vitesse de 24Ks/S et 12bits de résolution. Enfin la troisième application est la mesure de pression stationnaire sur la voilure des avions afin d'en connaître les contraintes. Nous décrivons l'étude architecturale d'un convertisseur sigma-delta permettant d'atteindre une grande résolution pour des signaux de faible fréquence. Il sera de type incrémentale et répondra à des applications de type instrumentation de capteur. Sa résolution est de 16bits ENOB pour une fréquence maximale d'entrée de 100Hz et minimale de sortie d'1Ks/S. Le mode incrémental permettra d'obtenir une sortie en réponse à une requête de manière asynchrone. Une modélisation de chaque élément du système complet convertisseur plus capteur a été effectuée sous Matlab. L'étude de la partie filtrage numérique du convertisseur et l'optimisation de son implémentation numérique sont présentées. Cette étude architecturale complète aboutit au dimensionnement de chaque élément pour répondre au cahier des charges de l'application . / The domain of sensors instrumentation is constantly evolving. The present work proposes the design of the key elements conception which constitute the instrumentations chains of current sensors through 3 concrete applications. The first application is speed and position measurement, for example in a wheel bearing. We present the design and realization of an analogical circuit for the conditioning of magneto resistive sensor. This sensor measures the magnetic field generated by the coding wheel magnetic poles inside the bearing. The circuit is noise and power consumption optimized on a bandwidth of few kHz. To compensate sensors variability, the circuit includes offset regulations and gains. It also contains an OTP (One Time Programmable) memory which backs up the associated sensor regulations. The second application is the measurement of EcoG's signals to interface with the human brain. We describe the design and realization of SAR ADC. It is composed of a capacitive DAC with an attenuation capacitor to reduce the total number of condensers and, in doing so, to reduce power consumption. The comparator is composed by a rail-to-rail input and multistage preamplification and output offset storage. ADC total power consumption is 86µW for 24Ks/S speed and 12bits resolution. Finally the third application is the pressure measurement on aircraft wings. We describe the architectural study sigma-delta incremental ADC which reaches high resolution for low band pass signals. Its resolution is 16bits ENOB for a maximal input frequency of 100Hz and an output speed of 1Ks/S. The incremental mode leads to obtain output code in answer to asynchronous requests. Each system element (converter plus sensors) has been matlab modelled. The converter digital filtering study and its digital implementation optimization are presented. This complete architectural study concludes with the sizing of each element in order to answer the technical specifications of the application.

La chromatographie en phase liquide bidimensionnelle « comprehensive » en ligne (LCxLC) est une technique à très haut pouvoir de séparation. Après avoir établi son intérêt mais aussi les enjeux liés au développement de méthodes et les conditions expérimentales utilisées, une attention particulière est portée à l'optimisation des méthodes en LCxLC. Une procédure d'optimisation basée une méthode « Pareto-optimal » est décrite. Les conditions optimales prédites sont ensuite appliquées à la séparation RPLCxRPLC d'un mélange complexe de peptides et comparée avec la 1D-RPLC en termes de capacité de pics, temps d'analyse et facteur de dilution démontrant l'avantage fournit par la RPLCxRPLC. L'optimisation d'une méthode HICxRPLC-UV/MS en ligne permettant la caractérisation exhaustive d'un anticorps conjugué est réalisée soulignant, entre autres, la grande complémentarité entre les différents modes de détection employés en 1D et 2D.Enfin, la possibilité de développer un couplage RPLCxSFC est explorée dans le but d'augmenter l'espace de séparation pour des composés neutres. La méthode RPLCxSFC optimisée est comparée avec une séparation RPLCxRPLC optimisée pour l'analyse d'une bio-huile montrant qu'elle peut-être considérée comme une alternative crédible pour la séparation de tels échantillons / Comprehensive two-dimensional liquid chromatography is a powerful but complex separative technique. After detailing the interest of such a technique, the method development issues and the experimental conditions employed throughout this work, a particular attention is paid to the optimization of LCxLC methods. Accordingly an optimization procedure based on Pareto-optimal method is described. The predicted optimal conditions are then applied to experimental RPLCxRPLC separations of complex samples of peptides and compared with 1D-RPLC in terms of peak capacity, analysis time and sensitivity clearly showing the advantage of RPLCxRPLC approach.The optimization of a HICxRPLC-UV/MS method for the exhaustive characterization of an antibody-drug conjugate is achieved highlighting the high complementarity of the different detection modes used both in 1D and 2D. Finally, a proof of concept concerning the implementation of RPLCxSFC coupling is achieved with the aim of increasing the separation space coverage for neutral compounds. The optimized RPLCxSFC separation is then compared with an optimized RPLCxRPLC approach for the analysis of a bio-oil sample showing that RPLCxSFC is a credible alternative for the separation of such a sample

Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, typically requirelow-speed, medium-resolution ADCs. The successive approximation register (SAR) ADC exhibits significantly high energy efficiency compared to other prevalent ADC architectures due to its good tradeoffs among power consumption, conversion accuracy, and design complexity. To design an energy-efficient SAR ADC, an understanding of its error sources as well as its power consumption bounds is essential. This thesis analyzes the power consumption bounds of SAR ADC: 1) at low resolution, the power consumption is bounded by digital switching power; 2) at medium-to-high resolution, the power consumption is bounded by thermal noise if digital assisted techniques are used to alleviate mismatch issues; otherwise it is bounded by capacitor mismatch.  Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. It is not straightforward to effectively reduce the unnecessary speed for lower power consumption using inherently fast components in advanced CMOS technologies. Moreover, the leakage current degrades the sampling accuracy during the long conversion time, and the leakage power consumption contributes to a significant portion of the total power consumption. Two SAR ADCs have been implemented in this thesis. The first ADC, implemented in a 0.13-µm CMOS process, achieves 9.1 ENOB with 53-nW power consumption at 1 kS/s. The second ADC, implemented in a 65-nm CMOS process, achieves the same resolution at 1 kS/s with a substantial (94%) improvement in power consumption, resulting in 3-nW total power consumption. Our work demonstrates that the ultra-low-power operation necessitates maximum simplicity in the ADC architecture.

<div>Given the increasing importance of mobile data access, extending broadband wireless access have become a global grand challenge. Wireless sensor networks (WSNs) and millimeter wave (mmWave) systems have been introduced to resolve these issues which motivate us to have further investigation. In this paper, the first two work assuming a quantized-and-forward WSN. We first develop a rate adaptive integer forcing source coding (RAIF) scheme to enhance the system throughput by assigning optimal quantization rate to each sensor optimally. Then, we are interested in developing an supervised online technique for solving classification problems. In order to enhance the classification performance, we developed this technique by jointly training the decision function that determines/estimates class label, quantizers across all sensors, and reliability of sensors such that M' most reliable sensors are enabled. Finally, we develop an idea to provide a folded low-resolution ADC array architecture that can utilize any of the widely published centralized folded ADC (FADC) implementation by placing the centralized FADC branches at different antenna elements in a millimeter wave (mmWave) system. With adding a simple analog shift and modulo operations prior to the sign quantizer, we show that the multiple low-resolution ADCs across the array elements can be properly designed such that they can be combined into an effective high-resolution ADC with excellent performance characteristics.</div>

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International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / The function of a PCM telemetry encoder, installed in moving vehicles such as automobiles, aircraft, missiles, and artillery projectiles, is to transform many physical variables, such as velocity, shock, temperature, vibration and pressure, into digital data. Also, the encoder is required to make a data frame composed of digital input signals and frame synchronous data. The framed data is supplied to the input of a transmitter. There are three critical considerations in developing a PCM telemetry encoder to be installed in an artillery projectile. The first is the performance consideration, such as sampling rate, data receiving rate and data transmission rate. The second is the size consideration due to the severely limited installation space in an artillery projectile and the last is the power consumption consideration due to limitations of the munition’s power supply. To meet these three considerations, the best alternative is a one-chip solution. Using a commercially available TMS320F2812 DSP chip, we have implemented a 30-channel PCM telemetry encoder to process randomized data frames, composed of 16-channel analog data, 14-channel digital data and 2 frame synchronization data per data frame, at 10Mbps transmission baud rate. This paper describes the structure of the 30-channel PCM telemetry encoder and its performance.