It is well known that thermally evaporated a-As2S3 thin films are prone to oxidation when exposed to an ambient environment. These As2O3 crystals are a major source of scattering loss in sub-micron optical integrated circuits. Magnetron sputtering a-As2S3 not only produces films that have optical properties closer to their equilibrium state, the as-deposited films also show no signs of photo-decomposed As2O3. The TM propagation loss of the as-deposited As2S3-on-Ti:LiNbO3 waveguide is 0.20 plus/minus 0.05 dB/cm, and it is the first low loss hybrid waveguide demonstration. Using the recipe developed for sputtering As2S3, a hybrid Mach-Zehnder interferometer has been fabricated. This allows us to measure the group index of the integrated As2S3 waveguide and use it in the study of the group velocity dispersion in the sputtered film, as both material dispersion and waveguide dispersion may be present in the system. The average group index of the integrated As2S3 waveguide is 2.36 plus/minus 0.01. On-chip optical amplification was achieved through thermal diffusion of erbium into X-cut LiNbO3. The net gain measured for a transverse magnetic propagation mode in an 11 μm wide Er:Ti:LiNbO3 waveguide amplifier is 2.3 dB plus/minus 0.1 dB, and its on-chip gain is 1.2 plus/minus 0.1 dB/cm. The internal gain measured for a transverse electric propagation in an 7 μm wide Er:Ti:LiNbO3 waveguide amplifier is 1.8 dB plus/minus 0.1 dB and is among the highest reported in the literature. These gains were obtained with two 1488 nm lasers at a combined pump power of 182mW. In order to increase further the on-chip gain, we have to improve the mode overlap between the pump and the signal. This can be done by doping erbium into As2S3 film using multi-layer magnetron sputtering. The Rutherford backscattering spectroscopy shows that the doping of Er:As2S3 film with 16 layers of erbium is homogeneous, and Raman spectroscopy confirms no significant amount of Er-S clusters in the sputtered film. The deposition method was used to fabricate an Er:As2S3 waveguide, and the presence of active erbium ions in the waveguide is evident from the green luminescence it emitted when it was pumped by 1488 nm diode laser.

The instrumentation amplifier (IA) is one of the crucial blocks in an electrocardiogram recording system. It is the first block in the analog front-end chain that processes the ECG signal from the human body and thus it defines some of the most important specifications of the ECG system like the noise and common mode rejection ratio (CMRR). The extremely low ECG signal bandwidth also makes it difficult to achieve a fully integrated system. In this thesis, a fully integrated IA topology is presented that achieves low noise levels and low power dissipation. The chopper stabilized technique is implemented together with an AC coupled amplifier to reduce the effect of flicker noise while eliminating the effect of the differential electrode offset (DEO). An ultra low power operational transconductance amplifier (OTA) is the only active power consuming block in the IA and so an overall low power consumption is achieved. A new implementation of a large resistor using the T-network is presented which makes it easy to achieve a fully integrated solution. The proposed IA operates on a 2V supply and consumes a total current of 1.4µA while achieving an integrated noise of 1.2µVrms within the bandwidth. The proposed IA will relax the power and noise requirements of the analog-to-digital converter (ADC) that immediately follows it in the signal chain and thus reduce the cost and increase the lifetime of the recording device. The proposed IA has been implemented in the ONSEMI 0.5µm CMOS technology.

This thesis improved the structure of traditional envelope elimination and restoration transmitter by replacing the analog components of envelope detector and limiter using digital processing technique of polar transformation. Envelope signal was modulated by delta-sigma modulation, which could suppress the quantization noise and would be good for integrated circuit design. The front end analog circuits of transmitter used high efficiency class-S and class-E power amplifiers to amplify envelope and phase signal separately and finally combined them at the output of class-E power amplifier. The RF transmitters using polar modulation had advantages of high efficiency and linearity when transmitting high PAPR-valued digital modulation signals. For example, when transmitting the QPSK-modulated signal with 900MHz carrier and 1Msps data rate, the transmitter was measured with efficiency as high as 60%, ACPR above 34dB, and EVM less than 6.5%.

This thesis consists of two parts. Part one includes the design procedure and implementation of the building blocks for an RF tuner module used in the Digital Video Broadcasting ¡V Terrestrial ¡]DVB-T¡^system. It contains the comparison of several RF tuner architectures, frequency planning, and link-budget analysis. Measurement results for the designed tuner operating in the frequency range from 50 to 860 MHz show that the maximum power gain ranges from 49 to 57.6 dB. The entire range for gain control is over 60 dB. In the maximum gain state, the noise figure ranges form 6.8 to 11.5 dB, the output third-order interception point¡]OIP3¡^ranges from 11.7 to 13.8 dBm, and the image rejection is over 50 dB. By applying the simplified single-carrier modulation signals, the tuner can pass the DVB-T system specifications with respect to the adjacent-channel and overlapping-channel protection ratios. In part two, an RFIC design for low-noise variable-gain amplifier that can be used in the RF front end of DVB-T system is presented. It operates from 100 to 900 MHz and dissipates 59.4 mW under a 3.3-V power supply. In the maximum gain state, measurement results for this RFIC show that the noise figure is less than 4 dB, the maximum gain is more than 14 dB, and the OIP3 is about 6.8dBm. The entire gain control range is over 40 dB.

This thesis presents a novel three-level modulation technique for a Class-D audio amplifier, attempting to improve the poor performance of the conventional two-level modulation scheme at low input levels. The main drawback of the conventional two-level PWM (pulse-width modulation) and SDM (sigma-delta modulation) Class-D amplifier is that, with a zero input or small input, the excessively fast switching action at the output causes unwanted switching loss and switching noise, resulting in unnecessary energy waste and SNDR degradation. The presented three-level modulation circuit mainly consists of a linear feedback compensator, two comparators, and a switching logic circuit. The simulation and experimental results shows that the proposed three-level modulation s cheme outperforms the two-level sigma-delta modulation scheme in both efficiency and performance.

In this thesis a single stage detector logarithmic video amplifier is designed with a dynamic range of 40dB in 2-6GHz frequency band. Since the detector logarithmic video amplifier (DLVA) is used to convert the power of the RF signals to video voltages in logarithmic scale, it can be regarded as a logarithmic converter instead of logarithmic amplifier. The design is composed of two main parts: The Schottky diode detector rectifies the incoming RF signal and produces a video voltage and the logarithmic amplifier transforms the scale of the video voltage from linear scale to logarithmic scale in order to observe the RF signals with a wide amplitude range. The approximation of the logarithmic function is obtained by the summation of the output currents of the differential amplifiers operating as logarithmic stages. Offset voltage of the DLVA is minimized in order to obtain maximum sensitivity / this makes the detection of RF signals with low power possible. The study is composed of mainly three parts: First, brief information about logarithmic amplification techniques is given and the circuit architecture is developed for logarithmic amplification and video detection, second these circuits are simulated and finally the design is implemented and tested.

In modern wireless communication systems, new modulation types are introduced in order to support more users by considering spectral efficiency. These new signals are ensitive to nonlinearity when they have high peak to average ratio. The main part in the system that causes nonlinearity is the power amplifier. For power amplifiers, between linearity and efficiency, there is a trade-off. However, by using predistortion techniques, both linearity and efficiency can be obtained. In this thesis, various predistortion methods are explained and memory polynomial digital predistortion is studied because of its great advantages. The results are obtained by simulations through MATLAB and experiments. An open loop test bench is built up with real amplifier. During experimental procedure, as input two tone signal, 8psk modulated signal and pi/2 bpsk modulated signal are used. Predistortion with memory and memoryless predistortion performances are compared and superiority of the predistortion with memory is shown. Predistortion performance with respect to memory depth and polynomial order is also studied. Moreover, predistortion model range is investigated through evaluation of performance by applying predistorter function estimated at a specific bandwidth and power to other signals having different bandwidth and power. Besides these works, the details of predistortion algorithm and the problems that can be countered in practice are explained.

Abstract Four high-performance circuits design techniques for embedded DRAM are proposed. First, a negative voltage generator having high efficiency is proposed to provide the negative voltage for the modified word line driver. The negative voltage generator circuits could be manufactured in n-Well CMOS process, and its operation achieve optimal output voltage. When 2.0-V supplied voltage is applied, the output voltage of -1.6-V is obtained. Even though, the supplied voltage is scaled down to 1.5-V, the output voltage can still achieve -1.05-V. In contrast, the output voltage of traditional one under 2.0-V supplied voltage is only -0.67-V. Second, a fast wordline driver suitable for PMOS pass transistor is proposed. The wordline driver improves the turned-on time by 26.8ns compared with the traditional one and raises the operating speed by 79%. Third, a new reduced clock-swing driver is proposed. Under 2.0-V supplied voltage and 100MHz operating frequency, the total power consumption of the new driver working with RCSFF is reduced by 10% than that of traditional one working with RCSFF. For the above advantage of low power, the new driver is thus more suitable for embedded DRAM applications. Fourth, a modified hierarchical read bus amplifier is proposed. The read bus amplifier is based on the new sense-amplifier. It could drive the output by full-swing voltage. It improves the sensing speed by 2.1ns. And it got the same advantage of no dc idling current as the traditional N&PMOS cross-coupled amplifier. In this thesis, finally, the performance of these circuits is also integrated and examined in an 1-Kbit embedded DRAM test circuit. The simulation RAS access time of 27.9ns is achieved under 2.0V supplied voltage and loading of 16-Mbit embedded DRAM. This indicated the above proposed circuits could be applied in the low voltage and high speed embedded DRAM.

The theoretical stability analysis of mold level control system for slab continuous casting machine is presented in this thesis. In the procedure of analyzing the stability of the mold level control system, the PLC program written for the control system is studied first in order to obtain the mathematical model of a PID controller. Then the mathematical models of servo-amplifier, servo-valve, electro hydraulic system to the output of mold level are established. A simulative control system using Matlab software is constructed in accordance with these mathematical models so that not only the results of stability analysis can be verified but also the dynamic response of controlled system can be studied. Finally, the effects of some potential disturbance on system¡¦s dynamics, stability, and control accuracy are also analyzed.

The first topic of this thesis is to propose a novel voltage-to-frequency converter (VFC) to provide high sensitivity. The VFC circuit is composed of one current mirror, one current multiplier, and voltage window comparators. The proposed VFC tracks the variations of the stored charge of a built-in capacitor. The voltage window comparator monitors the voltage of the capacitor to determine whether the output is pulled high or pulled down. The worth-case linear range of the output frequency of the proposed VFC is 0 to 55 MHz provided that the input voltage is 0 to 0.9 V. The error is less than 9% while the power dissipation is 0.218 mW. The second topic is to carry out a novel CMOS current-mode high- speed sense amplifier (SA). The proposed SA is composed by cascading a current-mode sense amplifier and a voltage-mode sense amplifier. The small input impedance of the current-mode amplifier alleviates the loading effect on the bitlines of SRAM cells such that the sensing speed is enhanced. The voltage-mode amplifier is responsible for boosting the logic levels to full swing. The worst access time of the proposed design is found to be less than 1.26 ns with a 1 pF load on outputs. The power dissipation is merely 0.835 mW at 793 MHz.