This thesis focuses on the design and implementation of a three-level Class D audio amplifier by applying recently developed sliding-mode quantized control. The designed controller, which consists of the analog filters and logic circuit, switches an H-bridge Class-D amplifier with a lowpass LC filter and operates it in the sliding mode, in order to achieve desired stability and high fidelity in the audio band. The experimental result shows that the lowest THD+N (total harmonic distortion plus noise) can be as low as 0.02% at 1 kHz. The performance is better than most of the available commercial products.

Recently, with the escalating demands for optical communications, the need for bandwidth in optical communication network has increased. The technology breakthrough in dry fiber fabrication opens the possibility for fiber bandwidth from 1.3 to 1.6 £gm. Cr4+:YAG double-clad crystal fiber (DCF) grown by the co-drawing laser-heated pedestal growth method has a strong spontaneous emission spectrum from 1.3 to 1.6 £gm. Such fiber is, therefore, eminently suitable for broadband optical amplifier, amplifier spontaneous emission (ASE) light source, tunable solid-state laser, and optical coherence tomography (OCT) applications. In this thesis, multilayer dielectric thin films were directly deposited by E-gun coating onto the end faces of the heterostructure Cr4+:YAG DCF. In this way we have successfully improved the extracted ASE power by the high reflection (HR) coatings. The backward ASE in the fiber reflected and propagates with gain through the fiber in the forward direction. In dual-pump scheme, as much as 1.7 mW power (DCF length is 9.5 cm) of collimated output ASE was achieved. The dual-pump scheme and HR thin films provided 1.6 time improvements of the ASE output power. For broadband optical amplifier in dual-pump and double-pass scheme, a 3.7-dB gross gain and a 0.7-dB net loss (DCF length is 8.7 cm) at 1.4-£gm signal wavelength have been successfully developed with HR coatings onto one of the Cr4+:YAG DCF end faces. In addition, we have successfully developed the Cr4+:YAG DCF fiber laser by direct HR coatings onto fiber end faces. A record-low threshold of 96 mW (DCF length is 1.6 cm) with a slope efficiency of 6.9% was achieved at room temperature. It is more than four times lower than any previously reported Cr4+:YAG lasers.

This thesis proposes a modified inductively degenerated common-emitter low-noise amplifier. To add a series-shunt feedback capacitance in series to the base of the cascode transistor for increasing the load impedance of the common-emitter transistor and enhancing the Miller effect, it is applied to improve the circuit¡¦s performance. By thoroughly studying the Miller effect for the input matching, noise, and linearity analysis and derivation of the modified structure, the theoretical analysis and experiments demonstrate the improved linearity and well noise performance. In addition, the proposed method is presented with the good figure of merit. The proposed method is presented in a hybrid circuit with the NEC 2S5010 NPN transistor for 900 MHz applications. It demonstrates that this method improves the linearity and the figure of merit has been increased by 50 to 70 percent. Moreover, the novel low noise amplifier is designed with a 0.35£gm SiGe BiCMOS process supported by the TSMC for 5.7 GHz WLAN band applications. It is found that the circuit has the characteristic of IM3 nonlinearity cancellation because the cascode transistor eliminates the third-order intermodulation genaerated by the common-emitter transistor. This thesis establishes a realizable method for high-linearity low-noise amplifier.

The objective of this thesis is aimed at the design of low noise amplifier (LNA) for an ultra-wideband (UWB) receiver system using standard 0.18um CMOS process. A two amplified stage topology is proposed in the low noise amplifier. The first stage introduces inductively source degeneration and resistive-feedback, it can achieve wideband input impedance matching. The second stage introduces traditional CS configuration, it can improve the forward gain (S21). The second stage also used L-C section for output match. In order to improve the gain at high frequency, we introduces the series peaking between the first stage and second stage. The total power dissipation of the low noise amplifier is about 24.3mW at power supply 1.5 volt and the chip size is 1.283*1.008mm2. The simulated result shows that S11 is under -8dB, S22 is under -10dB, the forward gain S21 is 12.6dB~15.3dB at 3.1-10.6GHz, the reverse isolation S12 is under -30dB, and the noise figure is 3.24dB~4.84dB.

Steady increases in the bandwidth requirements of access networks and local area networks have created a need for short-reach links supporting data rates of 10 Gb/s and larger. Server applications and data center applications too require such links. The primary challenge for these links lies in the reduction of the cost while retaining or improving the performance. Traditionally, multimode fiber (MMF) has satisfied these needs because of its low installation cost resulting from the alignment tolerance associated with the large core size. However, in view of the ever-increasing performance requirements, extraction of the best performance requires a holistic view of the channel that involves global optimization of transmitter, fiber, receiver performance and signaling strategies. The optimization results in a channel impairment mitigation technique that is a combination of optical, opto-electronic, and electronic methods. Both glass and plastic MMF links have been addressed in this work and many of the advances apply equally to both media. One example that applies strictly to glass MMF is the use of Raman amplification to not only combat attenuation but to reduce intersymbol interference (ISI). Raman amplification was demonstrated as an optical channel impairment mitigation technique enabling multi-km, multi-Gb/s transmission over glass-MMF. We demonstrated both numerically and experimentally that a power penalty reduction of 1.4 dBo can be achieved for 10 Gb/s transmission over 9 km of 62 micron glass MMF with a Raman pump power 250 mW. In recent years, plastic optical fiber (POF) has emerged as a potentially lower cost alternative to glass-MMF in enabling high performance links. The primary objective of this research is to explore the possibilities and develop low-cost, short-reach, high-data-rate POF-links. Using a comprehensive multimode fiber model, we showed that strong mode coupling, together with a reasonably accurate refractive index profile enables 40 Gb/s transmission over 200 m of graded-index POF. We experimentally demonstrated 40 Gb/s error-free transmission over 100 m of graded index perfluorinated POF (GI-PF-POF). We also demonstrated that even larger core (120 micron) GI-PF-POF can support >10 Gb/s over 100 m length. We numerically computed and experimentally measured the differential modal delay of GI-PF-POF to demonstrate that the available bandwidth is nearly independent of the launch conditions. Therefore, the alignment tolerance at the transmitter is increased resulting in a dramatically reduced packaging cost at the transmitter. However, the large-core POF increases the difficultly in capturing of the light efficiently onto a detector and results in optical power penalty and associated modal noise. To solve this, we have designed and developed a 10 Gb/s photoreceiver consisting of a large (100 micron diameter) GaAs PIN photodetector and a regulated cascade input based transimpedance amplifier (TIA) with low input impedance. Thus, a low-cost, alignment-tolerant, high-data-rate link is realized that uses a high-power, high-speed vertical cavity surface emitting laser (VCSEL) transmitter, large-core, high-speed GI-PF-POF, and the developed receiver.

High-efficiency performance is one of the most important requirements of power amplifiers (PAs) for wireless applications. However, the design of highly efficient CMOS PAs for watt-level applications is a challenging task. This dissertation focuses on the development of the design method for highly efficient CMOS PAs to overcome the fundamental difficulties presented by CMOS technology. In this dissertation, the design method and analysis for a high-power and highefficiency class-E CMOS PA with a fully integrated transformer have been presented. This work is the first effort to set up a comprehensive design methodology for a fully integrated class-E CMOS PA including effects of an integrated transformer, which is very crucial for watt-level power applications. In addition, to improve efficiency of cascode class-E CMOS PAs, a charging acceleration technique is developed. The method accelerates a charging speed to turn off the common-gate device in the off-state, thus reducing the power loss. To demonstrate the proposed cascode class-E PA, a prototype CMOS PA was implemented in a 0.18-μm CMOS process. Measurements show an improvement of approximately 6% in the power added efficiency. The proposed cascode class-E PA structure is suitable for the design of high-efficiency class-E PAs while it reduces the voltage stress across the device.

There have been many efforts to improve efficiency of transmitter while meeting stringent linearity requirement of modern communication system. Among the technology to enhance efficiency of linear transmitter, the out-phasing technologies, also called the linear amplification with nonlinear components (LINC), is considered as a promising technology. LINC has been studied long times, since it provides excellent linearity with high efficiency by allowing adopt high efficient switch-mode power amplifiers. However, The LINC transmitter has some technical challenges: linearity degradation due to amplitude and phase mismatches, efficiency degradation due to poor combining efficiency, and narrow frequency bandwidth due to output matching network of switching power amplifier. In this thesis, some state-of-the-art techniques for solving the problems of LINC transmitters are presented. An unbalanced phase calibration technique compensates amplitude/phase mismatches between two parallel paths in the LINC system, and multi-level LINC (MLINC) and an uneven multi-level LINC (UMLINC) structure improve the overall power efficiency. And the reconfigurable Class-D switching PA enables multi-band operation with high efficiency and good linearity. With these techniques, the new multi-band out-phasing transmitter improves the efficiency without sacrificing the linearity performance.

<p>In this thesis, design aspects of fully integrated multibandmultistandard front-end receivers are investigated based onthree fundamental aspects: noise, linearity and operatingfrequency. System level studies were carried out to investigatethe effects of different modulation techniques, duplexing andmultiple access methods on the noise, linearity and selectivityperformance of the circuit. Based on these studies and thelow-cost consideration, zero-IF, low-IF and wideband-IFreceiver architectures are promising architectures. These havea common circuit topology in a direct connection between theLNA and the mixer, which has been explored in this work toimprove the overall RF-to-IF linearity. One front-end circuitapproach is used to achieve a low-cost solution, leading to anew multiband multistandard front-end receiver architecture.This architecture needs a circuit whose performance isadaptable due to different requirements specified in differentstandards, works across several RF-bands and uses a minimumamount ofexternal components.</p><p>Five new circuit topologies suitable for a front-endreceiver consisting of an LNA and mixer (low-noise converter orLNC) were developed. A dual-loop wide-band feedback techniquewas applied in all circuits investigated in this thesis. Threeof the circuits were implemented in 0.18 mm RF-CMOS and 25 GHzbipolar technologies. Measurement results of the circuitsconfirmed the correctness of the design approach.</p><p>The circuits were measured in several RF-bands, i.e. in the900 MHz, 1.8 GHz and 2.4 GHz bands, with S11 ranging from–9.2 dB to–17 dB. The circuits have a typicalperformance of 18-20 dB RF-to-IF gain, 3.5-4 dB DSB NF and upto +4.5 dBm IIP3. In addition, the circuit performance can beadjusted by varying the circuit’s first-stage biascurrent. The circuits may work at frequencies higher than 3GHz, as only 1.5 dB of attenuation is found at 3 GHz and nopeaking is noticed. In the CMOS circuit, the extrapolated gainat 5 GHz is about 15 dB which is consistent with the simulationresult. The die-area of each of the circuits is less than 1mm2.</p>

<p>Radar warning systems are life saving equipment in modern fighter aircraft. It is therefore vital that the system can tell the difference between a threat genuine frequency) and a false signal (spurious frequency). </p><p>This thesis presents a model aimed at predicting the frequencies and other parameters in the RF converter of the radar warning system. The components of the RF converter have been studied, measured, and modelled. The modelling tool has been the Simulink toolbox for Matlab. </p><p>Extreme accuracy has been sacrificed in order to make the model easy to use for the working engineer. Instead, this model presents a rough estimate of some of the most important properties of the radar warning system with just a few data sheet figures as input.</p><p>The simulation results are satisfactory as a whole. Simulink is the limiting factor in the implementation of the model. Significantly improved results can probably be obtained by working in another software environment.</p>

The objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation. / text