High-peak power laser systems are defined along with a brief introduction of the technology used in their development and application to the project. A review of concepts surrounding optical pulses, focusing on the particular phenomena involved with the ultrafast, follows. Numerical models involving optical pulses are introduced and verified. An extensive description of the laser system is presented, including models used in its design. Data verifying the correct operation of the laser system is presented and interpreted. A dispersion compensation system, including a function model, is introduced, and its application to the laser system is analyzed. An introduction to pulse characterization techniques is presented followed by the design and verification of two different characterization devices. Experiments utlizing the dispersion compensation system and pulse characterization devices are presented and the results are interpreted. Conclusions are made regarding the performance of the laser system models and pulse characterization devices, along with suggested improvements for each. The results of the experiments are discussed including suggestions for future work.

Radio frequency (RF) communications are limited to a number of frequency bands scattered over the radio spectrum. Applications over such bands increasingly require more versatile, data extensive wireless communications that leads to the necessity of high bandwidth efficient interfaces, operating over wideband frequency ranges. Whether for a base station or mobile device, the regulations and adequate transmission of such schemes place stringent requirements on the design of transmitter front-ends. Increasingly strenuous and challenging hardware design criteria are to be met, especially so in the design of power amplifiers (PA), the bottle neck of the transmitter’s design tradeoff between linearity and power efficiency. The power amplifier exhibits a nonideal behavior, characterized by both nonlinearity and memory effects, heavily affecting that tradeoff, and therefore requiring an effective linearization technique, namely Digital Predistortion (DPD). The effectiveness of the DPD is highly dependent on the modeling scheme used to compensate for the PA’s nonideal behavior. In fact, its viability is determined by the scheme’s accuracy and implementation complexity. Generic behavioral models for nonlinear systems with memory have been used, considering the PA as a black box, and requiring RF designers to perform extensive testing to determine the minimal complexity structure that achieves satisfactory results. This thesis first proposes a direct systematic approach based on the parallel Hammerstein structure to determine the exact number of coefficients needed in a DPD. Then a physical explanation of memory effects is detailed, which leads to a close-form expression for the characteristic behavior of the PA entirely based on circuit properties. The physical expression is implemented and tested as a modeling scheme. Moreover, a link between this formulation and the proven behavioral models is explored, namely the Volterra series and Memory Polynomial. The formulation shows the correlation between parameters of generic behavioral modeling schemes when applied to RF PAs and demonstrates redundancy based on the physical existence or absence of modeling terms, detailed for the proven Memory polynomial modeling and linearization scheme.

The evolution of wireless technology has necessitated the support of multiple communication standards by mobile devices. At present, multiple chipsets/radios operating at predefined sets of modulation schemes, frequency bands, bandwidths and output power levels are used to achieve this objective. This leads to higher component counts, increased cost and limits the capacity to cope with future communication standards. In order to tackle different wireless standards using a single chipset, digital circuits have been increasingly deployed in radios and demonstrated re-configurability in different modulation schemes (multimode) and frequency bands (multiband). Despite efforts and progress made in digitizing the entire radio, the power amplifier (PA) is still designed using an conventional approach and has become the bottleneck in digital transmitters, in terms of low average power efficiency, poor compatibility with modern CMOS technology and limited re-configurability. This research addresses these issues from two aspects. The first half of the thesis investigates signal encoding issues between the modulator and PA. We propose, analyze and evaluate a new hybrid amplitude/time signal encoding scheme that significantly improves the coding efficiency and dynamic range of a digitally modulated power amplifier (DMPA) without significantly increasing design complexity. The proposed hybrid amplitude/time encoding scheme combines both the amplitude domain and the time domain to optimally encode information. Experimental results show that hybrid amplitude/time encoding results in a 35% increase in the average coding efficiency with respect to conventional time encoding, and is only 6.7% lower than peak efficiency when applied to a Wireless Local Area Network (WLAN) signal with a peak to average power ratio equal to 9.9 dB. A new DMPA architecture, based on the proposed hybrid encoding, is also proposed. The second half of this thesis presents the design, analysis and implementation of a CMOS PA that is amenable to the proposed hybrid encoding scheme. A multi-way current mode class-D PA architecture has been proposed and realized in 130 nm CMOS technology. The designed PA has satisfied the objectives of wide bandwidth (1.5 GHz - 2.7 GHz at 1 dB output power), and high efficiency (PAE 63%) in addition to demonstrating linear responses using the proposed digital encoding. A complete digital transmitter combining the encoder and the multi-way PA was also investigated. The overall efficiency is 27% modulating 7.3 dB peak to average power ratio QAM signals.

This thesis addresses the potential of implementing watt-level class-AB Power Amplifier (PA) for WLAN in 65 nm CMOS technology, at 2.4 GHz frequency. In total, five PAs have been compared, where the examined parameters were output power (Pout), linearity, power added efficiency (PAE), and area consumption. Four PAs were implemented using conventional cascode topology with different combination of transistors sizes in 65nm CMOS, and one PA using a high-voltage Extended Drain MOS (EDMOS) device, implemented in the same 65 nm CMOS with no process or mask changes. All schematics were created using Cadence Virtuoso CAD tools. The test benches were created using the Agilent's Advance Design System ( ADS) and simulated with the ADS-Cadence dynamic link. The simulation results show that the EDMOS PA (L=350 nm) has the smallest area, but has harder to reach the required Pout. Cascode no. 3 (L= 500,260 nm) has the best Pout (29.1 dBm) and PAE (49.5 %). Cascode no. 2 (L= 500,350 nm) has the best linearity (low EVM). Cascode no. 1 (L=500,500 nm) has low Pout (27.7 dBm). Cascode no.4 (L=500,60 nm) has very bad linearity. The thesis also gives an overview for CMOS technology, discusses the most important aspects in RF PAs design, such as Pout, PAE, gain, and matching networks. Different PA classes are also discussed in this thesis.

Power-amplifier efficiency is a significant issue for the overall efficiency of most wireless system. Therefore, currently there are different kind of Switched mode power amplifiers are developed which are showing very high efficiency also at higher frequencies but all of these amplifiers are subjected to drive with the constant envelope signals. Whereas, for the increasing demand of high data rate transmissions in wireless communication there are some new modulation schemes are introduced and which are generating no more a constant envelope signal but a high peak to average power signal. Therefore, recently a new technique is proposed called the burst mode operation for operating the switched mode power amplifiers efficiently while driven by a high peak to average power signal.   The purpose of this master thesis work was to review the theory of this burst mode operation and some basic investigations of this theory on switched mode power amplifiers were performed in simulation environments. The amplifiers of class D, inverse D, DE and J are studied. The thesis work was mainly carried out by ADS and partly in MATLAB SIMULINK environment. Since this burst mode operation is a completely new technique therefore a new Harmonic balance simulation setups in ADS and Microwave Office are developed to generate the RF burst signals.   A Class J amplifier based on LDMOS technique is measured by a 16 carrier multi-tone signal having peak to average power ratio of 7 dB and achieved the drain efficiency of 50% with -30 dBc linearity at 946 MHz.

This master's thesis addresses two main problems. The first is how to suppress a common mode voltage that appears for current shunts, and the second how to let a voltage divider work under an unloaded condition to prevent loading errors and thereby a decreased measurement accuracy. Both these problems occurs during calibration of power meters, and verification of current shunts and voltage dividers. To the first problem three alternative solutions are presented; prototype a proposed instrumentation amplifier circuit, evaluate the commercial available instrumentation amplifier Analog Devices AD8130 or let the voltage measuring device suppress the common mode voltage. It is up to the researchers at SP to choose a solution. To address the second problem, a prototype buffer amplifier is built and verified. Measurements of the buffer amplifier show that it performs very well. At 100 kHz, the amplitude error is less than 20 μV/V, the phase error is less than 20 μrad, and the input Rp is over 10 MΩ. This is performance in line with the required to make accurate measurements possible at 100 kHz and over that.

The work describes the development of a reliable device for profiling anion beam in the intensity cross section. A sensor head consisting of a Faradaycup in combination with a Channel Electron Multiplier was designedand built together with electronics including power supply and front endelectronics. The design was chosen considering financial and long term lifeaspects. Testing, first calibration and error analysis were done using the ionbeam facilities where the unit is supposed to be installed permanently. Theprofiling system performed as designed and the profile of the ion beam couldbe measured reliably with an accuracy down to the femto ampere range.

This thesis work describes the implementation perspective of an integrated high efficiency DC-DC converter implemented in 65 nm CMOS. The implemented system employs the Buck converter topology to down-convert the input battery voltages. This converter offers its use as a power management unit in portable battery operated devices. This thesis work includes the description of a basic Buck converter along with the various key equations involved which describe the Buck operation as well as are used to deduce the requirements for the various internal building blocks of the system. A detailed description of the operation as well as the design of each of the building blocks is included. The implemented system can convert the input battery voltage in the range of 2.3 V to 3.6 V into an output supply voltage of 1.6 V. The system uses dual-mode feedback control to maintain the output voltage at 1.6 V. For the low load currents the PFM feedback control is used and for the higher load currents the PWM feedback control is used. This converter can supply load currents from 0 to 300 mA with efficiency above 85%. The static line regulation of the system is < 0.1% and the load regulation of the system is < 0.3%. A digital soft-start circuit is implemented in this system. The system also includes the capability to trim the output voltage in ~14 mV steps depending on the 4-bit input digital code.

Noise contribution in nonlinear systems is very different from that in linear systems. The noise effects in nonlinear systems can be complicated and not obvious to predict. In this thesis, the focus was on the noise contribution in nonlinear systems when measuring with the nonlinear vector network analyzer (NVNA). An additional noise source together with a single sinewave signal was fed into the input of the amplifier and the performance was studied. The input power of the amplifier is considered to be the sum of the noise power and the signal power. The variation of the 1 dB compression point and the third order interception point as functions of the added noise power were studied. From the measured results in this thesis, the 1 dB compression point referred to the output power will decrease when increasing the added noise power at the input of the amplifier. The contribution of the added noise to the 1 dB compression point of an amplifier is considered dual: with the added noise the linear regression lines of the AM/AM curves are changed, and due to hard clipping the useful output power is reduced. As a result of those two effects, the added noise made the compression start at a lower power level. When the added noise reaches a certain level, the 1 dB compression point is hard to measure. Thus when performing nonlinear measurements, the noise effects should be taken into considerations and further studies are required to get better understanding of the system’s behavior in noisy environment.

In this master degree work, a digital attenuator and a low noise amplifier (LNA) have been designed and integrated with the RF front-end receiver for IEEE 802.11b Wireless LAN standard. Firstly, the 4-bit digitally controlled attenuator has been designed with theattenuation range of 50 to 80 dB and reflection coefficient less than -25 dB. Next, the single stage wide band low noise amplifier with voltage gain larger than 14 dB and noise figure below 4 dB has been designed to operate at frequency 2.4 GHz. Finally, the integration with a down-conversion mixer has been done and evaluated its performance. The attenuator and low noise amplifier desired in this thesis have been implemented using standard CMOS 0.35µm technology and validated by the simulation tools Cadence Spectre-RF.