This report has been written at SAAB Bofors Dynamics (SBD) AB in Gothenburg at the department of optronic systems. In military observation operations, a target to hit is chosen by illumination of a laser designator. From the targetpoint laser radiation is reflected on a detector that helps identify the target. The detector is a semiconductor PIN-type that has been investigated in a laboratory environment together with a specially designed laser source. The detector is a photodiode and using purchased components, circuits for both the photodiode and the laserdiode has been designed and fabricated. The bandwidth of the op-amp should be about 30 MHz, in the experiments a bandwidth of 42 MHz was used. Initially the feedback network, which consists of a 5.6 pF capacitor in parallel with a 1-kohm resistor determined the bandwidth. To avoid the op-amp saturate under strong illuminated laser radiation the feedback network will use a 56-pF capacitor and a 100-ohm resistor respectively. The laser should be pulsed with 10-20 ns width, 10 Hz repetition frequency, about 800 nm wavelength and a maximum output power of 80 mW. To avoid electrical reflection signals at measurement equipment connections, the laser circuit includes a resistor of about 50 ohm, that together with the resistance in the laserdiode forms the right termination that eliminate the reflection signals. The wire-wound type of resistor shall be avoided in this application and instead a surface mounted type was beneficial with much lower inductance. The detector showed a linear behaviour up to 40-mW optical power. Further investigation was hindered by the breakdown of the laserdiodes. The function generator limits the tests to achieve 80 mW in light power. In different experiments the responsivity of the photodiode is different from the nominal value, however it would have required more time to investigate the causes.

High-peak power laser systems are defined along with a brief introduction of the technology used in their development and application to the project. A review of concepts surrounding optical pulses, focusing on the particular phenomena involved with the ultrafast, follows. Numerical models involving optical pulses are introduced and verified. An extensive description of the laser system is presented, including models used in its design. Data verifying the correct operation of the laser system is presented and interpreted. A dispersion compensation system, including a function model, is introduced, and its application to the laser system is analyzed. An introduction to pulse characterization techniques is presented followed by the design and verification of two different characterization devices. Experiments utlizing the dispersion compensation system and pulse characterization devices are presented and the results are interpreted. Conclusions are made regarding the performance of the laser system models and pulse characterization devices, along with suggested improvements for each. The results of the experiments are discussed including suggestions for future work.

Radio frequency (RF) communications are limited to a number of frequency bands scattered over the radio spectrum. Applications over such bands increasingly require more versatile, data extensive wireless communications that leads to the necessity of high bandwidth efficient interfaces, operating over wideband frequency ranges. Whether for a base station or mobile device, the regulations and adequate transmission of such schemes place stringent requirements on the design of transmitter front-ends. Increasingly strenuous and challenging hardware design criteria are to be met, especially so in the design of power amplifiers (PA), the bottle neck of the transmitter’s design tradeoff between linearity and power efficiency. The power amplifier exhibits a nonideal behavior, characterized by both nonlinearity and memory effects, heavily affecting that tradeoff, and therefore requiring an effective linearization technique, namely Digital Predistortion (DPD). The effectiveness of the DPD is highly dependent on the modeling scheme used to compensate for the PA’s nonideal behavior. In fact, its viability is determined by the scheme’s accuracy and implementation complexity. Generic behavioral models for nonlinear systems with memory have been used, considering the PA as a black box, and requiring RF designers to perform extensive testing to determine the minimal complexity structure that achieves satisfactory results. This thesis first proposes a direct systematic approach based on the parallel Hammerstein structure to determine the exact number of coefficients needed in a DPD. Then a physical explanation of memory effects is detailed, which leads to a close-form expression for the characteristic behavior of the PA entirely based on circuit properties. The physical expression is implemented and tested as a modeling scheme. Moreover, a link between this formulation and the proven behavioral models is explored, namely the Volterra series and Memory Polynomial. The formulation shows the correlation between parameters of generic behavioral modeling schemes when applied to RF PAs and demonstrates redundancy based on the physical existence or absence of modeling terms, detailed for the proven Memory polynomial modeling and linearization scheme.

In wireless communication systems, multiple standards have been implemented to meet the past and present demands of different applications. This proliferation of wireless standards, operating over multiple frequency bands, has increased the demand for radio frequency (RF) components, and consequently power amplifiers (PA) to operate over multiple frequency bands. In this research work, a systematic approach for the synthesis of a novel dual-band matching network is proposed and applied for effective design of PA capable of maintaining high power efficiency at two arbitrary widely spaced frequencies. The proposed dual-band matching network incorporates two different stages. The first one aims at transforming the targeted two complex impedances, at the two operating frequencies, to a real one. The second stage is a dual-band filter that ensures the matching of the former real impedance to the termination impedance to 50 Ohm. Furthermore, an additional transmission line is incorporated between the two previously mentioned stages to adjust the impedances at the second and third harmonics without altering the impedances seen at the fundamental frequencies. Although simple, the harmonic termination control is very effective in enhancing the efficiency of RF transistors, especially when exploiting the Class J design space. The proposed dual-band matching network synthesis methodology was applied to design a dual-band power amplifier using a packaged 45 W gallium nitride (GaN) transistor. The power amplifier prototype maintained a peak power efficiency of about 68% at the two operating frequencies, namely 800 MHz and 1.9 GHz. In addition, a Volterra based digital predistortion technique has been successfully applied to linearize the PA response around the two operating frequencies. In fact, when driven with multi-carrier wideband code division multiple access (WCDMA) and long term evolution (LTE) signals, the linearized amplifier maintained an adjacent channel power ratio (ACPR) of about 50 dBc and 46 dBc, respectively.

The trend toward higher-level circuit integration is the result of demand for lower cost and smaller feature size. The goal of this trend is to have a single-chip solution, in which analog and digital circuits are placed on the same die with advanced CMOS technology. The complete integration of a system may include a digital processor, memory, ADC, DAC, signal conditioning amplifiers, frequency translation, filtering, reference voltage/current generator, etc. Although advanced fabrication technology benefits digital circuits, it poses great challenges for analog circuits. For instance, the scaling of CMOS devices degrades important analog performance such as output resistance, lowering amplifier gain. Simply lowering the power supply voltage in analog circuits does not necessarily result in lower power dissipation. The many design constraints common to the design of analog circuits makes it difficult to curb their power consumption. This is especially true for already complicated analog systems like ADCs; reducing their appetite for power requires careful analysis of system requirements and special strategies. This thesis describes a 10bits 100-MS/s low-voltage pipelined analog-to-digital converter (ADC), which consists of 8-stage-pipelined low resolution ADCs and a 2-bit flash ADC. Several critical technologies are adopted to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, folded-cascode gain-boosted amplifiers and so on. The ADC is designed in a 90nm CMOS technology with a 1.2V supply voltage.

The objective of this thesis is aimed at the design of low noise amplifier (LNA) for an ultra-wideband (UWB) receiver system using standard 0.18um CMOS process. A two amplified stage topology is proposed in the low noise amplifier. The first stage introduces inductively source degeneration, it can achieve wideband input impedance matching. The second stage introduces traditional CS configuration, it can improve the forward gain (S21). The second stage also used L-C section for output match. In order to improve the gain at high frequency, we introduces the series peaking between the first stage and second stage. We use the resistive-feedback between second stage and output, it can achieve wideband output impedance matching. The total power dissipation of the low noise amplifier is about 16.5mW at power supply 1.5 volt and the chip size is 920*940mm2. The simulated result shows that S11 is under -9dB, S22 is under -10dB, the forward gain S21 is 11.63dB~12.56dB at 3.1-10.6GHz, the reverse isolation S12 is under -32dB, and the noise figure is3.3dB~3.96dB.

This thesis proposes a dB-linear programmable variable gain amplifier (VGA) and a voltage peak detector with digital calibration for FPW-based antibody sensing system. In the first topic, a dB-linear programmable variable gain amplifier is proposed. By using two source followers as the input terminals, input signals with very low DC offset could be received. The linear local-feedback transconductors are employed to be trans-condurctor-stage and load-stage. Besides, a reconfiguration method is used to reduce the layout area and improve the linearity of the gain to attain gain error less than 0.86 dB measured on silicon. In the second topic, a voltage peak detector with digital calibration is proposed. The voltage peak of the input sine-wave signal is sampled and held by using an integra-tor, a digital-to-analog converter, and a voltage comparator to generate a square-wave signal. Besides, the voltage error caused by the propagation delay could be calibrated by the proposed digital calibration method. The frequency of input signal is up to 20 MHz and the voltage error is justified to be less than 0.81 % by simulations.

Low size, low power, and wearable bio-signal recording systems require acquisition front-ends with high common-mode rejection for interference suppression and adjustable gain to provide an optimum signal level to a cascading analog-to-digital stage. This thesis presents the realization of microcontroller operated double-differential (DD) recording setup with automatic gain control (AGC) and automatic balance control, which can adjust the magnitude of recorded bio-potential signal to a target level and reject common-mode interference for full-bandwidth recording without filtering. Microcontroller code realizes the automatic control method of gain and balance adjustment by detecting, computing, and varying parameters to set timing clock pulses, which determine the gain magnitude and balance state. The automatic balance control compensates for imbalance in electrode interface impedance. The double-differential amplifier is implemented using two integrated variable gain amplifiers (ASIC) and one adder. Measured results of the variable gain amplifiers fabricated in 0.35 £gm CMOS technology show an input spot noise of 169 nV/¡ÔHz, a NEF below 10, and a circuit active area of 0.017 mm2 with a power consumption of 1.44 £gW. Measured results of the double-differential amplifier setup confirm interference suppression of 25.7 dB, tunable gain range of 39.6 dB, and 239 nV/¡ÔHz noise assuming ¡Ó10% interface mismatch. Practical measured examples incorporating the chips confirm gain control suitable for bio-potential recording and interference suppression in a balanced DD arrangement for electrocardiogram and electromyogram recording.

In this work, a highly linear broadband Low Noise Amplifier (LNA) is presented. The linearity issue in broadband Radio Frequency (RF) front-end is introduced, followed by an analysis of the specifications and requirements of a broadband LNA through consideration of broadband, multi-standard front-end design. Metal-Oxide- Semiconductor Field-Effect Transistor (MOSFET) non-linearity characteristics cause linearity problems in the RF front-end system. To solve this problem, feedback and the Derivative Superposition Method linearized MOSFET. In this work, novel linearization approaches such as the constant current biasing and the Derivative Superposition Method using a triode region transistor improve linearization stability against Process, Supply Voltage, and Temperature (PVT) variations and increase high power input capability. After analyzing and designing a resistive feedback LNA, novel linearization methods were applied. A highly linear broadband LNA is designed and simulated in 65nm CMOS technology. Simulation results including PVT variation and the Monte Carlo simulation are presented. We obtained -10dB S11, 9.77dB S21, and 4.63dB Noise Figure with IIP3 of 19.18dBm for the designed LNA.

The summing amplifier and the quantizer form two of the most critical blocks in a continuous time delta sigma (CT ΔΣ) analog-to-digital converter (ADC). Most of the conventional CT ΔΣ ADC designs incorporate a voltage summing amplifier and a voltage-mode quantizer. The high gain-bandwidth (GBW) requirement of the voltage summing amplifier increases the overall power consumption of the CT ΔΣ ADC. In this work, a novel method of performing the operations of summing and quantization is proposed. A current-mode summing stage is proposed in the place of a voltage summing amplifier. The summed signal, which is available in current domain, is then quantized with a 3-bit current mode flash ADC. This current mode summing approach offers considerable power reduction of about 80% compared to conventional solutions [2]. The total static power consumption of the summing stage and the quantizer is 5.3mW. The circuits were designed in IBM 90nm process. The static and dynamic characteristics of the quantizer are analyzed. The impact of process and temperature variation and mismatch tolerance as well as the impact of jitter, in the presence of an out-of-band blocker signal, on the performance of the quantizer is also studied.