The objective of this research is to explore high-speed analog-to-digital converters (ADCs) using silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for wireless digital receiver applications. The stringent requirements of ADCs for the high-performance next-generation wireless digital receiver include (1) low power, (2) low cost, (3) wide input signal bandwidth, (4) high sampling rate, and (5) medium to high resolution. The proposed research achieves the objective by implementing high-performance ADC's key building blocks and integrating these building blocks into a complete sigma-delta analog-to-digital modulator that satisfies the demanding specifications of next-generation wireless digital receiver applications. The scope of this research is divided into two main parts: (1) high-performance key building blocks of the ADC, and (2) high-speed sigma-delta analog-to-digital modulator. The research on ADC's building blocks includes the design of two high-speed track-and-hold amplifiers (THA) and two wide-bandwidth comparators operating at the sampling rate > 10 GS/sec with satisfying resolution. The research on high-speed sigma-delta analog-to-digital modulator includes the design and experimental characterization of a high-speed second-order low-pass sigma-delta modulator, which can operate with a sampling rate up to 20 GS/sec and with a medium resolution. The research is envisioned to demonstrate that the SiGe HBT technology is an ideal platform for the design of high-speed ADCs.

With the growing trend of wireless electronics, frequency spectrum is crowded with different applications. High data transfer rate solutions that operate in license-exempt frequency spectrum range are sought. The most promising candidate is the 60 GHz multi-giga bit transfer rate millimeter wave circuit. In order to provide a cost-effective solution, circuits designed in CMOS are implemented in a single SOC. In this work, a modeling technique created in Cadence shows an error of less than 3dB in magnitude and 5 degree in phase for a single transistor. Additionally, less than 3dB error of power performance for the PA is also verified. At the same time, layout strategies required for millimeter wave front-end circuits are investigated. All of these combined techniques help the design converge to one simulation platform for system level simulation. Another aspect enabling the design as a single SOC lies in integration. In order to integrate digital and analog circuits together, necessary peripheral circuits must be designed. An on-chip voltage regulator, which steps down the analog power supply voltage and is compatible with digital circuits, has been designed and has demonstrated an efficiency of 65 percent with the specific area constraint. The overall output voltage ripple generated is about 2 percent. With the necessary power supply voltage, gate voltage bias circuit designs have been illustrated. They provide feasible solutions in terms of area and power consumption. Temperature and power supply sensitivities are minimized in first two designs. Process variation is further compensated in the third design. The third design demonstrates a powerful solution that each aspect of variations is well within 10%. As the DC conditions are achieved on-chip for both the digital and analog circuits, digital and analog circuits must be connected together with a DAC. A high speed DAC is designed with special layout techniques. It is verified that the DAC can operate at a speed higher than 3 Gbps from the pulse-shaping FIR filter measurement result. With all of these integrated elements and modeling techniques, a high data transfer rate CMOS RF SOC operating at 60 GHz is possible.

Ultra-broadband Monolithic Microwave Integrated Circuit (MMIC) amplifiers find applications in multi-gigabit communication systems for 5G and millimeter wave measurement instrumentation systems. The aim of the research was to achieve maximum bandwidth of operation of the amplifier from the foundry process used and high reverse isolation ( < -25.0 dB) across the whole bandwidth. To achieve this, several design variations of DC - 110 GHzMMIC Cascode TravellingWave Amplifier (TWA) on 100 nm AlGaAs/GaAs pHEMT process were done for application in next generation instrumentation and high data transfer rate (100 Gb/s) optical modulator systems. The foundry service and device models used for the design are of the WINPP10-10 process from WIN Semiconductor Corp., Taiwan, a commercial and highly stable process. The cut-off frequency ft and maximum frequency of oscillation fmax for this process are 135 GHz and 185 GHz respectively. Thus, the design was aimed at pushing the ultimate limits of operation for this process. The design specifications were targeted to have S21 = 9.0 to 10.0 ± 1.0 dB, S11 & S22 ≤ -10.0 dB and S12 ≤ -25.0 dB in the whole frequency range. In order to achieve the targeted RF performance, it is imperative to have accurate transistor models over the frequency range of operation, transistor configuration mode and operating bias points. Using smaller periphery transistors results in lower extrinsic & intrinsic input and output capacitances that lead to achieving very wide band performance. Thus, device sizes as small as 2x10 μm were used for the design. A cascode topology, which is a series connection of a common-source and common-gate field effect transistor (FET), was used to achieve large bandwidth of operation, high reverse isolation and high input and output impedance. Using very small periphery devices at cascode bias points posed limitation in the design in terms of accuracy of transistor models under these conditions, specifically at high frequencies i.e., above 50 GHz. One of the major systemrequirements for the application of MMIC ultra-broadband amplifiers in instrumentation is to achieve and maintain high reverse isolation (≤ -25.0 dB) over the whole frequency range of operation which cannot be achieved alone by the cascode topology and new design techniques have to be devised. These twomajor challenges, namely high frequency small periphery FET model modification & development and design technique to achieve high reverse isolation in ultra-broadband frequency range have been addressed in this research.

abstract: Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

This thesis contains the description of well-known methods and principles dealing with the measurement of the flow-velocity of fluids. Furthermore, it contains the description of the development of the mobile flow-meter, including the realization and the technical description of the device. The thesis describes the advantages and disadvantages of the above mentioned flow-meter. The last part of the thesis is dedicated to the calibration of the device and to the possible practical use of the flow-meter.

Ce travail concerne la linéarisation des amplificateurs de haute puissance en utilisant la pré-distorsion numérique. L’amplificateur de haute puissance est un composant non-linéaire. La pré-distorsion numérique adaptative en bande de base est un technique efficace pour linéariser ses non-linéarités et ses effets de mémoire. Les modèles de la pré-distorsion numérique de basse complexité sont étudiés dans cette thèse. Un algorithme est proposé pour déterminer une structure optimale de modèle uni-étage ou multi-étage en prenant compte du compromis entre la précision de modélisation et la complexité. La structure cascadée, qui est avantageuse en complexité comparé avec celle d'uni-étage, est étudiée avec des méthodes d'identifications différentes. En termes d'implémentations expérimentales, l'étude d'impact des choix de gain différents est approfondie dans cette thèse. Toutes les études ont été évaluées par un amplificateur de puissance Doherty / This dissertation contributes to the linearization techniques of high power amplifier using digital predistortion method. High power amplifier is one of the most nonlinear components in radio transmitters. Unfortunately, for most current types of power amplifiers, a good efficiency is obtained at the price of a poor linearity especially with modern communication waveforms. Baseband adaptive digital predistortion is a powerful technique to linearize the power amplifiers and allows to push the power amplifier operation point towards its high efficiency region. Linearization of power amplifiers using digital predistortion with low complexities is the focus of this dissertation. An algorithm is proposed to determine an optimal model structure of single-stage or multi-stage predistorter according to a trade-off between modeling accuracy and model complexity. Multi-stage cascaded digital predistortions are studied with different identification methods, which have advantages on complexity of model identification compared with single-stage structure. The linearization performances are validated by experimental implementations on test bench. In terms of experimental implementations, this dissertation studies the impact of different gain choices on linearized power amplifier. All studies are evaluated with a Doherty power amplifier

O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico. / The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.

The geometry of CMOS processes has decreased in a steady pace over the years at the same time as the complexity has increased. Even if there are more requirements on the designer today, the main goal is still the same: to minimize the occupied area and power dissipation. This thesis investigates if a prediction of the costs in future CMOS processes can be made. By implementing several processes on a test circuit we can see a pattern in area and power dissipation when we change to smaller processes. This is done by optimizing a two-stage operational transconductance amplifier on basis of a given specification. A circuit optimization tool evaluates the performance measures and costs. The optimization results from the area and power dissipation is used to present a diagram that shows the decreasing costs with smaller processes and also a prediction of how small the costs will be for future processes. This thesis also presents different optimization tools and a design hexagon that can be used when we struggle with optimization trade-offs.

O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico. / The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.

abstract: Kinetic inductance springs from the inertia of charged mobile carriers in alternating electric fields and it is fundamentally different from the magnetic inductance which is only a geometry dependent property. The magnetic inductance is proportional to the volume occupied by the electric and magnetic fields and is often limited by the number of turns of the coil. Kinetic inductance on the other hand is inversely proportional to the density of electrons or holes that exert inertia, the unit mass of the charge carriers and the momentum relaxation time of these charge carriers, all of which can be varied merely by modifying the material properties. Highly sensitive and broadband signal amplifiers often broaden the field of study in astrophysics. Quantum-noise limited travelling wave kinetic inductance parametric amplifiers offer a noise figure of around 0.5 K ± 0.3 K as compared to 20 K in HEMT signal amplifiers and can be designed to operate to cover the entire W-band (75 GHz – 115 GHz).The research cumulating to this thesis involves applying and exploiting kinetic inductance properties in designing a W-band orthogonal mode transducer, quadratic gain phase shifter with a gain of ~49 dB over a meter of microstrip transmission line. The phase shifter will help in measuring the maximum amount of phase shift ∆ϕ_max (I) that can be obtained from half a meter transmission line which helps in predicting the gain of a travelling wave parametric amplifier. In another project, a microstrip to slot line transition is designed and optimized to operate at 150 GHz and 220 GHz frequencies, that is used as a part of horn antenna coupled microwave kinetic inductance detector proposed to operate from 138 GHz to 250 GHz. In the final project, kinetic inductance in a 2D electron gas (2DEG) is explored by design, simulation, fabrication and experimentation. A transmission line model of a 2DEG proposed by Burke (1999), is simulated and verified experimentally by fabricating a capacitvely coupled 2DEG mesa structure. Low temperature experiments were done at 77 K and 10 K with photo-doping the 2DEG. A circuit model of a 2DEG coupled co-planar waveguide model is also proposed and simulated. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2016