Thesis (Ph. D.)--University of Chicago, 1900.

No description available.

The security of service, confidential data, and intellectual property are threatened by physical attacks, which usually include reading and tampering the data. In many cases, attackers can have access to the tools and equipment that can be used to read the memory or corrupt it, either by invasive or non-invasive means. The secret keys used by cryptographic algorithms are usually stored in a memory. Physical unclonable functions (PUFs) are promising to deal with such vulnerabilities since, in the case of PUFs, the keys are generated only when required and do not need to be stored on a powered-off chip. PUFs use the inherent variations in the manufacturing process to generate chip-unique output sequences (response) to a query (challenge). These variations are random, device-unique, hard to replicate even by the same manufacturer using identical process, equipment and settings, and supposed to be static, making the PUF an ideal candidate for generation of cryptographic keys. This thesis work focuses on a delay-based PUF called arbiter PUF. It utilizes the intrinsic propagation delay differences of two symmetrical paths. In this work, an arbiter PUF implemented in Altera FPGA has been evaluated. The implementation includes Verilog HDL coding, placement and routing, and the communication methods between PC and FPGAs to make testing more efficient. The experimental results were analyzed based on three criteria, reliability, uniqueness, and uniformity. Experimental results show that the arbiter PUF is reliable with respect to temperature variations, although the bit error rate increases as the temperature difference becomes larger. Results also reveal that the uniqueness of the PUFs on each FPGA device is particularly low but on the other hand, the proportions of different response bits are uniform after symmetric routing is performed. / Tjänstens säkerhet, konfidentiella uppgifter och immateriell egendom hotas av fysiska attacker, som vanligtvis inkluderar läsning och manipulering av uppgifterna. I många fall kan angripare ha tillgång till de verktyg och utrustning som kan användas för att läsa minnet eller skada det , antingen med invasiva eller icke-invasiva medel. De hemliga nycklarna som används av kryptografiska algoritmer lagras vanligtvis i ett minne. Fysiska okonabla funktioner (PUF: er) lovar att hantera sådana sårbarheter eftersom, för PUF: er, nycklarna genereras endast när det behövs och inte behöver lagras på ett avstängd chip. PUF: er använder de inneboende variationerna i tillverkningsprocessen för att generera chip-unika utgångssekvenser (svar) på en fråga (utmaning). Dessa variationer är slumpmässiga, enhetsunika, svårt att kopiera till och med av samma tillverkare med identisk process, utrustning och inställningar, och antas vara statisk, vilket gör PUF till en idealisk kandidat för generering av kryptografiska nycklar. Detta avhandlingsarbete fokuserar på en fördröjningsbaserad PUF som kallas arbiter PUF. Den använder de inneboende utbredningsfördröjningsskillnaderna för två symmetriska vägar. I detta arbete har en arbiter PUF implementerad i Altera FPGA utvärderats. Implementeringen inkluderar Verilog HDLkodning, placering och routing och kommunikationsmetoderna mellan PC och FPGA för att effektivisera testningen. De experimentella resultaten analyserades baserat på tre kriterier, tillförlitlighet, unikhet och enhetlighet. Experimentella resultat visar att arbiter PUF är tillförlitlig med avseende på temperaturvariationer, även om bitfelfrekvensen ökar när temperaturdifferensen blir större. Resultaten avslöjar också att unikheten hos PUF: erna på varje FPGA-enhet är särskilt låg men å andra sidan är proportionerna av olika svarbitar enhetliga efter att symmetrisk dirigering har utförts.

Este estudio se basa en la premisa de que la interpretación es una actividad social y que por tanto necesita describirse y explicarse en referencia al contexto cultural, político y social del escenario en que el intérprete opera. Se estudian los aspectos sociopolíticos de la interpretación en el Tribunal Militar Internacional para el Lejano Oriente (TMILO, 1946-1948) mediante una investigación archivística e histórica de la organización de la interpretación y un estudio de caso del comportamiento de los lingüistas (especialistas del idioma) que trabajaron en el proceso de interpretación. Tras exponer resumidamente la organización de la interpretación, este estudio analiza las características propias de interpretar en el TMILO. En primer lugar, investiga por qué el tribunal organizó la interpretación de forma que tres grupos diferentes social y étnicamente se encargaban de tres funciones diferentes: los ciudadanos japoneses actuaban de intérpretes en el procedimiento, los nisei (Japoneses- americanos de segunda generación) monitorizaban la actuación de los intérpretes, y oficiales militares caucasianos, en calidad de peritos lingüísticos, decidían las discrepancias en las traducciones e interpretaciones. Este estudio desvela que la carencia de lingüistas americanos competentes condujo al uso de ciudadanos japoneses como intérpretes; y que dicha estructura jerárquica funcionaba como una muestra de autoridad y para impedir la "mala fe" que, supuestamente, albergaban los intérpretes japoneses y los monitores nisei. En segundo lugar, se aplica el concepto de "normas negociadas" para examinar cómo se desarrollaron los procesos de interpretación durante el primer año del TMILO en que ninguno de los lingüistas había recibido formación como intérprete profesional y los usuarios de la interpretación no estaban familiarizados con su funcionamiento. Este examen subraya el aspecto interactivo de la creación de normas y las limitaciones cognitivas del intérprete como un factor de dicho proceso. Por último, se examina la ambigua y compleja posición de los monitores nisei. Fueron contratados por un gobierno que les había tratado injustamente como "enemigos ajenos", en un juicio contra los antiguos líderes de la patria de sus padres; y usaban habilidades arraigadas en su herencia para trabajar como monitores.Se estudia el comportamiento de los lingüistas durante los testimonios de Hideki Tojo y otros testigos japoneses centrándonos en la naturaleza de las interjecciones de los monitores y de los intérpretes y las interacciones entre los lingüistas y otros participantes del juicio. Algunos de los resultados apoyan la hipótesis que conecta el comportamiento de los lingüistas con su posición provisional en la constelación de poder de este escenario.En último lugar de la jerarquía, los intérpretes japoneses hablan en contadas ocasiones por cuenta propia y casi nunca ponen objeciones a las interjecciones aparentemente innecesarias o incluso erróneas de los monitores. Dada la situación intermedia de los monitores en el sistema de interpretación, sus aparentemente excesivas interjecciones en japonés pueden explicarse como una muestra de autoridad hacia los intérpretes japoneses y como un mensaje al tribunal (que no entendía japonés) de que estaban trabajando con eficacia corrigiendo errores de interpretación. La menor frecuencia de interjecciones en inglés por parte de estos monitores puede ser debida a la consideración por la preocupación de sus patrones por la falta de tiempo. El perito lingüístico no se involucraba en ninguna actividad espontánea, pero su presencia al lado de la fiscalía y sus anuncios de resoluciones de disputas lingüísticas en el tribunal debe haber reforzado la imagen de que el ejército estadounidense estaba al mando.Los resultados de este estudio refuerzan la idea de que la interpretación es una práctica social. La influencia de los aspectos sociopolíticos del escenario se hace evidente en la organización de la interpretación. Además, la información disponible sugiere que el comportamiento de los lingüistas era consecuente con su posición relativa en la jerarquía. El autor espera que algunos de los temas tratados en este estudio, como la confianza, la ética, las relaciones de poder y las normas negociadas, sean revisados para una mayor comprensión de los temas relacionados con el idioma en nuestra sociedad actual. / This study is based on the premise that interpreting is a social activity, which therefore needs to be described and explained with reference to the social, political and cultural context of the setting in which the interpreter operates. Sociopolitical aspects of interpreting at the International Military Tribunal for the Far East (IMTFE, 1946-1948) are studied through historical and archival research of the interpreting arrangements and a case study on the behavior of linguists (language specialists) who worked in the interpreting process during the testimonies of Hideki Tojo and other Japanese witnesses. Three sets of concepts are applied to analyze three salient features of interpreting at the IMTFE. Based on the notions of "trust, power and control", the historical and political context of the IMTFE and the social and cultural backgrounds of each linguist group are examined to explore why the tribunal devised the interpreting arrangements in which three ethnically and socially different groups of linguists engaged in three different functions: interpreter, monitor and language arbiter. The concept of "negotiated norms" is applied to discuss the interactional aspect of how the interpreting procedures developed over the initial stage of the trial, with the interpreters' cognitive constraints as a factor in that process. Cronin's notion (2002) of "autonomous and heteronomous interpreters" is drawn on to discuss the complex position of the Japanese American linguists who worked as monitors. The nature of interjections by the monitors and interpreters and the interactions between the court and each linguist group during the interpreted testimonies of Japanese witnesses are examined. Findings of this analysis support the hypothesis which links interpreters' choices, strategies and behavior to their awareness of where they stand in the power constellation of the interpreted event.

Thesis (Ph. D.)--University of Chicago, Dept. of Classical Languages and Literatures, December 2003. / Includes bibliographical references. Also available on the Internet.

Physical Unclonable Functions are a unique class of circuits that leverage the inherentvariations in manufacturing process to create unique,unclonableIDs and secret keys.The distinguishing feature of PUFs is that even an untrusted foundry cannot create a copy of the circuit as it is impossible to control the manufacturing process variations.PUFs can operate reliably in presence of voltage and temperature variations. In thisthesis, weexplorethe security offered by PUFs and tradeoffs between different metrics such as uniqueness, reliability and energy consumption.Benefits of sub-threshold PUF operation and the use of delay based Arbiter PUFs and ring oscillator PUFs in low power applications is evaluated. As we scale into lower technology nodes, there exists sufficient inter chip variation that enables each IC to be identified securely.The impact of scaling on the identification capabilities of a PUF and its reliability has been demonstrated in this work by analyzing the behavior of an Arbiter PUF in 45nm, 32nm and 22nm technology nodes. Further,the Arbiter PUF design has been implemented on a test-chip and fabricated using 45nm industry models andresults from post silicon validation are presented. Finally, we investigate a new class of PUF circuits in this work, that provide better security against machine learning based software modeling attacks. The strong identification capabilities and sufficiently high reliability offered by these PUF circuits make them promising candidates for future applications requiring securehardware cryptographic primitives.

The objective of this thesis is to automate the design of round-robin arbiter logic. The resulting arbitration logic is more than 1.8X times faster than the fastest prior state-of-the-art arbitration logic the author could find reported in the literature. The generated arbiter implemented in a single chip is fast enough in 0.25ьm CMOS technology to achieve terabit switching with a single chip computer network switch. Moreover, this arbiter is applicable to crossbar (Xbar) arbitration logic. The generated Xbar, customized according to user specifications, provides multiple communication paths among masters and slaves. As the number of transistors on a single chip increases rapidly, there is a productivity gap between the number of transistors available in a chip and the number of transistors per hour a chip designer designs. One solution to reduce this productivity gap is to increase the use of Silicon Intellectual Property (SIP) cores. However, a SIP core should be customized before being used in a system different than the one for which it was designed. Thus, to reconfigure the SIP core, either an engineer must spend significant effort altering the core by hand or else an enhanced CAD tool can automatically customize the core according to customer specifications. In this thesis, we present SIP generator tools for arbiter and Xbar generation. First, we introduce a Round-robin Arbiter Generator (RAG). The RAG can generate a hierarchical Bus Arbiter (BA) which is faster than all known previous approaches. RAG can also generate a hierarchical Switch Arbiter (SA) which is faster than all known previous approaches. Using a 0.25ьm TSMC standard cell library from LEDA Systems, we show the arbitration time of a 32x32 SA and demonstrate that our SA meets the time constraint to achieve terabit throughput. Furthermore, using a novel token-passing hierarchical arbitration scheme, our 32x32 SA performs better than the Ping-Pong Arbiter and Programmable Priority Encoder by factors of 1.8X and 2.3X, respectively, with less power dissipation. Finally, we present an Xbar switch Generator (X-Gt) tool that automatically configures a crossbar for a multiprocessor System-on-a-Chip (SoC). An Xbar is generated in Register Transfer Level (RTL) Verilog HDL.

L'étude de différents bus de communination parallèle à usage multi-microprocesseur (bus SM 90, MULTIBUS, VME), ainsi que des techniques d'arbitrage associées, a conduit à s'intéresser à la compatibilité de l'arbitre de bus intégré ABC 90 de la SM 90 (dont les functionnalités sont les plus puissantes) avec les autres types de bus (MULTIBUS, VME). La première étape de l'étude se traduit par la proposition d'utilisation de l'ABC 90 comme organe d'allocation de bus dans différentes configurations d'architectures, et ce par adjonction d'éléments discrets. La seconde étape consiste à proposer un circuit intégré d'arbitre de bus multiprotocole en partant des spécifications de l'ABC 90 et en y intégrant les résultats obtenus dans la proposition précédente. La validation de ces deux propositions a été obtenue par simulation. / O estudo de diferentes "bus" de comunicação paralela utilizados em arquiteturas multi-microprocesssodores ("bus" das estruturas SM 90, MULTIBUS e VME), assim que suas técnicas de arbitragem respectivas, nos permitiram de conduzir nosso trabalho sobre o estudo de compatibilidade do circuito integrado arbitro de bus ABC 90 da estrutura SM 90 (cujas funções são as mais potentes) com os outros tipos de "bus" (MULTIBUS e VME). A primeira etapa de nosso estudo se traduz pela proposição de utilização do circuito ABC 90 com órgão de alocação de "bus" em diferentes configurações arquiteturais multi-microprocessadores através da introdução de componentes discretos. A segunda etapa consiste na proposição de um circuito integrado arbitro de "bus" multi-protocolos partindo das especificações do circuito ABC 90 e dos resultados obtidos pela primeira proposição. A validação das duas proposições sugeridas par este trabalho foi obtida através de simulações. / The existence of so many parallel communication multi-microprocessor buses (buses of the SM 90, MULTIBUS & VME structures) and their different arbiter techniques led us to study the compatibility of the integrated bus arbiter ABC 90 of the SM 90 (which presents the widest range of functions) with other types of buses MULTIBUS and VME). The first part of the study involved the feasibility of using the ABC 90 circuit as bus arbiter in different architectural configurations; this has been realized by the addition of discrete components. The second step consisted in the design of an integrated multi - protocol communication arbiter, as an extension of the ABC 90's specifications and based on the results obtained in the first part of the study. The validation of both proposals was carried out by simulation.

L'étude de différents bus de communination parallèle à usage multi-microprocesseur (bus SM 90, MULTIBUS, VME), ainsi que des techniques d'arbitrage associées, a conduit à s'intéresser à la compatibilité de l'arbitre de bus intégré ABC 90 de la SM 90 (dont les functionnalités sont les plus puissantes) avec les autres types de bus (MULTIBUS, VME). La première étape de l'étude se traduit par la proposition d'utilisation de l'ABC 90 comme organe d'allocation de bus dans différentes configurations d'architectures, et ce par adjonction d'éléments discrets. La seconde étape consiste à proposer un circuit intégré d'arbitre de bus multiprotocole en partant des spécifications de l'ABC 90 et en y intégrant les résultats obtenus dans la proposition précédente. La validation de ces deux propositions a été obtenue par simulation. / O estudo de diferentes "bus" de comunicação paralela utilizados em arquiteturas multi-microprocesssodores ("bus" das estruturas SM 90, MULTIBUS e VME), assim que suas técnicas de arbitragem respectivas, nos permitiram de conduzir nosso trabalho sobre o estudo de compatibilidade do circuito integrado arbitro de bus ABC 90 da estrutura SM 90 (cujas funções são as mais potentes) com os outros tipos de "bus" (MULTIBUS e VME). A primeira etapa de nosso estudo se traduz pela proposição de utilização do circuito ABC 90 com órgão de alocação de "bus" em diferentes configurações arquiteturais multi-microprocessadores através da introdução de componentes discretos. A segunda etapa consiste na proposição de um circuito integrado arbitro de "bus" multi-protocolos partindo das especificações do circuito ABC 90 e dos resultados obtidos pela primeira proposição. A validação das duas proposições sugeridas par este trabalho foi obtida através de simulações. / The existence of so many parallel communication multi-microprocessor buses (buses of the SM 90, MULTIBUS & VME structures) and their different arbiter techniques led us to study the compatibility of the integrated bus arbiter ABC 90 of the SM 90 (which presents the widest range of functions) with other types of buses MULTIBUS and VME). The first part of the study involved the feasibility of using the ABC 90 circuit as bus arbiter in different architectural configurations; this has been realized by the addition of discrete components. The second step consisted in the design of an integrated multi - protocol communication arbiter, as an extension of the ABC 90's specifications and based on the results obtained in the first part of the study. The validation of both proposals was carried out by simulation.

L'étude de différents bus de communination parallèle à usage multi-microprocesseur (bus SM 90, MULTIBUS, VME), ainsi que des techniques d'arbitrage associées, a conduit à s'intéresser à la compatibilité de l'arbitre de bus intégré ABC 90 de la SM 90 (dont les functionnalités sont les plus puissantes) avec les autres types de bus (MULTIBUS, VME). La première étape de l'étude se traduit par la proposition d'utilisation de l'ABC 90 comme organe d'allocation de bus dans différentes configurations d'architectures, et ce par adjonction d'éléments discrets. La seconde étape consiste à proposer un circuit intégré d'arbitre de bus multiprotocole en partant des spécifications de l'ABC 90 et en y intégrant les résultats obtenus dans la proposition précédente. La validation de ces deux propositions a été obtenue par simulation. / O estudo de diferentes "bus" de comunicação paralela utilizados em arquiteturas multi-microprocesssodores ("bus" das estruturas SM 90, MULTIBUS e VME), assim que suas técnicas de arbitragem respectivas, nos permitiram de conduzir nosso trabalho sobre o estudo de compatibilidade do circuito integrado arbitro de bus ABC 90 da estrutura SM 90 (cujas funções são as mais potentes) com os outros tipos de "bus" (MULTIBUS e VME). A primeira etapa de nosso estudo se traduz pela proposição de utilização do circuito ABC 90 com órgão de alocação de "bus" em diferentes configurações arquiteturais multi-microprocessadores através da introdução de componentes discretos. A segunda etapa consiste na proposição de um circuito integrado arbitro de "bus" multi-protocolos partindo das especificações do circuito ABC 90 e dos resultados obtidos pela primeira proposição. A validação das duas proposições sugeridas par este trabalho foi obtida através de simulações. / The existence of so many parallel communication multi-microprocessor buses (buses of the SM 90, MULTIBUS & VME structures) and their different arbiter techniques led us to study the compatibility of the integrated bus arbiter ABC 90 of the SM 90 (which presents the widest range of functions) with other types of buses MULTIBUS and VME). The first part of the study involved the feasibility of using the ABC 90 circuit as bus arbiter in different architectural configurations; this has been realized by the addition of discrete components. The second step consisted in the design of an integrated multi - protocol communication arbiter, as an extension of the ABC 90's specifications and based on the results obtained in the first part of the study. The validation of both proposals was carried out by simulation.