Digital computers have changed human society in a profound way over the last 50 years. Key properties that contribute to the success of the computer are flexible programmability and fast access to large amounts of data and instructions. Effective access to algorithms and data is a fundamental property that limits the capabilities of computer systems. For PC computers, the main memory consists of dynamic random access memory (DRAM). Communication between memory and processor has traditionally been performed over a multi-drop bus. Signal frequencies on these buses have gradually increased in order to keep up with the progress in integrated circuit data processing capabilities. Increased signal frequencies have exposed the inherent signal degradation effects of a multidrop bus structure. As of today, the main approach to tackle these effects has been to reduce the number of endpoints of the bus structure. Though improvements in DRAM memory technology have increased the available memory size at each endpoint, the increase has not been able to fully fulfill the demand for larger system memory capacity. Different bus structural changes have been used to overcome this problem. All are different compromises between access latency, data transmission capacity, memory capacity, and implementation costs. In this thesis we focus on using the signal processing capabilities of a modern integrated circuit technology as an alternative to bus structural changes. This has the potential to give low latency, high memory capacity, and relatively high data transmission capacity at an additional cost limited to integrated circuit blocks. We first use information theory to estimate the unexplored potential of existing multi-drop bus structures. Hereby showing that reduction of the number of endpoints for multi-drop buses, is by no means based on the fundamental limit of the data transmission capacity of the bus structure. Two test-chips have been designed and fabricated to experimentally demonstrate the feasibility of several Gb/s data-rates over multidrop buses, with limited cost overhead and no latency penalty. The test-chips implement decision feedback equalization, adopted for high speed multi-drop use. The equalizers feature digital filter implementations which, in combination with high speed DACs, enable the use of long digital filters for high speed decision feedback equalization. Blind adaptation has also been implemented to demonstrate extraction of channel characteristics during data transmission. The use of single sided equalization has been proposed in order to limit the need for equalization implementation to the host side of a DRAM memory bus. Furthermore, we propose to utilize the reciprocal properties of the communication channel to ensure that single sided equalization can be performed without any channel characterization hardware on the memory chips. Finally, issues related to evaluation of high-speed channels are addressed and the on-chip structures used for channel evaluation in this project are presented.

The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. The advantage of PTL is higher speed, smaller area and lower power for some particular circuits such as XOR. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this thesis, we develop a novel PTL synthesizer that can efficiently generate PTL-based circuits. We proposed a new synthesis method (hybrid PTL/CMOS Library design) that has multiple driving strengths and multiple threshold voltages to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flow employs the popular Synopsys Design Compiler (DC) to perform logic translation and minimization based on the standard cell library composed of PTL and CMOS logic cells. Thus, the PTL design flow can be easily embedded in the standard cell-based ASIC design flow.

Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers shorter design time, induces fewer errors in the design process, and is easier to maintain. Development of a cell library is laborious, prone to errors and even a small error on a library cell can possibly be disastrous due to repeated use of the cell in a design. In this thesis, we investigated ways to automate the process for development of a cell library, specifically TSMC 0.18-micron CMOS standard cell library. We examined various steps in the design flow to identify required repetitive tasks for individual cells. Those steps include physical verification, netlist extraction, cell characterization, and generation of Synopsys Liberty Format file. We developed necessary scripts in Skill, Tcl, Perl and Shell to automate those steps. Additionally, we developed scripts to automate the quality assurance process of the cell library, where quality assurance consists of verifying the entire ASIC design flow adopted for the Virginia Tech VLSI Telecommunications (VTVT) lab. Our scripts have been successfully used to develop our TSMC 0.18-micron library and to verify the quality assurance. The first version of the cell library was released on November 1, 2007 to universities worldwide, and as of March 2008, 20 universities have received the library from us. / Master of Science

No description available.

Cette thèse est la R&D de l’électronique de front-end destinée à la camera de deuxième génération du télescope de grande taille LST de projet CTA, étant basée sur les détecteurs de type SiPM. Cette étude rassemble des équipes du LAPP, de l’université de Padoue, de l’INFN et du MPI de Munich. La première partie de cette thèse porte sur les tests de caractérisations d’une matrice de 16 SiPMs fabriquée par Hamamatsu. Les résultats de ces tests ont souligné les avantages qui pourraient être apportés par l’utilisation de tels détecteurs. Un cahier des charges pour l’électronique a été défini à l’issue de ces tests. Notamment, une nécessité de corriger la dispersion en gain entre les 16 pixels qui a été trouvée d’environ 10%. La seconde partie est la conception d’un circuit intégré (ASIC) qui pourrait lire les signaux des pixels -SiPM avec la moindre perturbation possible de fonctionnement du détecteur. Cet ASIC inclut des fonctions de contrôle (slow control) qui permettent l’ajustement de gain des pixels, l’amélioration de l’uniformité de gain et la possibilité de supprimer les canaux bruyants ou encore même le contournement du processus de contrôle de gain. Ces fonctionnalités peuvent unifier le gain de 16 canaux. Les sorties des 16 canaux seront sommées pour en faire deux signaux seulement à la sortie de l’ASIC. Ces deux signaux, un sur le haut gain et l’autre sur le bas gain seront fournis au système d’acquisition qui suivra l’ASIC. Une fonction de déclenchement génèrera un signal de trigger qui sera ainsi transmis au système d’acquisition. Cet ASIC a été réalisée avec la technologie AMS 0.35um BiCMOS. Les simulations ont montré une gamme dynamique linéairement couverte jusqu’à 2000 photoélectrons et la possibilité de mesurer le photoélectron unique grâce au bon rapport signal sur bruit électronique. Les tests au laboratoire confirment une grande partie de ces résultats. / This thesis is the R&D on front-end electronics for a second generation camera based on the SiPM detectors for the Large Size Telescope (LST) of the CTA project. It is a part of the SiPM collaboration involving the LAPP, the University of Padua, the INFN and the MPI in Munich. The first part of the thesis is the characterization of an array of 16 SiPMs from Hamamatsu. The study proves the advantages of using such detectors in the LST. It defines the specifications of the readout electronics that are the aim of this work. Especially that it should ameliorate the gain dispersion of the 16 pixels that was found of about 10%. The second part is the design of the readout ASIC. The scheme tends to measure the SiPMs’ signals with minimum disturbance of the detector. It integrates slow control facilities that adjust the detector’s gain, minimize the dispersion in gain and provide the possibility of deleting noisy channels or even completely jumping over the control process. These facilities could perfectly get rid of the gain dispersion. Outputs of the 16 pixels will be summed on both high gain and low gain so that only two signals are delivered to the acquisition system that follows. A trigger function will also generate a trigger signal to the acquisition system. The choice was made to realize this ASIC according to the rules of the AMS 0.35um BiCMOS technology. Simulation shows a linearly-covered dynamic range up to 2000 photoelectrons with good signal to noise ratio that allows the measurement of the single photoelectron. Laboratory tests confirm a great part of these results.

La bioélectronique est un domaine transdisciplinaire qui oeuvre, entre autres, àl’interconnexion entre des systèmes biologiques présentant une activité électrique et le mondede l’électronique. Cette communication avec le vivant implique l’observation de l’activitéélectrique des cellules considérées et nécessite donc une chaine d’acquisition électronique.L’utilisation de Multi/Micro Electrodes Array débouche sur des systèmes devantacquérir un grand nombre de canaux en parallèle, dès lors la consommation etl’encombrement des circuits d’acquisition ont un impact significatif sur la viabilité dusystème destiné à être implanté.Cette thèse propose deux réflexions à propos de ces circuits d’acquisition. Une ces desréflexions a trait aux circuits d’amplification, à leur impédance d’entrée et à leurconsommation ; l’autre concerne un détecteur de potentiels d’action analogique, samodélisation et son optimisation.Ces travaux théoriques ayant abouti à des résultats concrets, un ASIC a été conçu,fabriqué, testé et caractérisé au cours de cette thèse. Cet ASIC à huit canaux comporte doncdes amplificateurs et des détecteurs de potentiels d’action analogiques et constitue le principalapport de ce travail de thèse. / Bioelectronics is a transdisciplinary field which develops interconnection devicesbetween biological systems presenting electrical activity and the world of electronics. Thiscommunication with living tissues implies to observe the electrical activity of the cells andtherefore requires an electronic acquisition chain.The use of Multi / Micro Electrode Array leads to systems that acquire a large numberof parallel channels, thus consumption and congestion of acquisition circuits have asignificant impact on the viability of the system to be implanted.This thesis proposes two reflections about these acquisition circuits. One of thesereflections relates to amplifier circuits, their input impedance and consumption; the otherconcerns an analogue action potentials detector, its modeling and optimization.These theoretical work leading to concrete results, an ASIC was designed,manufactured, tested and characterized in this thesis. This eight-channel ASIC thereforeincludes amplifiers and analogue action potentials detector and is the main contribution of thisthesis.

Indiana University-Purdue University Indianapolis (IUPUI) / A novel method of power management and sequential monitoring of several sensors is proposed in this work. Application specific integrated circuits (ASICs) consisting of analog and digital sub-systems forming a system on chip (SoC) has been designed using complementary metal-oxide-semiconductor (CMOS) technology. The analog sub-system comprises the sensor-drivers that convert the input voltage variations to output pulse-frequency. The digital sub-system includes the system management unit (SMU), counter, and shift register modules. This performs the power-usagemanagement, sensor-sequence-control, and output-data-frame-generation functions. The SMU is the key unit within the digital sub-system is that enables or disables a sensor. It captures the pulse waves from a sensor for 3 clocks out of a 16-clock cycle, and transmits the signal to the counter modules. As a result, the analog sub-system is at on-state for only 3/16th fraction (18 %) of the time, leading to reduced power consumption. Three cycles is an optimal number selected for the presented design as the system is unstable with less than 3 cycles and higher clock cycles results in increased power consumption. However, the system can achieve both higher sensitivity and better stability with increased on-state clock cycles. A current-starved-ring-oscillator generates pulse waves that depend on the sensor input parameter. By counting the number of pulses of a sensor-driver in one clock cycle, a sensor input parameter is converted to digital. The digital sub-system constructs a 16-bit frame consisting of 8-bit sensor data, start and stop bits, and a parity bit. Ring oscillators that drive capacitance and resistance-based sensors use an arrangement of delay elements with two levels of control voltages. A bias unit which provides these two levels of control voltages consists of CMOS cascade current mirror to maximize voltage swing for control voltage level swings which give the oscillator wider tuning range and lower temperature induced variations. The ring oscillator was simulated separately for 250 nm and 180 nm CMOS technologies. The simulation results show that when the input voltage of the oscillator is changed by 1 V, the output frequency changes linearly by 440 MHz for 180 nm technology and 206 MHz for 250 nm technology. In a separate design, a temperature sensitive ring oscillator with symmetrical load and temperature dependent input voltage was implemented. When the temperature in the simulation model was varied from -50C to 100C the oscillator output frequency reduced by 510 MHz for the 250 nm and by 810 MHz for 180 nm CMOS technologies, respectively. The presented system does not include memory unit, thus, the captured sensor data has to be instantaneously transmitted to a remote station, e.g. end user interface. This may result in a loss of sensor data in an event of loss of communication link with the remote station. In addition, the presented design does not include transmitter and receiver modules, and thus necessitates the use of separate modules for the transfer of the data.