The thermal performance of the power MOSFET module is subject to change over its lifetime. This is caused by the growth of voids and other defects in the die-attach layer. The goal of this dissertation is to develop measurement techniques and finite element simulations that can measure the changes in thermal performance caused by changes in die-attach voided area. These experimental results and simulations can then be used to create predictions of the thermal performance of a particular power semiconductor module at various stages of die-attach fatigue. In the results and simulations presented, a relationship is developed between thermal impedance and void area coverage. This dissertation starts by presenting an analysis of the thermal and mechanical stresses needed for crack and void growth in the power semiconductor die-attach region. Accelerated life testing is then performed for both commercial and prototype power semiconductor devices to generate the stresses needed to precipitate void growth. Representative groups of lead and lead-free solders are then tested to compare levels of die-attach degradation under accelerated life conditions. Hardware is developed to experimentally measure thermal impedance using temperaturesensitive characteristics of the power MOSFET. The power semiconductor devices that were subjected to accelerated life testing are then measured with this hardware. The results show that die-attach voided area coverage increases thermal impedance. Representative lumped parameter thermal models that use R-C circuits are derived to demonstrate the ability of the thermal impedance analyzer to determine the differences in the die-attach layer. Finite element modeling (FEM) is then used on representative voided devices to support these results, with additional emphasis on peak temperatures caused by hotspots located over the voided areas. Experimental techniques are further applied to measurement of cooling trends that occur due to the existence of voids in the die-attach layer. These measurements are correlated with finite element thermal simulations to develop a relationship between thermal impedance, hotspot temperature, die-attach void size, and total voided area coverage. / Ph. D.

No description available.

Well-logging and aerospace applications require electronics capable of withstanding elevated temperature operation. A key element of high temperature packaging technology is the Si die attach material, and a comparative study of two die attach systems for use in harsh environment has been performed. Die bond sample packages, using commercial adhesives and an Au-Si eutectic solder, have been manufactured and were subsequently thermally exposed for various times at 250 and 300°C respectively. The adhesive die bond packages comprised a high temperature co-fired ceramic (HTCC) substrate with W, Ni and Au metallisations whereas the Au-Si die bond packages used thick film Au metallised on a Al₂O₃ substrate. Optimisation of the eutectic die bonding parameters was successfully performed for the Au-Si system by an experimental design method, which improved mean and spread of maximum bonded areas and consequently, the shear load to failure. Bonded area was systematically assessed by scanning acoustic microscopy (SAM) followed by digital image analysis (DIA). Accelerated testing comprised thermal cycling and thermal shock and although showing some degradation, Au-2wt%Si die bonds were surprisingly robust, showing excellent subsequent stability during industrial device testing investigations.

No description available.

Silver sintering technology has received considerable attention in recent years because it has the potential to be a suitable interconnection material for high-temperature power electronic packaging, such as high melting temperature, high electrical/thermal conductivity, and excellent mechanical reliability. It should be noted, however, that pressure (usually between three to five MPa) was added during the sintering stage for attaching power chips with area larger than 100 mm2. This extra pressure increased the complexity of the sintering process. The maximum chip size processed by pressure-free sintering, in the published resources, was 6 x 6 mm2. One objective of this work was to achieve chip-attachment with area of 13.5 x 13.5 mm2 (a chip size of one kind of commercial IGBT) by pressure-free sintering of nano-silver paste. Another objective was to fabricate high-power (1200 V and 150 A) multi-chip module by pressure-free sintering. In each module (half-bridge), two IGBT dies (13.5 x 13.5 mm2) and two diode dies (10 x 10 mm2) were attached to a DBC substrate. Modules with solder joints (SN100C) and pressure-sintered silver joints were also fabricated as the control group. The peak temperature in the process of of pressure-free sintering of silver was around 260oC, whereas 270oC for vacuum reflowing of solder, and 280oC under three MPa for pressure-sintering of silver. The process for wire bonding, lead-frame attachment, and thermocouple attachment are also recorded. Modules with the above three kinds of joints were first characterized by electrical methods. All of them could block 1200 V DC voltage after packaging, which is the voltage rating of bare dies. Modules were also tested up to the rated current (150 A) and half of the rated voltage (600 V), which were the test conditions in the datasheet for commercial modules with the same voltage and current ratings. I-V characteristics of packaged devices were similar (on-resistance less than 0.5 mohm). All switching waveforms at transient stage (both turn-on and turn-off) were clean. Six switching parameters (turn-on delay, rise time, turn-off delay, fall time, turn-on loss, and turn-off loss) were measured, which were also similar (<9%) among different kinds of modules. The results from electrical characterizations showed that both static characterizations and double-pulse test cannot be used for evaluating the differences among chip-attach layers. All modules were also characterized by their thermal performances. Transient thermal impedances were measured by gate-emitter signals. Two setups for thermal impedance measurement were used. In one setup, the bottoms of modules were left in the air, and in the other setup, bottoms of modules were attached to a chiller (liquid cooling and temperature controlled at 25oC) with thermal grease. Thermal impedances of three kinds of modules still increased after 40 seconds for the testing without chiller, since the thermal resistance of heat convection from bottom copper to the air was included , which was much larger than the sum of the previous layers (from IGBT junction, through the chip-attach layer, to the bottom of DBC substrate). In contrast, thermal impedances became almost stable (less than 3%) after 15 seconds for all modules when the chiller was used. Among these three kinds of modules, the module with pressure sintered joints had the lowest thermal impedance and the thermal resistance (tested with the chiller) around 0.609oK/W, In contrast, the thermal resistance was around 964oK /W for the soldered module, and 2.30oK /W for pressure-free sintered module. In summary, pressure-free large-area sintered joints were achieved and passed the fabrication process for IGBT half-bridge module with wiring bonding. Packaged devices with these kinds of joints were verified with good electrical performance. However, thermal performances of pressure-free joints were worse than solder joints and pressure-sintered joints. / Master of Science

Die attachment is one of the most important processes in the packaging of power semiconductor devices. The current die-attach materials/techniques, including conductive adhesives and reflowed solders, can not meet the advance of power conversation application. Silver paste sintering has been widely used in microelectronics and been demonstrated the superior properties. The high processing temperature, however, prevents its application of interconnecting power semiconductor devices. This research focuses processing and characterization of micron-scale and nanoscale silver paste for power semiconductor devices attachment. Lowering the processing temperature is the essential to implement sintering silver paste for power semiconductor devices attachment. Two low-temperature sintering techniques - pressure-assisted sintering micro-scale silver paste and sintering nanoscale silver paste without external pressure - were developed. With the large external pressure, the sintering temperature of micro-scale silver paste can be significantly lowered. The experimental results show that by using external pressure (>40MPa), the commercial micro-scale silver paste can be sintered to have eighty percent relative density at 240oC, which is compatible with the temperature of solder reflowing. The measured properties including electrical conductivity, thermal conductivity, interfacial thermal resistance, and the shear strength of sintered silver joints, are significantly better than those of the reflowed solder layer. Given only twenty percent of small pores in the submicron range, the reliability of the silver joints is also better than that of the solder joints under the thermal cycled environment. The large external pressure, however, makes this technique difficult to automatically implement and also has a potential to damage the brittle power semiconductor devices. Reducing silver particles in the paste from micro-size to nanoscale can increases the sintering driving force and thus lowers the sintering temperature. Several approaches were developed to address sintering challenges of nanoscale silver particles, such as particles aggregation and/or agglomeration, and non-densification diffusion at low temperature. These approaches are : nanoscale silver slurry, instead of dry silver powder, is used to keep silver particles stable and prevent their aggregation. Ultrasonic vibration, instead of conventional ball milling, is applied to disperse nanoscale silver particles in the paste from to avoid from agglomerating. Selected organics in the paste are applied to delay the onset of mass-diffusion and prevent non-densification diffusion at low temperature. The measured results show that with heat-treatment at 300oC within one hour, the sintered nanoscale silver has significantly improved electrical and thermal properties than reflowed solders. The shear strength of sintered silver interconnection is compatible with that of solder. The low-temperature sinterable nanoscale silver paste was applied to attach the bare Silicon carbide (SiC) schottky barrier diode (SBD) for high temperature application. Limited burn-out path for organics in the silver layer challenges the sintering die-attach. This difficulty was lessened by reducing organics ratio in the silver paste. The effects of die-size and heating rate on sintering die-attach were also investigated. The single chip packaging of SiC SBD was fabricated by sintering die-attach and wire-bonding. The tested results demonstrate that the sintering nanoscale silver paste can be applied as a viable die-attach solution for high-temperature application. / Ph. D.

Currently, there are two major driving forces for considering alternative materials to lead- based products, specifically interconnections, in electronics applications, including the impending legislation or regulations which may tax, restrict, or eliminate the use of lead and the trend toward advanced interconnection technology, which may challenge the limits of present soldering technology. The reliability of solder joints is a concern because fracture failures in solder joints accounts for 70% of failures in electronic components. Lead-free solders are being investigated as replacements for lead solders currently used in electronics. Thermo-mechanical properties describe the stresses accumulated due to thermal fatigue as a result of CTE mismatch within the system. By understanding the failure mechanisms related to lead-free solders, the application of lead- free solders could be more strategically designed for specific applications. The objective of this thesis is to observe microstructural change in large-area solder joints caused by thermal cycling and relate these changes to reliability issues in large-area lead and lead-free solder constructed semiconductor power devices. This study focused on the microstructural changes within the solder alloy of a large-area solder joint under thermal cycling conditions. Two major primary observations were made from this research, they are: 1) due to a combination of testing conditions and material properties, the lead-free solders, Sn/3.5Ag and Sn/Ag/0.7Cu, sustained the most severe damage as compared to Sn/37Pb, and 2) due to elevated stresses at the solder/substrate interface in a simulated power semiconductor device sample damage was found to be most severe. / Master of Science

Due to the multi-tasking and miniaturization of electronic devices, faster heat transfer is required from the device to avoid the thermal failure. Die-attached polymer adhesives are used to bond the chips in electronic packaging. These adhesives have to hold strong mechanical, thermal, dielectric, and moisture resistant properties. As polymers are insulators, heat conductive particles are inserted in it to enhance the thermal flow with an attention that there would be no electrical conductivity as well as no reduction in dielectric strength. This thesis focuses on the characterization of polymer nanocomposites for thermal and electrical properties with experimental and computational tools. Platelet geometry of hexagonal boron nitride offers highly anisotropic properties. Therefore, their alignment and degree of orientation offers tunable properties in polymer nanocomposites for thermal, electrical, and mechanical properties. This thesis intends to model the anisotropic behavior of thermal and dielectric properties using finite element and molecular dynamics simulations as well as experimental validation.

Die komplexen Strukturen von MEMS-Drehratensensoren führen immer wieder zu Herausforderungen bei der Systembeschreibung. Die zunehmende Miniaturisierung der Bauteile steigert den Einfluss von mechanischen Nichtlinearitäten und AVT-Einflüssen. Daher sind ein tiefer gehendes Verständnis dieser Effekte und verbesserte Simulationsmethoden zur effizienten Entwicklung neuer Sensoren von großer Bedeutung. In dieser Arbeit wird die TPWL-Methode, ein Ansatz für ein transientes nichtlineares ROM, vorgestellt und erfolgreich auf MEMS-Drehratensensoren angewendet. Im Fokus der Untersuchungen stehen die Implementierung der Methode und die Zeitersparnis gegenüber FE-Simulationen - diese beträgt bis zu 3 Größenordnungen. Weiterhin finden sich Untersuchungen der ROM-Daten, mit einem Schwerpunkt auf deren Interpretation, in den Ausführungen. Hierdurch werden Limitierungen, Rahmenbedingungen und Aussagekraft der Methodik aufgezeigt. Diese Erkenntnisse ermöglichen es, zukünftige Simulationen durch geeignet gewählte Parameter und Trainingsdaten effektiv aufzusetzen. Es werden TPWL-Ansätze auf Basis von POD und modaler Superposition verglichen, um systematische Vorteile der POD zu erklären. Die Validierung der Modelle erfolgt qualitativ sowie mit Messungen, analytischen und FE-Rechnungen. Bestehende Ansätze zur Simulation von AVT-Einflüssen, mit einem Schwerpunkt auf mechanischen Stresswirkpfaden, auf MEMS-Drehratensensoren werden untersucht und erweitert. Als Basis für Package- und statische Struktursimulationen dienen FE-Modelle und für die transiente Systemsimulation ein ROM. Es stehen Verständnis und Analyse der Wirkpfade im Vordergrund. Die resultierenden Erkenntnisse werden erfolgreich in die Modelle eingebracht. Ein einfacher, dennoch aussagekräftiger Ansatz zur Abschätzung des Drehraten-Offsets gestresster Sensoren wird vorgestellt. Zudem wird ein vielversprechendes neuartiges FE-Modell zur Simulation von Die-attach- und Lötsimulationen hergeleitet. Oberflächen- und Signalmessungen von durch eine Leiterplattenbiegung gestressten Sensoren dienen zur Validierung. Die vorgestellten Modelle werden erfolgreich validiert und können zukünftig zur Optimierung des Entwicklungsprozesses von MEMS-Drehratensensoren verwendet werden.:Abkürzungen und Symbole I. Einführung, Grundlagen und Methoden 1. Einleitung 1.1. Hintergrund und aktuelle Entwicklung 1.2. Motivation und Zielsetzung der Arbeit 1.3. Struktur der Arbeit 2. Grundlagen MEMS 2.1. Definition der Mikrosystemtechnik 2.2. Technologie und Aufbau von MEMS Bausteinen 2.3. Funktionsprinzipien und physikalischen Grundlagen von MEMS-Gyroskopen 3. Rechenmodelle für mechanische Systeme 3.1. Analytische Rechnungen mithilfe der Balkentheorie 3.2. Finite-Elemente-Methode 3.3. Ordnungsreduktionsverfahren 3.4. Ordnungsreduzierte Systemmodelle in der Signalflusssimulation II. Mechanische Nichtlinearitäten 4. Nichtlinearitäten in MEMS-Gyroskopen 4.1. Einleitung und Motivation 4.2. Gegenüberstellung nichtlinearer Effekte und deren Einflüsse auf MEMS-Gyroskope 4.3. Konzepte zur Vermeidung von Stress-Stiffening und deren Grenzen 5. Methoden zur Simulation mechanischer Nichtlinearitäten 5.1. Nichtlineare Effekte in der FE-Rechnung 5.2. Konzept der Trajectory Piecewise Linearization 5.3. Werkzeuge zur Implementierung eines TPWL-Verfahrens in die Systemsimulation 5.4. Generierung einer ordnungsreduzierten TPWL-Simulation von Drehratensensoren 6. Die Trajectory Piecewise Linearization in der Praxis 6.1. Beidseitig eingespannter Biegebalken in der TPWL mit POD 6.2. Die TPWL anhand eines perforierten Einmassenschwingers 6.3. Untersuchung einer stark nichtlinearen Sensorgeometrie III. Einfluss von mechanischem Stress durch die Aufbau- und Verbindungstechnik auf Sensoren und Sensor-Packages 7. Messungen und Simulationen in der AVT 7.1. Einleitung und Motivation 7.2. Einfluss von mechanischem Stress auf die Sensorgeometrie 7.3. Schema einer Stresssimulation 7.4. Experimentelles Setup 7.5. Viskoelastische Eigenschaften in Experiment und Simulation 8. FE-Package Simulationen 8.1. Annahmen 8.2. Struktur und Inhalt einer FE-Package-Simulation 8.3. CAD-Modellierung und Vernetzung 8.4. Prozesssimulationen 8.5. Biegesimulation 8.6. Validierung durch Weißlichtinterferometrie 9. FE-Modelle von MEMS Strukturen 9.1. Transfer des AVT Stresses aus den Package Simulationen 9.2. Stresseinfluss auf Eigenfrequenzen 10.Berücksichtigung von AVT-Einflüssen in Signalflusssimulationen 10.1. Signalflussmodelle mit AVT-Einfluss 10.2. Sensormoden und Dämpfungsmatrix 10.3. Validierung der Modelle anhand des Closed-Loop Systems 10.4. Simulation des Dreikanalsensors IV. Abschluss 11.Zusammenfassung 11.1. Mechanische Nichtlinearitäten 11.2. Einfluss der Aufbau- und Verbindungstechnik 12.Fazit und Ausblick V. Anhang A. Faktoren der Newmark-Integration B. Einfluss der Samplingrate auf die Schwingungsfrequenz in einer transienten FE-Simulation C. Ergebnisstabellen zu Kapitel 6.1 D. Einseitig eingespannter Biegebalken mit Streckbiegung D.1. Aufbau des Systems D.2. Systemtraining D.3. Systemsimulation und Auswertung D.4. Fazit E. Modenabbildungen zu Kapitel 6.2 F. Vergleich von TPWL und linearer Ordnungsreduktion mit nichtlinearen Kräften G. Modellbeispiel Schwingungsform H. Mathematische Ergänzungen I. Einfluss von Prozessparametern Quellenangaben Tabellenverzeichnis Abbildungsverzeichnis Danksagung Versicherung Thesen / The complex structures of MEMS yaw-rate sensors continuously lead to challenges in their system description. The continuing miniaturization of the components increases the effects of mechanical nonlinearities and packaging influences. Therefore, a deeper understanding of these effects and improved simulation methods are of great importance for the efficient development of new sensors. In this work the TPWL-method, an approach for a transient nonlinear ROM, is introduced and successfully applied to MEMS yaw-rate sensors. The focal points of the study, are the implementation of the method, and the time savings compared to FE-simulations; which are up to 3 magnitudes. Furthermore, the analysis of the ROM-data with a focus on its interpretation is included. This highlights limits, boundary conditions and the informative value of the method. These insights enable the future set up of simulations effectively with appropriately chosen parameters and training data. TPWL-approaches with POD and modal superposition are compared to highlight systematic advantages of the POD. The validation of the models is realized qualitatively as well as with measurements, analytical and FE-calculations. Existing approaches for the simulation of packaging influences with a focal point on mechanical stress root causes are studied and extended. As a baseline for package and static structure simulations FE-models are used, and for transient system simulations a ROM is used. Understanding and analysis of the root causes stand in the foreground. The resulting insights are successfully implemented into the models. A simple but significant approach for an estimation of the yaw-rate offset of stressed sensors is introduced. Additionally, a promising and new FE-model for the simulation of die attach and solder simulations is derived. Surface and signal measurements of sensors, stressed by the bending of a printed circuit board, serve for validation. The introduced models were validated successfully and can be used in the future to optimize the development process of MEMS yaw-rate sensors.:Abkürzungen und Symbole I. Einführung, Grundlagen und Methoden 1. Einleitung 1.1. Hintergrund und aktuelle Entwicklung 1.2. Motivation und Zielsetzung der Arbeit 1.3. Struktur der Arbeit 2. Grundlagen MEMS 2.1. Definition der Mikrosystemtechnik 2.2. Technologie und Aufbau von MEMS Bausteinen 2.3. Funktionsprinzipien und physikalischen Grundlagen von MEMS-Gyroskopen 3. Rechenmodelle für mechanische Systeme 3.1. Analytische Rechnungen mithilfe der Balkentheorie 3.2. Finite-Elemente-Methode 3.3. Ordnungsreduktionsverfahren 3.4. Ordnungsreduzierte Systemmodelle in der Signalflusssimulation II. Mechanische Nichtlinearitäten 4. Nichtlinearitäten in MEMS-Gyroskopen 4.1. Einleitung und Motivation 4.2. Gegenüberstellung nichtlinearer Effekte und deren Einflüsse auf MEMS-Gyroskope 4.3. Konzepte zur Vermeidung von Stress-Stiffening und deren Grenzen 5. Methoden zur Simulation mechanischer Nichtlinearitäten 5.1. Nichtlineare Effekte in der FE-Rechnung 5.2. Konzept der Trajectory Piecewise Linearization 5.3. Werkzeuge zur Implementierung eines TPWL-Verfahrens in die Systemsimulation 5.4. Generierung einer ordnungsreduzierten TPWL-Simulation von Drehratensensoren 6. Die Trajectory Piecewise Linearization in der Praxis 6.1. Beidseitig eingespannter Biegebalken in der TPWL mit POD 6.2. Die TPWL anhand eines perforierten Einmassenschwingers 6.3. Untersuchung einer stark nichtlinearen Sensorgeometrie III. Einfluss von mechanischem Stress durch die Aufbau- und Verbindungstechnik auf Sensoren und Sensor-Packages 7. Messungen und Simulationen in der AVT 7.1. Einleitung und Motivation 7.2. Einfluss von mechanischem Stress auf die Sensorgeometrie 7.3. Schema einer Stresssimulation 7.4. Experimentelles Setup 7.5. Viskoelastische Eigenschaften in Experiment und Simulation 8. FE-Package Simulationen 8.1. Annahmen 8.2. Struktur und Inhalt einer FE-Package-Simulation 8.3. CAD-Modellierung und Vernetzung 8.4. Prozesssimulationen 8.5. Biegesimulation 8.6. Validierung durch Weißlichtinterferometrie 9. FE-Modelle von MEMS Strukturen 9.1. Transfer des AVT Stresses aus den Package Simulationen 9.2. Stresseinfluss auf Eigenfrequenzen 10.Berücksichtigung von AVT-Einflüssen in Signalflusssimulationen 10.1. Signalflussmodelle mit AVT-Einfluss 10.2. Sensormoden und Dämpfungsmatrix 10.3. Validierung der Modelle anhand des Closed-Loop Systems 10.4. Simulation des Dreikanalsensors IV. Abschluss 11.Zusammenfassung 11.1. Mechanische Nichtlinearitäten 11.2. Einfluss der Aufbau- und Verbindungstechnik 12.Fazit und Ausblick V. Anhang A. Faktoren der Newmark-Integration B. Einfluss der Samplingrate auf die Schwingungsfrequenz in einer transienten FE-Simulation C. Ergebnisstabellen zu Kapitel 6.1 D. Einseitig eingespannter Biegebalken mit Streckbiegung D.1. Aufbau des Systems D.2. Systemtraining D.3. Systemsimulation und Auswertung D.4. Fazit E. Modenabbildungen zu Kapitel 6.2 F. Vergleich von TPWL und linearer Ordnungsreduktion mit nichtlinearen Kräften G. Modellbeispiel Schwingungsform H. Mathematische Ergänzungen I. Einfluss von Prozessparametern Quellenangaben Tabellenverzeichnis Abbildungsverzeichnis Danksagung Versicherung Thesen

Advances in wide-bandgap semiconductor devices have increased the allowable operating temperature of power electronic systems. High-temperature devices can benefit applications such as renewable energy, electric vehicles, and space-based power electronics that currently require bulky cooling systems for silicon power devices. Cooling systems can typically be reduced in size or removed by adopting wide-bandgap semiconductor devices, such as silicon carbide. However, to do this, semiconductor device packaging with high reliability at high temperatures is necessary. Transient liquid phase (TLP) die-attach has shown in literature to be a promising bonding technique for this packaging need. In this work TLP has been comprehensively investigated and characterized to assess its viability for high-temperature power electronics applications. The reliability and durability of TLP die-attach was extensively investigated utilizing electrical resistivity measurement as an indicator of material diffusion in gold-indium TLP samples. Criteria of ensuring diffusive stability were also developed. Samples were fabricated by material deposition on glass substrates with variant Au–In compositions but identical barrier layers. They were stressed with thermal cycling to simulate their operating conditions then characterized and compared. Excess indium content in the die-attach was shown to have poor reliability due to material diffusion through barrier layers while samples containing suitable indium content proved reliable throughout the thermal cycling process. This was confirmed by electrical resistivity measurement, EDS, FIB, and SEM characterization. Thermal and mechanical characterization of TLP die-attached samples was also performed to gain a newfound understanding of the relationship between TLP design parameters and die-attach properties. Samples with a SiC diode chip TLP bonded to a copper metalized silicon nitride iv substrate were made using several different values of fabrication parameters such as gold and indium thickness, Au–In ratio, and bonding pressure. The TLP bonds were then characterized for die-attach voiding, shear strength, and thermal impedance. It was found that TLP die-attach offers high average shear force strength of 22.0 kgf and a low average thermal impedance of 0.35 K/W from the device junction to the substrate. The influence of various fabrication parameters on the bond characteristics were also compared, providing information necessary for implementing TLP die-attach into power electronic modules for high-temperature applications. The outcome of the investigation on TLP bonding techniques was incorporated into a new power module design utilizing TLP bonding. A full half-bridge inverter power module for low-power space applications has been designed and analyzed with extensive finite element thermomechanical modeling. In summary, TLP die-attach has investigated to confirm its reliability and to understand how to design effective TLP bonds, this information has been used to design a new high-temperature power electronic module.