The thermal performance of the power MOSFET module is subject to change over its lifetime. This is caused by the growth of voids and other defects in the die-attach layer. The goal of this dissertation is to develop measurement techniques and finite element simulations that can measure the changes in thermal performance caused by changes in die-attach voided area. These experimental results and simulations can then be used to create predictions of the thermal performance of a particular power semiconductor module at various stages of die-attach fatigue. In the results and simulations presented, a relationship is developed between thermal impedance and void area coverage. This dissertation starts by presenting an analysis of the thermal and mechanical stresses needed for crack and void growth in the power semiconductor die-attach region. Accelerated life testing is then performed for both commercial and prototype power semiconductor devices to generate the stresses needed to precipitate void growth. Representative groups of lead and lead-free solders are then tested to compare levels of die-attach degradation under accelerated life conditions. Hardware is developed to experimentally measure thermal impedance using temperaturesensitive characteristics of the power MOSFET. The power semiconductor devices that were subjected to accelerated life testing are then measured with this hardware. The results show that die-attach voided area coverage increases thermal impedance. Representative lumped parameter thermal models that use R-C circuits are derived to demonstrate the ability of the thermal impedance analyzer to determine the differences in the die-attach layer. Finite element modeling (FEM) is then used on representative voided devices to support these results, with additional emphasis on peak temperatures caused by hotspots located over the voided areas. Experimental techniques are further applied to measurement of cooling trends that occur due to the existence of voids in the die-attach layer. These measurements are correlated with finite element thermal simulations to develop a relationship between thermal impedance, hotspot temperature, die-attach void size, and total voided area coverage. / Ph. D.

Flat plate heat pipes are very efficient passive two-phase heat transport devices. Their high e'ciency and low mass are desirable in the aerospace and electronics industries. The highly competitive nature of the thermal management industry results in little awareness of the capabilities of at plate heat pipes, which has resulted in only a few applications of the technology. In the year 2000 a research and development project sponsored by Space Dynamics Laboratory was launched to investigate building carbon-based at heat pipes. The at conguration is desireable to incorporate many components onto one thermal management system. Development led to the adoption of the term "Channel Panel" because of the orthogonal grid of channels used as the capillary structure. Work to date has veried the utility and basic function of this technology but has not resulted in a standard method for the design and fabrication of channel panels. This study investigates and evaluates currently available and relevent models useful for the design of channel panels, investigates issues with fabrication, and makes suggestions for future development. Shallow pool boiling is shown to be an appropriate model for the critical heat ux of boiling in at plate heat pipes and provides a means for estimating the convective heat transfer coe'cient. Previous work by Neal Hubbard is modied and shown to accurately couple the geometry and operating limits of a channel panel. Experiments verify the analytical predictions of these models. Issues in the fabrication of channel panels are reported as well as standard procedures for cleaning and lling. The nal result is a standard method for the initial design phase of channel panel at plate heat pipes.

Silver sintering technology has received considerable attention in recent years because it has the potential to be a suitable interconnection material for high-temperature power electronic packaging, such as high melting temperature, high electrical/thermal conductivity, and excellent mechanical reliability. It should be noted, however, that pressure (usually between three to five MPa) was added during the sintering stage for attaching power chips with area larger than 100 mm2. This extra pressure increased the complexity of the sintering process. The maximum chip size processed by pressure-free sintering, in the published resources, was 6 x 6 mm2. One objective of this work was to achieve chip-attachment with area of 13.5 x 13.5 mm2 (a chip size of one kind of commercial IGBT) by pressure-free sintering of nano-silver paste. Another objective was to fabricate high-power (1200 V and 150 A) multi-chip module by pressure-free sintering. In each module (half-bridge), two IGBT dies (13.5 x 13.5 mm2) and two diode dies (10 x 10 mm2) were attached to a DBC substrate. Modules with solder joints (SN100C) and pressure-sintered silver joints were also fabricated as the control group. The peak temperature in the process of of pressure-free sintering of silver was around 260oC, whereas 270oC for vacuum reflowing of solder, and 280oC under three MPa for pressure-sintering of silver. The process for wire bonding, lead-frame attachment, and thermocouple attachment are also recorded. Modules with the above three kinds of joints were first characterized by electrical methods. All of them could block 1200 V DC voltage after packaging, which is the voltage rating of bare dies. Modules were also tested up to the rated current (150 A) and half of the rated voltage (600 V), which were the test conditions in the datasheet for commercial modules with the same voltage and current ratings. I-V characteristics of packaged devices were similar (on-resistance less than 0.5 mohm). All switching waveforms at transient stage (both turn-on and turn-off) were clean. Six switching parameters (turn-on delay, rise time, turn-off delay, fall time, turn-on loss, and turn-off loss) were measured, which were also similar (<9%) among different kinds of modules. The results from electrical characterizations showed that both static characterizations and double-pulse test cannot be used for evaluating the differences among chip-attach layers. All modules were also characterized by their thermal performances. Transient thermal impedances were measured by gate-emitter signals. Two setups for thermal impedance measurement were used. In one setup, the bottoms of modules were left in the air, and in the other setup, bottoms of modules were attached to a chiller (liquid cooling and temperature controlled at 25oC) with thermal grease. Thermal impedances of three kinds of modules still increased after 40 seconds for the testing without chiller, since the thermal resistance of heat convection from bottom copper to the air was included , which was much larger than the sum of the previous layers (from IGBT junction, through the chip-attach layer, to the bottom of DBC substrate). In contrast, thermal impedances became almost stable (less than 3%) after 15 seconds for all modules when the chiller was used. Among these three kinds of modules, the module with pressure sintered joints had the lowest thermal impedance and the thermal resistance (tested with the chiller) around 0.609oK/W, In contrast, the thermal resistance was around 964oK /W for the soldered module, and 2.30oK /W for pressure-free sintered module. In summary, pressure-free large-area sintered joints were achieved and passed the fabrication process for IGBT half-bridge module with wiring bonding. Packaged devices with these kinds of joints were verified with good electrical performance. However, thermal performances of pressure-free joints were worse than solder joints and pressure-sintered joints. / Master of Science

Ce document porte sur le développement d’un nouveau banc de mesure pour la caractérisation de l’impédance thermique des HEMTs GaN. Le banc développé repose sur la méthode dite « 3ω » qui consiste à mesurer l’harmonique 3 d’un signal électrique véritable image des variations thermiques du composant. Un balayage en fonction de la fréquence d’excitation conduit à l’extraction de l’impédance thermique. Les résultats de mesures ont été validés par les simulations électriques. Des études complémentaires ont été réalisées pour l’identification des effets de pièges en utilisant différentes méthodes permettant l’extraction de la signature des pièges. La réalisation des modèles non-linéaires est présentée pour les transistors HEMT AlGaN/GaN et InAIN/GaN pour des applications d’amplificateur de puissance dans les bandes de fréquences X et K. / This report is devoted to the development of a new measurement bench for thermal impedance characterization of GaN HEMTs. This measurement test set uses the so-called « 3ω » technique, which consists to measure the electrical signal at third harmonic real image of the thermal magnitude variations of the device. A sweep in function of the excitation frequency allows extracting of the thermal impedance. The measurement results have been validated by electrical simulation. Other complementary studies were performed to identify the trapping effects using different methods to extract the traps signature. The realization of nonlinear models is presented for AlGaN HEMT / GaN and InAIN / GaN to the power amplification applications in frequency bands X and K.

This work intends to enhance the state of the research in power cycling tests with statements on achievable measurement accuracy, proposed test bench topologies and recommendations on improved test strategies for various types of semiconductor power devices. Chapters 1 and 2 describe the current state of the power cycling tests in the context of design for reliability comprising applicable standards and lifetime models. Measurement methods in power cycling tests for the essential physical parameters are explained in chapter 3. The dynamic and static measurement accuracy of voltage, current and temperature are discussed. The feasibly achievable measurement delay tmd of the maximal junction temperature Tjmax, its consequences on accuracy and methods to extrapolate to the time point of the turn-off event are explained. A method to characterize the thermal path of devices to the heatsink via measurements of the thermal impedance Zth is explained. Test bench topologies starting from standard setups, single to multi leg DC benches are discussed in chapter 4. Three application-closer setups implemented by the author are explained. For tests on thyristors a test concept with truncated sinusoidal current waveforms and online temperature measurement is introduced. An inverter-like topology with actively switching IGBTs is presented. In contrast to standard setups, there the devices under test prove switching capability until reaching the end-of-life criteria. Finally, a high frequency switching topology with low DC-link voltage and switching losses contributing significantly to the overall power losses is presented providing new degrees of freedom for setting test conditions. The particularities of semiconductor power devices in power cycling tests are thematized in chapter 5. The first part describes standard packages and addressed failure mechanisms in power cycling. For all relevant power electronic devices in silicon and silicon carbide, the devices’ characteristics, methods for power cycling and their consequences for test results are explained. The work is concluded and suggestions for future work are given in chapter 6.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 257 / Diese Arbeit bereichert den Stand der Wissenschaft auf dem Gebiet von Lastwechseltests mit Beiträgen zu verbesserter Messgenauigkeit, vorgeschlagenen Teststandstopologien und verbesserten Teststrategien für verschiedene Arten von leistungselektronischen Bauelementen. Kurzgefasst der Methodik von Lastwechseltests. Das erste Themengebiet in Kapitel 1 und Kapitel 2 beschreibt den aktuellen Stand zu Lastwechseltests im Kontext von Design für Zuverlässigkeit, welcher in anzuwendenden Standards und publizierten Lebensdauermodellen dokumentiert ist. Messmethoden für relevante physikalische Parameter in Lastwechseltests sind in Kapitel 3. erläutert. Zunächst werden dynamische und statische Messgenauigkeit für Spannung, Strom und Temperaturen diskutiert. Die tatsächlich erreichbare Messverzögerung tMD der maximalen Sperrschichttemperatur Tjmax und deren Auswirkung auf die Messgenauigkeit der Lastwechselfestigkeit wird dargelegt. Danach werden Methoden zur Rückextrapolation zum Zeitpunkt des Abschaltvorgangs des Laststroms diskutiert. Schließlich wird die Charakterisierung des Wärmepfads vom Bauelement zur Wärmesenke mittels Messung der thermischen Impedanz Zth behandelt. In Kapitel 4 werden Teststandstopologien beginnend mit standardmäßig genutzten ein- und mehrsträngigen DC-Testständen vorgestellt. Drei vom Autor umgesetzte anwendungsnahe Topologien werden erklärt. Für Tests mit Thyristoren wird ein Testkonzept mit angeschnittenem sinusförmigem Strom und in situ Messung der Sperrschichttemperatur eingeführt. Eine umrichterähnliche Topologie mit aktiv schaltenden IGBTs wird vorgestellt. Zuletzt wird eine Topologie mit hoch frequent schaltenden Prüflingen an niedriger Gleichspannung bei der Schaltverluste signifikant zur Erwärmung der Prüflinge beitragen vorgestellt. Dies ermöglicht neue Freiheitsgrade um Testbedingungen zu wählen. Die Besonderheiten von leistungselektronischen Bauelementen werden in Kapitel 5 thematisiert. Der erste Teil beschreibt Gehäusetypen und adressierte Fehlermechanismen in Lastwechseltests. Für alle untersuchten Bauelementtypen in Silizium und Siliziumkarbid werden Charakteristiken, empfohlene Methoden für Lastwechseltests und Einflüsse auf Testergebnisse erklärt. Die Arbeit wird in Kapitel 6 zusammengefasst und Vorschläge zu künftigen Arbeiten werden unterbreitet.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 257

CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / O câncer de mama é um problema de saúde pública e possui a maior incidência e mortalidade na população feminina em todo o mundo. A detecção precoce do câncer de mama é essencial para redução da morbidade e mortalidade associadas a esta doença. Alguns dos métodos usados para detecção dos tumores mamários são a ultrassonografia, a imagem por ressonância magnética (MRI), a tomografia por emissão de pósitrons (PET), a tomossíntese e a mamografia, recomendada como técnica de rastreamento. Cada um dos métodos apresenta vantagens e desvantagens, como provocar desconforto ao paciente durante a realização dos exames, possíveis reações ao agente de contraste, emissão de radiação, dependência do operador para análise dos resultados, dificuldade de detecção em tecidos densos, falta de acessibilidade para pessoas com deficiência ou baixa mobilidade, alto custo e produção de rejeitos radioativos. O objetivo principal deste trabalho é aplicar os métodos de impedância eletromecânica e térmica na detecção de inclusões para que possam ser futuramente usados como técnicas alternativas às já existentes na identificação de tumores mamários. A aplicação do método da impedância eletromecânica que utiliza transdutores piezelétricos, atuando simultaneamente como sensor e atuador, acoplados à estrutura analisada permite o monitoramento das mudanças da massa, rigidez e/ou amortecimento e a consequente detecção da inclusão. O mesmo procedimento é aplicado no método da impedância térmica que, por sua vez, consiste na razão entre a variação da resposta da temperatura superficial da estrutura em função da aplicação de um fluxo de calor externo. A detecção das inclusões torna-se possível devido a definições de métricas de dano que são parâmetros estatísticos capazes de representar numericamente a diferença entre duas medições antes e após o dano. A metodologia proposta é validada experimentalmente através da aplicação em materiais hiperplásticos de geometria simples e complexa. Amostras de silicone e modelos de aplicação médica são analisadas. Os métodos de impedância propostos apontaram, preliminarmente, para uma maior sensibilidade da técnica a inclusões menores, de 10 mm de diâmetro para os testes realizados. Além disso, observou-se que o aquecimento externo imposto aos modelos e a presença de geração de calor nas inclusões auxiliou na detecção. Um teste qualitativo foi realizado in vivo para a análise do potencial de uso da impedância eletromecânica em aplicações clínicas. Este trabalho apresenta contribuições importantes, não só no campo da engenharia biomecânica, mas também na análise do comportamento estrutural, ampliando as aplicações de técnicas de dano em materiais hiperelásticos, assim como, propondo o uso da impedância térmica como um novo parâmetro para identificação de inclusões ou falhas estruturais em ensaios não destrutivos. / Breast cancer is a public health problem and has the highest incidence and mortality in the female population worldwide. Early detection of breast cancer is essential for reducing the morbidity and mortality associated with this disease. Some of the methods used to detect breast tumors are ultrasonography, magnetic resonance imaging (MRI), positron emission tomography (PET), tomosynthesis and mammography, which is recommended as a screening technique. Each method has its advantages and disadvantages, such as discomfort to the patient during the exams, possible reactions to the contrast agent, radiation emission, operator dependence for the analysis of results, difficulty for detection in dense tissues, lack of accessibility for people with disabilities or low mobility, high cost and radioactive waste production. The main objective of this work is to apply the electromechanical and thermal impedance methods in the detection of inclusions, in order to be used, in the future, as alternative techniques to those already existent for the identification of breast tumors. The application of the electromechanical impedance method using piezoelectric transducers, acting simultaneously as a sensor and actuator, coupled to the analyzed structure allows the monitoring of mass, rigidity and/or damping variations, and consequent detection of the inclusion. The same procedure is applied in the thermal impedance method, which consists of the ratio between the gradient of the surface temperature response of the structure as a function of the application of an external heat flow. The detection of inclusions is possible due to the damage metrics that are statistical parameters capable of numerically representing the difference between two measurements before and after the damage. The proposed methodology is validated experimentally through the application in hyperplastic materials of simple and complex geometry. Silicone samples and medical application models are analyzed. The proposed impedance methods preliminarily presented a higher sensitivity of the technique to smaller inclusions of 10 mm in diameter for the tests performed. In addition, it was observed that the external heating imposed on the models and the presence of heat generation in the inclusions aided in the detection. A qualitative test was performed in vivo to analyze the potential of the use of electromechanical impedance in clinical applications. This work presents important contributions not only in the field of biomechanical engineering, but also in the analysis of structural behavior, expanding the applications of damage techniques in hyperelastic materials, as well as proposing the use of thermal impedance as a new parameter for identification of inclusions or structural failures in nondestructive testing. / Tese (Doutorado)

Les environnements ont tendance à être plus sévères (plus chauds et quelquefois plus froids). À ce titre, l’électronique de puissance haute température est un enjeu majeur pour le futur. Concernant les technologies d’assemblage à haute température, les brasures haute température comme l'alliage 88Au/12Ge, 97Au/3Si et 5Sn/95Pb pourraient supporter ces niveaux de contraintes thermiques, qui sont actuellement développées pour répondre à ces exigences. Nous avons effectué les caractérisations électriques, mécaniques et thermomécaniques des matériaux d’assemblage. Une étude thermique a réalisée par des méthodes expérimentales et des simulations numériques, l’étude numérique est réalisée sous ANSYS dans le but d’estimer les influences des différents paramètres sur la performance thermique de l’assemblage. En plus, les cyclages thermiques passif de grande amplitude sont effectués pour analyser la fiabilité des modules de puissance dans ces conditions d’utilisation. / The environments tend to be more severe (hotter and sometimes colder). As such, the high temperature power electronics is a major challenge for the future. Concerning the technologies for high temperature assembly, high temperature brazing alloy as 88Au / 12Ge, 97Au / 3Si and 5Sn / 95Pb could support these levels of thermal stresses, which are being developed to answer these requirements. We performed the electric, mechanical and thermomechanical characterizations for the materials of assembly. A thermal study was realized by experimental methods and numerical simulations, the numerical study is carried out in ANSYS in order to estimate the influences of the various parameters on the thermal performance of the assembly. In addition, the passive thermal cycles of large amplitude are conducted to analyze the reliability of the power modules in these conditions.

L'électronique de puissance et particulièrement les systèmes de conversions deviennent un enjeu majeur de la transition énergétique et de l'avenir des transports. Les contraintes technico-économiques liées aux nouvelles applications impliquent une augmentation des densités de puissance au sein des modules tout en limitant leur coût et en conservant une robustesse satisfaisante. Aujourd'hui, des solutions semblent émerger grâce à des structures innovantes associées aux composants grands gap et à l'intégration tridimensionnelle. Ces solutions apportent cependant un certain nombre de contraintes liées aux interconnexions électrothermomécaniques (ETM). L'augmentation des niveaux de température permis par les composants grands gap et l'attrait du refroidissement double face offert par les assemblages 3D augmentent de manière importante les contraintes thermomécaniques et causent des problèmes de fiabilité. C'est pourquoi de nouvelles interconnexions ETM sont développées pour s'adapter aux nouvelles contraintes et rendre possible ce saut technologique. Cependant les outils permettant la caractérisation thermique et électrique de ces nouvelles interconnexions restent à développer. Les travaux présentés dans ce mémoire se portent sur le développement et la mise au point d'outils de caractérisation des interconnexions dans des assemblages 3D. La difficulté d'obtenir la température du composant au sein du boîtier nous a poussé à explorer deux voies permettant d'estimer la température de jonction (TJ). Premièrement par l'implantation de capteurs de température et de tension au coeur d'un composant de puissance grâce la réalisation d'une puce de test spécifique. Et deuxièmement, par l'observation de la réponse en température de composants fonctionnels faisant appel à l'utilisation d'un paramètre électrique thermosensible (PTS) du composant. Les deux pistes explorées mettent à profit des solutions spécifiques innovantes pour permettre des caractérisations thermique et électrique fines des assemblages d'électronique de puissance. / Power electronic and particularly conversion systems are becoming a major challenge for the future of energetic and transport systems. Technical and economic constraints related to new applications lead to an increase of module power densities while reducing cost and maintaining a good robustness. Today, solutions seem to emerge from innovative structures associated to wide band-gap semiconductors and three-dimensional integration. These solutions lead to many constraints in electro-thermo-mechanical (ETM) interconnection field. Temperature level rises allowed by wide band-gap semiconductors and attractiveness of double sided cooling provide by the 3D assemblies have significantly increase thermo-mechanical stresses and cause reliability problems. This is why new ETM interconnections are developed to facing those difficulties and enable this technological gap. However, thermal and electrical interconnections characterization tools need to be develop. Works presented in this thesis focuses on the development of tools for new interconnections characterization adapted to 3D package. The difficulty of obtaining the temperature of the component within the package has led us to explore two ways to estimate the junction temperature (TJ). In a first hand we integrate temperature and voltage sensors inside a power component in a clean room process thanks to the achievement of a specific thermal test chip (TTC). And in a second hand, by observing the temperature response of functional components, using a temperature-sensitive electrical parameter (TSEP). The both paths explored take advantage of innovative specific solutions to allow precise thermal and electrical characterization of power electronic assemblies.

Eine kompakte Integration der Leistungselektronik in einem Fahrzeuggetriebe des Hybridfahrzeugs stellt hohe Anforderungen an die Lastwechselfestigkeit der Halbleiter-Leistungsmodule. Gefordert wird die Auslegung für die Kühlmitteltemperatur von 125°C und für die Sperrschichttemperatur von 200°C. Für die Untersuchung der Lastwechselfestigkeit bei geforderten hohen Temperaturen werden neue Prüfstandskonzepte und Messmethoden vorgestellt. Mit realisierten Testständen wird die Lastwechselfestigkeit der neuen Aufbau- und Verbindungstechnologien „gehärtete Aluminiumbonddrähte”, „Diffusionslöten”, „Lötung mit vertikalen Strukturen” und „Niedertemperatur-Verbindungstechnik” untersucht. / High power density of the power electronics in a hybrid electric vehicle demands a high power cycling capability of the semiconductor power module. Requirements are: 125°C coolant and 200°C junction temperature. For the investigation of the power cycling capability at high temperatures new test benches and measurement methods are introduces. With realized methods the reliability of following new interconnection technologies is investigated: doped aluminium bond wires, diffusion soldering, solder layer with vertical microstructures, low temperature sinter technology.

Diese Arbeit beschäftigt sich mit drei verschiedenen Temperaturmessmethoden VCE, VGTH sowie über die Messung der thermsichen Impedanz mit 10ms langen Lastimpulsen und vergleicht die Messergebnisse mit zwei Simulatoren. Dabei wird ein Schaltungs- sowie ein Halbleitersimulator verwendet und das bisherige Simulationsmodell angepasst.